1 /* 2 * Emulation of Linux signals 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu.h" 21 #include "user-internals.h" 22 #include "signal-common.h" 23 #include "linux-user/trace.h" 24 25 /* Size of dummy stack frame allocated when calling signal handler. 26 See arch/powerpc/include/asm/ptrace.h. */ 27 #if defined(TARGET_PPC64) 28 #define SIGNAL_FRAMESIZE 128 29 #else 30 #define SIGNAL_FRAMESIZE 64 31 #endif 32 33 /* See arch/powerpc/include/asm/ucontext.h. Only used for 32-bit PPC; 34 on 64-bit PPC, sigcontext and mcontext are one and the same. */ 35 struct target_mcontext { 36 target_ulong mc_gregs[48]; 37 /* Includes fpscr. */ 38 uint64_t mc_fregs[33]; 39 40 #if defined(TARGET_PPC64) 41 /* Pointer to the vector regs */ 42 target_ulong v_regs; 43 /* 44 * On ppc64, this mcontext structure is naturally *unaligned*, 45 * or rather it is aligned on a 8 bytes boundary but not on 46 * a 16 byte boundary. This pad fixes it up. This is why we 47 * cannot use ppc_avr_t, which would force alignment. This is 48 * also why the vector regs are referenced in the ABI by the 49 * v_regs pointer above so any amount of padding can be added here. 50 */ 51 target_ulong pad; 52 /* VSCR and VRSAVE are saved separately. Also reserve space for VSX. */ 53 struct { 54 uint64_t altivec[34 + 16][2]; 55 } mc_vregs; 56 #else 57 target_ulong mc_pad[2]; 58 59 /* We need to handle Altivec and SPE at the same time, which no 60 kernel needs to do. Fortunately, the kernel defines this bit to 61 be Altivec-register-large all the time, rather than trying to 62 twiddle it based on the specific platform. */ 63 union { 64 /* SPE vector registers. One extra for SPEFSCR. */ 65 uint32_t spe[33]; 66 /* 67 * Altivec vector registers. One extra for VRSAVE. 68 * On ppc32, we are already aligned to 16 bytes. We could 69 * use ppc_avr_t, but choose to share the same type as ppc64. 70 */ 71 uint64_t altivec[33][2]; 72 } mc_vregs; 73 #endif 74 }; 75 76 /* See arch/powerpc/include/asm/sigcontext.h. */ 77 struct target_sigcontext { 78 target_ulong _unused[4]; 79 int32_t signal; 80 #if defined(TARGET_PPC64) 81 int32_t pad0; 82 #endif 83 target_ulong handler; 84 target_ulong oldmask; 85 target_ulong regs; /* struct pt_regs __user * */ 86 #if defined(TARGET_PPC64) 87 struct target_mcontext mcontext; 88 #endif 89 }; 90 91 /* Indices for target_mcontext.mc_gregs, below. 92 See arch/powerpc/include/asm/ptrace.h for details. */ 93 enum { 94 TARGET_PT_R0 = 0, 95 TARGET_PT_R1 = 1, 96 TARGET_PT_R2 = 2, 97 TARGET_PT_R3 = 3, 98 TARGET_PT_R4 = 4, 99 TARGET_PT_R5 = 5, 100 TARGET_PT_R6 = 6, 101 TARGET_PT_R7 = 7, 102 TARGET_PT_R8 = 8, 103 TARGET_PT_R9 = 9, 104 TARGET_PT_R10 = 10, 105 TARGET_PT_R11 = 11, 106 TARGET_PT_R12 = 12, 107 TARGET_PT_R13 = 13, 108 TARGET_PT_R14 = 14, 109 TARGET_PT_R15 = 15, 110 TARGET_PT_R16 = 16, 111 TARGET_PT_R17 = 17, 112 TARGET_PT_R18 = 18, 113 TARGET_PT_R19 = 19, 114 TARGET_PT_R20 = 20, 115 TARGET_PT_R21 = 21, 116 TARGET_PT_R22 = 22, 117 TARGET_PT_R23 = 23, 118 TARGET_PT_R24 = 24, 119 TARGET_PT_R25 = 25, 120 TARGET_PT_R26 = 26, 121 TARGET_PT_R27 = 27, 122 TARGET_PT_R28 = 28, 123 TARGET_PT_R29 = 29, 124 TARGET_PT_R30 = 30, 125 TARGET_PT_R31 = 31, 126 TARGET_PT_NIP = 32, 127 TARGET_PT_MSR = 33, 128 TARGET_PT_ORIG_R3 = 34, 129 TARGET_PT_CTR = 35, 130 TARGET_PT_LNK = 36, 131 TARGET_PT_XER = 37, 132 TARGET_PT_CCR = 38, 133 /* Yes, there are two registers with #39. One is 64-bit only. */ 134 TARGET_PT_MQ = 39, 135 TARGET_PT_SOFTE = 39, 136 TARGET_PT_TRAP = 40, 137 TARGET_PT_DAR = 41, 138 TARGET_PT_DSISR = 42, 139 TARGET_PT_RESULT = 43, 140 TARGET_PT_REGS_COUNT = 44 141 }; 142 143 144 struct target_ucontext { 145 target_ulong tuc_flags; 146 target_ulong tuc_link; /* ucontext_t __user * */ 147 struct target_sigaltstack tuc_stack; 148 #if !defined(TARGET_PPC64) 149 int32_t tuc_pad[7]; 150 target_ulong tuc_regs; /* struct mcontext __user * 151 points to uc_mcontext field */ 152 #endif 153 target_sigset_t tuc_sigmask; 154 #if defined(TARGET_PPC64) 155 target_sigset_t unused[15]; /* Allow for uc_sigmask growth */ 156 struct target_sigcontext tuc_sigcontext; 157 #else 158 int32_t tuc_maskext[30]; 159 int32_t tuc_pad2[3]; 160 struct target_mcontext tuc_mcontext; 161 #endif 162 }; 163 164 /* See arch/powerpc/kernel/signal_32.c. */ 165 struct target_sigframe { 166 struct target_sigcontext sctx; 167 struct target_mcontext mctx; 168 int32_t abigap[56]; 169 }; 170 171 #if defined(TARGET_PPC64) 172 173 #define TARGET_TRAMP_SIZE 6 174 175 struct target_rt_sigframe { 176 /* sys_rt_sigreturn requires the ucontext be the first field */ 177 struct target_ucontext uc; 178 target_ulong _unused[2]; 179 uint32_t trampoline[TARGET_TRAMP_SIZE]; 180 target_ulong pinfo; /* struct siginfo __user * */ 181 target_ulong puc; /* void __user * */ 182 struct target_siginfo info; 183 /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */ 184 char abigap[288]; 185 } __attribute__((aligned(16))); 186 187 #else 188 189 struct target_rt_sigframe { 190 struct target_siginfo info; 191 struct target_ucontext uc; 192 int32_t abigap[56]; 193 }; 194 195 #endif 196 197 #if defined(TARGET_PPC64) 198 199 struct target_func_ptr { 200 target_ulong entry; 201 target_ulong toc; 202 }; 203 204 #endif 205 206 /* See arch/powerpc/kernel/signal.c. */ 207 static target_ulong get_sigframe(struct target_sigaction *ka, 208 CPUPPCState *env, 209 int frame_size) 210 { 211 target_ulong oldsp; 212 213 oldsp = target_sigsp(get_sp_from_cpustate(env), ka); 214 215 return (oldsp - frame_size) & ~0xFUL; 216 } 217 218 #if ((defined(TARGET_WORDS_BIGENDIAN) && defined(HOST_WORDS_BIGENDIAN)) || \ 219 (!defined(HOST_WORDS_BIGENDIAN) && !defined(TARGET_WORDS_BIGENDIAN))) 220 #define PPC_VEC_HI 0 221 #define PPC_VEC_LO 1 222 #else 223 #define PPC_VEC_HI 1 224 #define PPC_VEC_LO 0 225 #endif 226 227 228 static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) 229 { 230 target_ulong msr = env->msr; 231 int i; 232 target_ulong ccr = 0; 233 234 /* In general, the kernel attempts to be intelligent about what it 235 needs to save for Altivec/FP/SPE registers. We don't care that 236 much, so we just go ahead and save everything. */ 237 238 /* Save general registers. */ 239 for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { 240 __put_user(env->gpr[i], &frame->mc_gregs[i]); 241 } 242 __put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]); 243 __put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]); 244 __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]); 245 __put_user(cpu_read_xer(env), &frame->mc_gregs[TARGET_PT_XER]); 246 247 for (i = 0; i < ARRAY_SIZE(env->crf); i++) { 248 ccr |= env->crf[i] << (32 - ((i + 1) * 4)); 249 } 250 __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); 251 252 /* Save Altivec registers if necessary. */ 253 if (env->insns_flags & PPC_ALTIVEC) { 254 uint32_t *vrsave; 255 for (i = 0; i < 32; i++) { 256 ppc_avr_t *avr = cpu_avr_ptr(env, i); 257 ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i]; 258 259 __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); 260 __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); 261 } 262 #if defined(TARGET_PPC64) 263 vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; 264 /* 64-bit needs to put a pointer to the vectors in the frame */ 265 __put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs); 266 #else 267 vrsave = (uint32_t *)&frame->mc_vregs.altivec[32]; 268 #endif 269 __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave); 270 } 271 272 #if defined(TARGET_PPC64) 273 /* Save VSX second halves */ 274 if (env->insns_flags2 & PPC2_VSX) { 275 uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; 276 for (i = 0; i < 32; i++) { 277 uint64_t *vsrl = cpu_vsrl_ptr(env, i); 278 __put_user(*vsrl, &vsregs[i]); 279 } 280 } 281 #endif 282 283 /* Save floating point registers. */ 284 if (env->insns_flags & PPC_FLOAT) { 285 for (i = 0; i < 32; i++) { 286 uint64_t *fpr = cpu_fpr_ptr(env, i); 287 __put_user(*fpr, &frame->mc_fregs[i]); 288 } 289 __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); 290 } 291 292 #if !defined(TARGET_PPC64) 293 /* Save SPE registers. The kernel only saves the high half. */ 294 if (env->insns_flags & PPC_SPE) { 295 for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { 296 __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); 297 } 298 __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); 299 } 300 #endif 301 302 /* Store MSR. */ 303 __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); 304 } 305 306 static void encode_trampoline(int sigret, uint32_t *tramp) 307 { 308 /* Set up the sigreturn trampoline: li r0,sigret; sc. */ 309 __put_user(0x38000000 | sigret, &tramp[0]); 310 __put_user(0x44000002, &tramp[1]); 311 } 312 313 static void restore_user_regs(CPUPPCState *env, 314 struct target_mcontext *frame, int sig) 315 { 316 target_ulong save_r2 = 0; 317 target_ulong msr; 318 target_ulong xer; 319 target_ulong ccr; 320 321 int i; 322 323 if (!sig) { 324 save_r2 = env->gpr[2]; 325 } 326 327 /* Restore general registers. */ 328 for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { 329 __get_user(env->gpr[i], &frame->mc_gregs[i]); 330 } 331 __get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]); 332 __get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]); 333 __get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]); 334 335 __get_user(xer, &frame->mc_gregs[TARGET_PT_XER]); 336 cpu_write_xer(env, xer); 337 338 __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]); 339 for (i = 0; i < ARRAY_SIZE(env->crf); i++) { 340 env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf; 341 } 342 343 if (!sig) { 344 env->gpr[2] = save_r2; 345 } 346 /* Restore MSR. */ 347 __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); 348 349 /* If doing signal return, restore the previous little-endian mode. */ 350 if (sig) { 351 ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | 352 (msr & (1ull << MSR_LE)))); 353 } 354 355 /* Restore Altivec registers if necessary. */ 356 if (env->insns_flags & PPC_ALTIVEC) { 357 ppc_avr_t *v_regs; 358 uint32_t *vrsave; 359 #if defined(TARGET_PPC64) 360 uint64_t v_addr; 361 /* 64-bit needs to recover the pointer to the vectors from the frame */ 362 __get_user(v_addr, &frame->v_regs); 363 v_regs = g2h(env_cpu(env), v_addr); 364 #else 365 v_regs = (ppc_avr_t *)frame->mc_vregs.altivec; 366 #endif 367 for (i = 0; i < 32; i++) { 368 ppc_avr_t *avr = cpu_avr_ptr(env, i); 369 ppc_avr_t *vreg = &v_regs[i]; 370 371 __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); 372 __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); 373 } 374 #if defined(TARGET_PPC64) 375 vrsave = (uint32_t *)&v_regs[33]; 376 #else 377 vrsave = (uint32_t *)&v_regs[32]; 378 #endif 379 __get_user(env->spr[SPR_VRSAVE], vrsave); 380 } 381 382 #if defined(TARGET_PPC64) 383 /* Restore VSX second halves */ 384 if (env->insns_flags2 & PPC2_VSX) { 385 uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; 386 for (i = 0; i < 32; i++) { 387 uint64_t *vsrl = cpu_vsrl_ptr(env, i); 388 __get_user(*vsrl, &vsregs[i]); 389 } 390 } 391 #endif 392 393 /* Restore floating point registers. */ 394 if (env->insns_flags & PPC_FLOAT) { 395 uint64_t fpscr; 396 for (i = 0; i < 32; i++) { 397 uint64_t *fpr = cpu_fpr_ptr(env, i); 398 __get_user(*fpr, &frame->mc_fregs[i]); 399 } 400 __get_user(fpscr, &frame->mc_fregs[32]); 401 env->fpscr = (uint32_t) fpscr; 402 } 403 404 #if !defined(TARGET_PPC64) 405 /* Save SPE registers. The kernel only saves the high half. */ 406 if (env->insns_flags & PPC_SPE) { 407 for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { 408 __get_user(env->gprh[i], &frame->mc_vregs.spe[i]); 409 } 410 __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]); 411 } 412 #endif 413 } 414 415 #if !defined(TARGET_PPC64) 416 void setup_frame(int sig, struct target_sigaction *ka, 417 target_sigset_t *set, CPUPPCState *env) 418 { 419 struct target_sigframe *frame; 420 struct target_sigcontext *sc; 421 target_ulong frame_addr, newsp; 422 int err = 0; 423 424 frame_addr = get_sigframe(ka, env, sizeof(*frame)); 425 trace_user_setup_frame(env, frame_addr); 426 if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1)) 427 goto sigsegv; 428 sc = &frame->sctx; 429 430 __put_user(ka->_sa_handler, &sc->handler); 431 __put_user(set->sig[0], &sc->oldmask); 432 __put_user(set->sig[1], &sc->_unused[3]); 433 __put_user(h2g(&frame->mctx), &sc->regs); 434 __put_user(sig, &sc->signal); 435 436 /* Save user regs. */ 437 save_user_regs(env, &frame->mctx); 438 439 env->lr = default_sigreturn; 440 441 /* Turn off all fp exceptions. */ 442 env->fpscr = 0; 443 444 /* Create a stack frame for the caller of the handler. */ 445 newsp = frame_addr - SIGNAL_FRAMESIZE; 446 err |= put_user(env->gpr[1], newsp, target_ulong); 447 448 if (err) 449 goto sigsegv; 450 451 /* Set up registers for signal handler. */ 452 env->gpr[1] = newsp; 453 env->gpr[3] = sig; 454 env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx); 455 456 env->nip = (target_ulong) ka->_sa_handler; 457 458 /* Signal handlers are entered in big-endian mode. */ 459 ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); 460 461 unlock_user_struct(frame, frame_addr, 1); 462 return; 463 464 sigsegv: 465 unlock_user_struct(frame, frame_addr, 1); 466 force_sigsegv(sig); 467 } 468 #endif /* !defined(TARGET_PPC64) */ 469 470 void setup_rt_frame(int sig, struct target_sigaction *ka, 471 target_siginfo_t *info, 472 target_sigset_t *set, CPUPPCState *env) 473 { 474 struct target_rt_sigframe *rt_sf; 475 struct target_mcontext *mctx = 0; 476 target_ulong rt_sf_addr, newsp = 0; 477 int i, err = 0; 478 #if defined(TARGET_PPC64) 479 struct target_sigcontext *sc = 0; 480 struct image_info *image = ((TaskState *)thread_cpu->opaque)->info; 481 #endif 482 483 rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf)); 484 if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1)) 485 goto sigsegv; 486 487 tswap_siginfo(&rt_sf->info, info); 488 489 __put_user(0, &rt_sf->uc.tuc_flags); 490 __put_user(0, &rt_sf->uc.tuc_link); 491 target_save_altstack(&rt_sf->uc.tuc_stack, env); 492 #if !defined(TARGET_PPC64) 493 __put_user(h2g (&rt_sf->uc.tuc_mcontext), 494 &rt_sf->uc.tuc_regs); 495 #endif 496 for(i = 0; i < TARGET_NSIG_WORDS; i++) { 497 __put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]); 498 } 499 500 #if defined(TARGET_PPC64) 501 mctx = &rt_sf->uc.tuc_sigcontext.mcontext; 502 503 sc = &rt_sf->uc.tuc_sigcontext; 504 __put_user(h2g(mctx), &sc->regs); 505 __put_user(sig, &sc->signal); 506 #else 507 mctx = &rt_sf->uc.tuc_mcontext; 508 #endif 509 510 save_user_regs(env, mctx); 511 512 env->lr = default_rt_sigreturn; 513 514 /* Turn off all fp exceptions. */ 515 env->fpscr = 0; 516 517 /* Create a stack frame for the caller of the handler. */ 518 newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + 16); 519 err |= put_user(env->gpr[1], newsp, target_ulong); 520 521 if (err) 522 goto sigsegv; 523 524 /* Set up registers for signal handler. */ 525 env->gpr[1] = newsp; 526 env->gpr[3] = (target_ulong) sig; 527 env->gpr[4] = (target_ulong) h2g(&rt_sf->info); 528 env->gpr[5] = (target_ulong) h2g(&rt_sf->uc); 529 env->gpr[6] = (target_ulong) h2g(rt_sf); 530 531 #if defined(TARGET_PPC64) 532 if (get_ppc64_abi(image) < 2) { 533 /* ELFv1 PPC64 function pointers are pointers to OPD entries. */ 534 struct target_func_ptr *handler = 535 (struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler); 536 env->nip = tswapl(handler->entry); 537 env->gpr[2] = tswapl(handler->toc); 538 } else { 539 /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */ 540 env->gpr[12] = env->nip = ka->_sa_handler; 541 } 542 #else 543 env->nip = (target_ulong) ka->_sa_handler; 544 #endif 545 546 #ifdef TARGET_WORDS_BIGENDIAN 547 /* Signal handlers are entered in big-endian mode. */ 548 ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); 549 #else 550 /* Signal handlers are entered in little-endian mode. */ 551 ppc_store_msr(env, env->msr | (1ull << MSR_LE)); 552 #endif 553 554 unlock_user_struct(rt_sf, rt_sf_addr, 1); 555 return; 556 557 sigsegv: 558 unlock_user_struct(rt_sf, rt_sf_addr, 1); 559 force_sigsegv(sig); 560 561 } 562 563 #if !defined(TARGET_PPC64) 564 long do_sigreturn(CPUPPCState *env) 565 { 566 struct target_sigcontext *sc = NULL; 567 struct target_mcontext *sr = NULL; 568 target_ulong sr_addr = 0, sc_addr; 569 sigset_t blocked; 570 target_sigset_t set; 571 572 sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE; 573 if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1)) 574 goto sigsegv; 575 576 __get_user(set.sig[0], &sc->oldmask); 577 __get_user(set.sig[1], &sc->_unused[3]); 578 579 target_to_host_sigset_internal(&blocked, &set); 580 set_sigmask(&blocked); 581 582 __get_user(sr_addr, &sc->regs); 583 if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1)) 584 goto sigsegv; 585 restore_user_regs(env, sr, 1); 586 587 unlock_user_struct(sr, sr_addr, 1); 588 unlock_user_struct(sc, sc_addr, 1); 589 return -QEMU_ESIGRETURN; 590 591 sigsegv: 592 unlock_user_struct(sr, sr_addr, 1); 593 unlock_user_struct(sc, sc_addr, 1); 594 force_sig(TARGET_SIGSEGV); 595 return -QEMU_ESIGRETURN; 596 } 597 #endif /* !defined(TARGET_PPC64) */ 598 599 /* See arch/powerpc/kernel/signal_32.c. */ 600 static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig) 601 { 602 struct target_mcontext *mcp; 603 target_ulong mcp_addr; 604 sigset_t blocked; 605 target_sigset_t set; 606 607 if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask), 608 sizeof (set))) 609 return 1; 610 611 #if defined(TARGET_PPC64) 612 mcp_addr = h2g(ucp) + 613 offsetof(struct target_ucontext, tuc_sigcontext.mcontext); 614 #else 615 __get_user(mcp_addr, &ucp->tuc_regs); 616 #endif 617 618 if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1)) 619 return 1; 620 621 target_to_host_sigset_internal(&blocked, &set); 622 set_sigmask(&blocked); 623 restore_user_regs(env, mcp, sig); 624 625 unlock_user_struct(mcp, mcp_addr, 1); 626 return 0; 627 } 628 629 long do_rt_sigreturn(CPUPPCState *env) 630 { 631 struct target_rt_sigframe *rt_sf = NULL; 632 target_ulong rt_sf_addr; 633 634 rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + 16; 635 if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1)) 636 goto sigsegv; 637 638 if (do_setcontext(&rt_sf->uc, env, 1)) 639 goto sigsegv; 640 641 target_restore_altstack(&rt_sf->uc.tuc_stack, env); 642 643 unlock_user_struct(rt_sf, rt_sf_addr, 1); 644 return -QEMU_ESIGRETURN; 645 646 sigsegv: 647 unlock_user_struct(rt_sf, rt_sf_addr, 1); 648 force_sig(TARGET_SIGSEGV); 649 return -QEMU_ESIGRETURN; 650 } 651 652 /* This syscall implements {get,set,swap}context for userland. */ 653 abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx, 654 abi_ulong unew_ctx, abi_long ctx_size) 655 { 656 struct target_ucontext *uctx; 657 struct target_mcontext *mctx; 658 659 /* For ppc32, ctx_size is "reserved for future use". 660 * For ppc64, we do not yet support the VSX extension. 661 */ 662 if (ctx_size < sizeof(struct target_ucontext)) { 663 return -TARGET_EINVAL; 664 } 665 666 if (uold_ctx) { 667 TaskState *ts = (TaskState *)thread_cpu->opaque; 668 669 if (!lock_user_struct(VERIFY_WRITE, uctx, uold_ctx, 1)) { 670 return -TARGET_EFAULT; 671 } 672 673 #ifdef TARGET_PPC64 674 mctx = &uctx->tuc_sigcontext.mcontext; 675 #else 676 /* ??? The kernel aligns the pointer down here into padding, but 677 * in setup_rt_frame we don't. Be self-compatible for now. 678 */ 679 mctx = &uctx->tuc_mcontext; 680 __put_user(h2g(mctx), &uctx->tuc_regs); 681 #endif 682 683 save_user_regs(env, mctx); 684 host_to_target_sigset(&uctx->tuc_sigmask, &ts->signal_mask); 685 686 unlock_user_struct(uctx, uold_ctx, 1); 687 } 688 689 if (unew_ctx) { 690 int err; 691 692 if (!lock_user_struct(VERIFY_READ, uctx, unew_ctx, 1)) { 693 return -TARGET_EFAULT; 694 } 695 err = do_setcontext(uctx, env, 0); 696 unlock_user_struct(uctx, unew_ctx, 1); 697 698 if (err) { 699 /* We cannot return to a partially updated context. */ 700 force_sig(TARGET_SIGSEGV); 701 } 702 return -QEMU_ESIGRETURN; 703 } 704 705 return 0; 706 } 707 708 void setup_sigtramp(abi_ulong sigtramp_page) 709 { 710 uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 2 * 8, 0); 711 assert(tramp != NULL); 712 713 #ifdef TARGET_ARCH_HAS_SETUP_FRAME 714 default_sigreturn = sigtramp_page; 715 encode_trampoline(TARGET_NR_sigreturn, tramp + 0); 716 #endif 717 718 default_rt_sigreturn = sigtramp_page + 8; 719 encode_trampoline(TARGET_NR_rt_sigreturn, tramp + 2); 720 721 unlock_user(tramp, sigtramp_page, 2 * 8); 722 } 723