1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu.h" 23 #include "cpu_loop-common.h" 24 #include "elf.h" 25 #include "internal.h" 26 27 # ifdef TARGET_ABI_MIPSO32 28 # define MIPS_SYSCALL_NUMBER_UNUSED -1 29 static const int8_t mips_syscall_args[] = { 30 #include "syscall-args-o32.c.inc" 31 }; 32 # endif /* O32 */ 33 34 /* Break codes */ 35 enum { 36 BRK_OVERFLOW = 6, 37 BRK_DIVZERO = 7 38 }; 39 40 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 41 unsigned int code) 42 { 43 int ret = -1; 44 45 switch (code) { 46 case BRK_OVERFLOW: 47 case BRK_DIVZERO: 48 info->si_signo = TARGET_SIGFPE; 49 info->si_errno = 0; 50 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 51 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 52 ret = 0; 53 break; 54 default: 55 info->si_signo = TARGET_SIGTRAP; 56 info->si_errno = 0; 57 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 58 ret = 0; 59 break; 60 } 61 62 return ret; 63 } 64 65 void cpu_loop(CPUMIPSState *env) 66 { 67 CPUState *cs = env_cpu(env); 68 target_siginfo_t info; 69 int trapnr; 70 abi_long ret; 71 # ifdef TARGET_ABI_MIPSO32 72 unsigned int syscall_num; 73 # endif 74 75 for(;;) { 76 cpu_exec_start(cs); 77 trapnr = cpu_exec(cs); 78 cpu_exec_end(cs); 79 process_queued_cpu_work(cs); 80 81 switch(trapnr) { 82 case EXCP_SYSCALL: 83 env->active_tc.PC += 4; 84 # ifdef TARGET_ABI_MIPSO32 85 syscall_num = env->active_tc.gpr[2] - 4000; 86 if (syscall_num >= sizeof(mips_syscall_args)) { 87 /* syscall_num is larger that any defined for MIPS O32 */ 88 ret = -TARGET_ENOSYS; 89 } else if (mips_syscall_args[syscall_num] == 90 MIPS_SYSCALL_NUMBER_UNUSED) { 91 /* syscall_num belongs to the range not defined for MIPS O32 */ 92 ret = -TARGET_ENOSYS; 93 } else { 94 /* syscall_num is valid */ 95 int nb_args; 96 abi_ulong sp_reg; 97 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 98 99 nb_args = mips_syscall_args[syscall_num]; 100 sp_reg = env->active_tc.gpr[29]; 101 switch (nb_args) { 102 /* these arguments are taken from the stack */ 103 case 8: 104 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 105 goto done_syscall; 106 } 107 /* fall through */ 108 case 7: 109 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 110 goto done_syscall; 111 } 112 /* fall through */ 113 case 6: 114 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 115 goto done_syscall; 116 } 117 /* fall through */ 118 case 5: 119 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 120 goto done_syscall; 121 } 122 /* fall through */ 123 default: 124 break; 125 } 126 ret = do_syscall(env, env->active_tc.gpr[2], 127 env->active_tc.gpr[4], 128 env->active_tc.gpr[5], 129 env->active_tc.gpr[6], 130 env->active_tc.gpr[7], 131 arg5, arg6, arg7, arg8); 132 } 133 done_syscall: 134 # else 135 ret = do_syscall(env, env->active_tc.gpr[2], 136 env->active_tc.gpr[4], env->active_tc.gpr[5], 137 env->active_tc.gpr[6], env->active_tc.gpr[7], 138 env->active_tc.gpr[8], env->active_tc.gpr[9], 139 env->active_tc.gpr[10], env->active_tc.gpr[11]); 140 # endif /* O32 */ 141 if (ret == -TARGET_ERESTARTSYS) { 142 env->active_tc.PC -= 4; 143 break; 144 } 145 if (ret == -TARGET_QEMU_ESIGRETURN) { 146 /* Returning from a successful sigreturn syscall. 147 Avoid clobbering register state. */ 148 break; 149 } 150 if ((abi_ulong)ret >= (abi_ulong)-1133) { 151 env->active_tc.gpr[7] = 1; /* error flag */ 152 ret = -ret; 153 } else { 154 env->active_tc.gpr[7] = 0; /* error flag */ 155 } 156 env->active_tc.gpr[2] = ret; 157 break; 158 case EXCP_TLBL: 159 case EXCP_TLBS: 160 case EXCP_AdEL: 161 case EXCP_AdES: 162 info.si_signo = TARGET_SIGSEGV; 163 info.si_errno = 0; 164 /* XXX: check env->error_code */ 165 info.si_code = TARGET_SEGV_MAPERR; 166 info._sifields._sigfault._addr = env->CP0_BadVAddr; 167 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 168 break; 169 case EXCP_CpU: 170 case EXCP_RI: 171 info.si_signo = TARGET_SIGILL; 172 info.si_errno = 0; 173 info.si_code = 0; 174 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 175 break; 176 case EXCP_INTERRUPT: 177 /* just indicate that signals should be handled asap */ 178 break; 179 case EXCP_DEBUG: 180 info.si_signo = TARGET_SIGTRAP; 181 info.si_errno = 0; 182 info.si_code = TARGET_TRAP_BRKPT; 183 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 184 break; 185 case EXCP_DSPDIS: 186 info.si_signo = TARGET_SIGILL; 187 info.si_errno = 0; 188 info.si_code = TARGET_ILL_ILLOPC; 189 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 190 break; 191 case EXCP_FPE: 192 info.si_signo = TARGET_SIGFPE; 193 info.si_errno = 0; 194 info.si_code = TARGET_FPE_FLTUNK; 195 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { 196 info.si_code = TARGET_FPE_FLTINV; 197 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { 198 info.si_code = TARGET_FPE_FLTDIV; 199 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { 200 info.si_code = TARGET_FPE_FLTOVF; 201 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) { 202 info.si_code = TARGET_FPE_FLTUND; 203 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { 204 info.si_code = TARGET_FPE_FLTRES; 205 } 206 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 207 break; 208 /* The code below was inspired by the MIPS Linux kernel trap 209 * handling code in arch/mips/kernel/traps.c. 210 */ 211 case EXCP_BREAK: 212 { 213 abi_ulong trap_instr; 214 unsigned int code; 215 216 if (env->hflags & MIPS_HFLAG_M16) { 217 if (env->insn_flags & ASE_MICROMIPS) { 218 /* microMIPS mode */ 219 ret = get_user_u16(trap_instr, env->active_tc.PC); 220 if (ret != 0) { 221 goto error; 222 } 223 224 if ((trap_instr >> 10) == 0x11) { 225 /* 16-bit instruction */ 226 code = trap_instr & 0xf; 227 } else { 228 /* 32-bit instruction */ 229 abi_ulong instr_lo; 230 231 ret = get_user_u16(instr_lo, 232 env->active_tc.PC + 2); 233 if (ret != 0) { 234 goto error; 235 } 236 trap_instr = (trap_instr << 16) | instr_lo; 237 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 238 /* Unfortunately, microMIPS also suffers from 239 the old assembler bug... */ 240 if (code >= (1 << 10)) { 241 code >>= 10; 242 } 243 } 244 } else { 245 /* MIPS16e mode */ 246 ret = get_user_u16(trap_instr, env->active_tc.PC); 247 if (ret != 0) { 248 goto error; 249 } 250 code = (trap_instr >> 6) & 0x3f; 251 } 252 } else { 253 ret = get_user_u32(trap_instr, env->active_tc.PC); 254 if (ret != 0) { 255 goto error; 256 } 257 258 /* As described in the original Linux kernel code, the 259 * below checks on 'code' are to work around an old 260 * assembly bug. 261 */ 262 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 263 if (code >= (1 << 10)) { 264 code >>= 10; 265 } 266 } 267 268 if (do_break(env, &info, code) != 0) { 269 goto error; 270 } 271 } 272 break; 273 case EXCP_TRAP: 274 { 275 abi_ulong trap_instr; 276 unsigned int code = 0; 277 278 if (env->hflags & MIPS_HFLAG_M16) { 279 /* microMIPS mode */ 280 abi_ulong instr[2]; 281 282 ret = get_user_u16(instr[0], env->active_tc.PC) || 283 get_user_u16(instr[1], env->active_tc.PC + 2); 284 285 trap_instr = (instr[0] << 16) | instr[1]; 286 } else { 287 ret = get_user_u32(trap_instr, env->active_tc.PC); 288 } 289 290 if (ret != 0) { 291 goto error; 292 } 293 294 /* The immediate versions don't provide a code. */ 295 if (!(trap_instr & 0xFC000000)) { 296 if (env->hflags & MIPS_HFLAG_M16) { 297 /* microMIPS mode */ 298 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 299 } else { 300 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 301 } 302 } 303 304 if (do_break(env, &info, code) != 0) { 305 goto error; 306 } 307 } 308 break; 309 case EXCP_ATOMIC: 310 cpu_exec_step_atomic(cs); 311 break; 312 default: 313 error: 314 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 315 abort(); 316 } 317 process_pending_signals(env); 318 } 319 } 320 321 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 322 { 323 CPUState *cpu = env_cpu(env); 324 TaskState *ts = cpu->opaque; 325 struct image_info *info = ts->info; 326 int i; 327 328 struct mode_req { 329 bool single; 330 bool soft; 331 bool fr1; 332 bool frdefault; 333 bool fre; 334 }; 335 336 static const struct mode_req fpu_reqs[] = { 337 [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, 338 [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, 339 [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, 340 [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, 341 [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, 342 [MIPS_ABI_FP_XX] = { false, false, true, true, true }, 343 [MIPS_ABI_FP_64] = { false, false, true, false, false }, 344 [MIPS_ABI_FP_64A] = { false, false, true, false, true } 345 }; 346 347 /* 348 * Mode requirements when .MIPS.abiflags is not present in the ELF. 349 * Not present means that everything is acceptable except FR1. 350 */ 351 static struct mode_req none_req = { true, true, false, true, true }; 352 353 struct mode_req prog_req; 354 struct mode_req interp_req; 355 356 for(i = 0; i < 32; i++) { 357 env->active_tc.gpr[i] = regs->regs[i]; 358 } 359 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 360 if (regs->cp0_epc & 1) { 361 env->hflags |= MIPS_HFLAG_M16; 362 } 363 364 #ifdef TARGET_ABI_MIPSO32 365 # define MAX_FP_ABI MIPS_ABI_FP_64A 366 #else 367 # define MAX_FP_ABI MIPS_ABI_FP_SOFT 368 #endif 369 if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN) 370 || (info->interp_fp_abi > MAX_FP_ABI && 371 info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) { 372 fprintf(stderr, "qemu: Unexpected FPU mode\n"); 373 exit(1); 374 } 375 376 prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req 377 : fpu_reqs[info->fp_abi]; 378 interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req 379 : fpu_reqs[info->interp_fp_abi]; 380 381 prog_req.single &= interp_req.single; 382 prog_req.soft &= interp_req.soft; 383 prog_req.fr1 &= interp_req.fr1; 384 prog_req.frdefault &= interp_req.frdefault; 385 prog_req.fre &= interp_req.fre; 386 387 bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || 388 env->insn_flags & ISA_MIPS64R2 || 389 env->insn_flags & ISA_MIPS32R6 || 390 env->insn_flags & ISA_MIPS64R6; 391 392 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { 393 env->CP0_Config5 |= (1 << CP0C5_FRE); 394 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 395 env->hflags |= MIPS_HFLAG_FRE; 396 } 397 } else if ((prog_req.fr1 && prog_req.frdefault) || 398 (prog_req.single && !prog_req.frdefault)) { 399 if ((env->active_fpu.fcr0 & (1 << FCR0_F64) 400 && cpu_has_mips_r2_r6) || prog_req.fr1) { 401 env->CP0_Status |= (1 << CP0St_FR); 402 env->hflags |= MIPS_HFLAG_F64; 403 } 404 } else if (!prog_req.fre && !prog_req.frdefault && 405 !prog_req.fr1 && !prog_req.single && !prog_req.soft) { 406 fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); 407 exit(1); 408 } 409 410 if (env->insn_flags & ISA_NANOMIPS32) { 411 return; 412 } 413 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != 414 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { 415 if ((env->active_fpu.fcr31_rw_bitmask & 416 (1 << FCR31_NAN2008)) == 0) { 417 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); 418 exit(1); 419 } 420 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { 421 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); 422 } else { 423 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); 424 } 425 restore_snan_bit_mode(env); 426 } 427 } 428