1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "cpu_loop-common.h" 24 #include "signal-common.h" 25 #include "elf.h" 26 #include "internal.h" 27 #include "fpu_helper.h" 28 29 # ifdef TARGET_ABI_MIPSO32 30 # define MIPS_SYSCALL_NUMBER_UNUSED -1 31 static const int8_t mips_syscall_args[] = { 32 #include "syscall-args-o32.c.inc" 33 }; 34 # endif /* O32 */ 35 36 /* Break codes */ 37 enum { 38 BRK_OVERFLOW = 6, 39 BRK_DIVZERO = 7 40 }; 41 42 static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap) 43 { 44 target_ulong pc = env->active_tc.PC; 45 46 switch (code) { 47 case BRK_OVERFLOW: 48 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc); 49 break; 50 case BRK_DIVZERO: 51 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc); 52 break; 53 default: 54 if (trap) { 55 force_sig(TARGET_SIGTRAP); 56 } else { 57 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc); 58 } 59 break; 60 } 61 } 62 63 void cpu_loop(CPUMIPSState *env) 64 { 65 CPUState *cs = env_cpu(env); 66 int trapnr, si_code; 67 unsigned int code; 68 abi_long ret; 69 # ifdef TARGET_ABI_MIPSO32 70 unsigned int syscall_num; 71 # endif 72 73 for(;;) { 74 cpu_exec_start(cs); 75 trapnr = cpu_exec(cs); 76 cpu_exec_end(cs); 77 process_queued_cpu_work(cs); 78 79 switch(trapnr) { 80 case EXCP_SYSCALL: 81 env->active_tc.PC += 4; 82 # ifdef TARGET_ABI_MIPSO32 83 syscall_num = env->active_tc.gpr[2] - 4000; 84 if (syscall_num >= sizeof(mips_syscall_args)) { 85 /* syscall_num is larger that any defined for MIPS O32 */ 86 ret = -TARGET_ENOSYS; 87 } else if (mips_syscall_args[syscall_num] == 88 MIPS_SYSCALL_NUMBER_UNUSED) { 89 /* syscall_num belongs to the range not defined for MIPS O32 */ 90 ret = -TARGET_ENOSYS; 91 } else { 92 /* syscall_num is valid */ 93 int nb_args; 94 abi_ulong sp_reg; 95 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 96 97 nb_args = mips_syscall_args[syscall_num]; 98 sp_reg = env->active_tc.gpr[29]; 99 switch (nb_args) { 100 /* these arguments are taken from the stack */ 101 case 8: 102 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 103 goto done_syscall; 104 } 105 /* fall through */ 106 case 7: 107 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 108 goto done_syscall; 109 } 110 /* fall through */ 111 case 6: 112 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 113 goto done_syscall; 114 } 115 /* fall through */ 116 case 5: 117 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 118 goto done_syscall; 119 } 120 /* fall through */ 121 default: 122 break; 123 } 124 ret = do_syscall(env, env->active_tc.gpr[2], 125 env->active_tc.gpr[4], 126 env->active_tc.gpr[5], 127 env->active_tc.gpr[6], 128 env->active_tc.gpr[7], 129 arg5, arg6, arg7, arg8); 130 } 131 done_syscall: 132 # else 133 ret = do_syscall(env, env->active_tc.gpr[2], 134 env->active_tc.gpr[4], env->active_tc.gpr[5], 135 env->active_tc.gpr[6], env->active_tc.gpr[7], 136 env->active_tc.gpr[8], env->active_tc.gpr[9], 137 env->active_tc.gpr[10], env->active_tc.gpr[11]); 138 # endif /* O32 */ 139 if (ret == -QEMU_ERESTARTSYS) { 140 env->active_tc.PC -= 4; 141 break; 142 } 143 if (ret == -QEMU_ESIGRETURN) { 144 /* Returning from a successful sigreturn syscall. 145 Avoid clobbering register state. */ 146 break; 147 } 148 if ((abi_ulong)ret >= (abi_ulong)-1133) { 149 env->active_tc.gpr[7] = 1; /* error flag */ 150 ret = -ret; 151 } else { 152 env->active_tc.gpr[7] = 0; /* error flag */ 153 } 154 env->active_tc.gpr[2] = ret; 155 break; 156 case EXCP_CpU: 157 case EXCP_RI: 158 case EXCP_DSPDIS: 159 force_sig(TARGET_SIGILL); 160 break; 161 case EXCP_INTERRUPT: 162 /* just indicate that signals should be handled asap */ 163 break; 164 case EXCP_DEBUG: 165 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, 166 env->active_tc.PC); 167 break; 168 case EXCP_FPE: 169 si_code = TARGET_FPE_FLTUNK; 170 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { 171 si_code = TARGET_FPE_FLTINV; 172 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) { 173 si_code = TARGET_FPE_FLTDIV; 174 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) { 175 si_code = TARGET_FPE_FLTOVF; 176 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) { 177 si_code = TARGET_FPE_FLTUND; 178 } else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) { 179 si_code = TARGET_FPE_FLTRES; 180 } 181 force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC); 182 break; 183 case EXCP_OVERFLOW: 184 force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->active_tc.PC); 185 break; 186 /* The code below was inspired by the MIPS Linux kernel trap 187 * handling code in arch/mips/kernel/traps.c. 188 */ 189 case EXCP_BREAK: 190 /* 191 * As described in the original Linux kernel code, the below 192 * checks on 'code' are to work around an old assembly bug. 193 */ 194 code = env->error_code; 195 if (code >= (1 << 10)) { 196 code >>= 10; 197 } 198 do_tr_or_bp(env, code, false); 199 break; 200 case EXCP_TRAP: 201 do_tr_or_bp(env, env->error_code, true); 202 break; 203 case EXCP_ATOMIC: 204 cpu_exec_step_atomic(cs); 205 break; 206 default: 207 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 208 abort(); 209 } 210 process_pending_signals(env); 211 } 212 } 213 214 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 215 { 216 CPUState *cpu = env_cpu(env); 217 TaskState *ts = get_task_state(cpu); 218 struct image_info *info = ts->info; 219 int i; 220 221 struct mode_req { 222 bool single; 223 bool soft; 224 bool fr1; 225 bool frdefault; 226 bool fre; 227 }; 228 229 static const struct mode_req fpu_reqs[] = { 230 [MIPS_ABI_FP_ANY] = { true, true, true, true, true }, 231 [MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true }, 232 [MIPS_ABI_FP_SINGLE] = { true, false, false, false, false }, 233 [MIPS_ABI_FP_SOFT] = { false, true, false, false, false }, 234 [MIPS_ABI_FP_OLD_64] = { false, false, false, false, false }, 235 [MIPS_ABI_FP_XX] = { false, false, true, true, true }, 236 [MIPS_ABI_FP_64] = { false, false, true, false, false }, 237 [MIPS_ABI_FP_64A] = { false, false, true, false, true } 238 }; 239 240 /* 241 * Mode requirements when .MIPS.abiflags is not present in the ELF. 242 * Not present means that everything is acceptable except FR1. 243 */ 244 static struct mode_req none_req = { true, true, false, true, true }; 245 246 struct mode_req prog_req; 247 struct mode_req interp_req; 248 249 for(i = 0; i < 32; i++) { 250 env->active_tc.gpr[i] = regs->regs[i]; 251 } 252 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 253 if (regs->cp0_epc & 1) { 254 env->hflags |= MIPS_HFLAG_M16; 255 } 256 257 #ifdef TARGET_ABI_MIPSO32 258 # define MAX_FP_ABI MIPS_ABI_FP_64A 259 #else 260 # define MAX_FP_ABI MIPS_ABI_FP_SOFT 261 #endif 262 if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN) 263 || (info->interp_fp_abi > MAX_FP_ABI && 264 info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) { 265 fprintf(stderr, "qemu: Unexpected FPU mode\n"); 266 exit(1); 267 } 268 269 prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req 270 : fpu_reqs[info->fp_abi]; 271 interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req 272 : fpu_reqs[info->interp_fp_abi]; 273 274 prog_req.single &= interp_req.single; 275 prog_req.soft &= interp_req.soft; 276 prog_req.fr1 &= interp_req.fr1; 277 prog_req.frdefault &= interp_req.frdefault; 278 prog_req.fre &= interp_req.fre; 279 280 bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 || 281 env->insn_flags & ISA_MIPS_R6; 282 283 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { 284 env->CP0_Config5 |= (1 << CP0C5_FRE); 285 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { 286 env->hflags |= MIPS_HFLAG_FRE; 287 } 288 } else if ((prog_req.fr1 && prog_req.frdefault) || 289 (prog_req.single && !prog_req.frdefault)) { 290 if ((env->active_fpu.fcr0 & (1 << FCR0_F64) 291 && cpu_has_mips_r2_r6) || prog_req.fr1) { 292 env->CP0_Status |= (1 << CP0St_FR); 293 env->hflags |= MIPS_HFLAG_F64; 294 } 295 } else if (prog_req.fr1) { 296 env->CP0_Status |= (1 << CP0St_FR); 297 env->hflags |= MIPS_HFLAG_F64; 298 } else if (!prog_req.fre && !prog_req.frdefault && 299 !prog_req.fr1 && !prog_req.single && !prog_req.soft) { 300 fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); 301 exit(1); 302 } 303 304 if (env->insn_flags & ISA_NANOMIPS32) { 305 return; 306 } 307 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != 308 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { 309 if ((env->active_fpu.fcr31_rw_bitmask & 310 (1 << FCR31_NAN2008)) == 0) { 311 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); 312 exit(1); 313 } 314 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { 315 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); 316 } else { 317 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); 318 } 319 restore_snan_bit_mode(env); 320 } 321 } 322