1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <stdlib.h> 20 #include <stdio.h> 21 #include <stdarg.h> 22 #include <string.h> 23 #include <errno.h> 24 #include <unistd.h> 25 #include <sys/mman.h> 26 #include <sys/syscall.h> 27 #include <sys/resource.h> 28 29 #include "qemu.h" 30 #include "qemu-common.h" 31 #include "cache-utils.h" 32 /* For tb_lock */ 33 #include "exec-all.h" 34 #include "tcg.h" 35 #include "qemu-timer.h" 36 #include "envlist.h" 37 38 #define DEBUG_LOGFILE "/tmp/qemu.log" 39 40 char *exec_path; 41 42 int singlestep; 43 unsigned long mmap_min_addr; 44 #if defined(CONFIG_USE_GUEST_BASE) 45 unsigned long guest_base; 46 int have_guest_base; 47 unsigned long reserved_va; 48 #endif 49 50 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 51 const char *qemu_uname_release = CONFIG_UNAME_RELEASE; 52 53 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 54 we allocate a bigger stack. Need a better solution, for example 55 by remapping the process stack directly at the right place */ 56 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 57 58 void gemu_log(const char *fmt, ...) 59 { 60 va_list ap; 61 62 va_start(ap, fmt); 63 vfprintf(stderr, fmt, ap); 64 va_end(ap); 65 } 66 67 #if defined(TARGET_I386) 68 int cpu_get_pic_interrupt(CPUState *env) 69 { 70 return -1; 71 } 72 #endif 73 74 /* timers for rdtsc */ 75 76 #if 0 77 78 static uint64_t emu_time; 79 80 int64_t cpu_get_real_ticks(void) 81 { 82 return emu_time++; 83 } 84 85 #endif 86 87 #if defined(CONFIG_USE_NPTL) 88 /***********************************************************/ 89 /* Helper routines for implementing atomic operations. */ 90 91 /* To implement exclusive operations we force all cpus to syncronise. 92 We don't require a full sync, only that no cpus are executing guest code. 93 The alternative is to map target atomic ops onto host equivalents, 94 which requires quite a lot of per host/target work. */ 95 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; 96 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 97 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 98 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 99 static int pending_cpus; 100 101 /* Make sure everything is in a consistent state for calling fork(). */ 102 void fork_start(void) 103 { 104 pthread_mutex_lock(&tb_lock); 105 pthread_mutex_lock(&exclusive_lock); 106 mmap_fork_start(); 107 } 108 109 void fork_end(int child) 110 { 111 mmap_fork_end(child); 112 if (child) { 113 /* Child processes created by fork() only have a single thread. 114 Discard information about the parent threads. */ 115 first_cpu = thread_env; 116 thread_env->next_cpu = NULL; 117 pending_cpus = 0; 118 pthread_mutex_init(&exclusive_lock, NULL); 119 pthread_mutex_init(&cpu_list_mutex, NULL); 120 pthread_cond_init(&exclusive_cond, NULL); 121 pthread_cond_init(&exclusive_resume, NULL); 122 pthread_mutex_init(&tb_lock, NULL); 123 gdbserver_fork(thread_env); 124 } else { 125 pthread_mutex_unlock(&exclusive_lock); 126 pthread_mutex_unlock(&tb_lock); 127 } 128 } 129 130 /* Wait for pending exclusive operations to complete. The exclusive lock 131 must be held. */ 132 static inline void exclusive_idle(void) 133 { 134 while (pending_cpus) { 135 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 136 } 137 } 138 139 /* Start an exclusive operation. 140 Must only be called from outside cpu_arm_exec. */ 141 static inline void start_exclusive(void) 142 { 143 CPUState *other; 144 pthread_mutex_lock(&exclusive_lock); 145 exclusive_idle(); 146 147 pending_cpus = 1; 148 /* Make all other cpus stop executing. */ 149 for (other = first_cpu; other; other = other->next_cpu) { 150 if (other->running) { 151 pending_cpus++; 152 cpu_exit(other); 153 } 154 } 155 if (pending_cpus > 1) { 156 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 157 } 158 } 159 160 /* Finish an exclusive operation. */ 161 static inline void end_exclusive(void) 162 { 163 pending_cpus = 0; 164 pthread_cond_broadcast(&exclusive_resume); 165 pthread_mutex_unlock(&exclusive_lock); 166 } 167 168 /* Wait for exclusive ops to finish, and begin cpu execution. */ 169 static inline void cpu_exec_start(CPUState *env) 170 { 171 pthread_mutex_lock(&exclusive_lock); 172 exclusive_idle(); 173 env->running = 1; 174 pthread_mutex_unlock(&exclusive_lock); 175 } 176 177 /* Mark cpu as not executing, and release pending exclusive ops. */ 178 static inline void cpu_exec_end(CPUState *env) 179 { 180 pthread_mutex_lock(&exclusive_lock); 181 env->running = 0; 182 if (pending_cpus > 1) { 183 pending_cpus--; 184 if (pending_cpus == 1) { 185 pthread_cond_signal(&exclusive_cond); 186 } 187 } 188 exclusive_idle(); 189 pthread_mutex_unlock(&exclusive_lock); 190 } 191 192 void cpu_list_lock(void) 193 { 194 pthread_mutex_lock(&cpu_list_mutex); 195 } 196 197 void cpu_list_unlock(void) 198 { 199 pthread_mutex_unlock(&cpu_list_mutex); 200 } 201 #else /* if !CONFIG_USE_NPTL */ 202 /* These are no-ops because we are not threadsafe. */ 203 static inline void cpu_exec_start(CPUState *env) 204 { 205 } 206 207 static inline void cpu_exec_end(CPUState *env) 208 { 209 } 210 211 static inline void start_exclusive(void) 212 { 213 } 214 215 static inline void end_exclusive(void) 216 { 217 } 218 219 void fork_start(void) 220 { 221 } 222 223 void fork_end(int child) 224 { 225 if (child) { 226 gdbserver_fork(thread_env); 227 } 228 } 229 230 void cpu_list_lock(void) 231 { 232 } 233 234 void cpu_list_unlock(void) 235 { 236 } 237 #endif 238 239 240 #ifdef TARGET_I386 241 /***********************************************************/ 242 /* CPUX86 core interface */ 243 244 void cpu_smm_update(CPUState *env) 245 { 246 } 247 248 uint64_t cpu_get_tsc(CPUX86State *env) 249 { 250 return cpu_get_real_ticks(); 251 } 252 253 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 254 int flags) 255 { 256 unsigned int e1, e2; 257 uint32_t *p; 258 e1 = (addr << 16) | (limit & 0xffff); 259 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 260 e2 |= flags; 261 p = ptr; 262 p[0] = tswap32(e1); 263 p[1] = tswap32(e2); 264 } 265 266 static uint64_t *idt_table; 267 #ifdef TARGET_X86_64 268 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 269 uint64_t addr, unsigned int sel) 270 { 271 uint32_t *p, e1, e2; 272 e1 = (addr & 0xffff) | (sel << 16); 273 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 274 p = ptr; 275 p[0] = tswap32(e1); 276 p[1] = tswap32(e2); 277 p[2] = tswap32(addr >> 32); 278 p[3] = 0; 279 } 280 /* only dpl matters as we do only user space emulation */ 281 static void set_idt(int n, unsigned int dpl) 282 { 283 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 284 } 285 #else 286 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 287 uint32_t addr, unsigned int sel) 288 { 289 uint32_t *p, e1, e2; 290 e1 = (addr & 0xffff) | (sel << 16); 291 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 292 p = ptr; 293 p[0] = tswap32(e1); 294 p[1] = tswap32(e2); 295 } 296 297 /* only dpl matters as we do only user space emulation */ 298 static void set_idt(int n, unsigned int dpl) 299 { 300 set_gate(idt_table + n, 0, dpl, 0, 0); 301 } 302 #endif 303 304 void cpu_loop(CPUX86State *env) 305 { 306 int trapnr; 307 abi_ulong pc; 308 target_siginfo_t info; 309 310 for(;;) { 311 trapnr = cpu_x86_exec(env); 312 switch(trapnr) { 313 case 0x80: 314 /* linux syscall from int $0x80 */ 315 env->regs[R_EAX] = do_syscall(env, 316 env->regs[R_EAX], 317 env->regs[R_EBX], 318 env->regs[R_ECX], 319 env->regs[R_EDX], 320 env->regs[R_ESI], 321 env->regs[R_EDI], 322 env->regs[R_EBP]); 323 break; 324 #ifndef TARGET_ABI32 325 case EXCP_SYSCALL: 326 /* linux syscall from syscall intruction */ 327 env->regs[R_EAX] = do_syscall(env, 328 env->regs[R_EAX], 329 env->regs[R_EDI], 330 env->regs[R_ESI], 331 env->regs[R_EDX], 332 env->regs[10], 333 env->regs[8], 334 env->regs[9]); 335 env->eip = env->exception_next_eip; 336 break; 337 #endif 338 case EXCP0B_NOSEG: 339 case EXCP0C_STACK: 340 info.si_signo = SIGBUS; 341 info.si_errno = 0; 342 info.si_code = TARGET_SI_KERNEL; 343 info._sifields._sigfault._addr = 0; 344 queue_signal(env, info.si_signo, &info); 345 break; 346 case EXCP0D_GPF: 347 /* XXX: potential problem if ABI32 */ 348 #ifndef TARGET_X86_64 349 if (env->eflags & VM_MASK) { 350 handle_vm86_fault(env); 351 } else 352 #endif 353 { 354 info.si_signo = SIGSEGV; 355 info.si_errno = 0; 356 info.si_code = TARGET_SI_KERNEL; 357 info._sifields._sigfault._addr = 0; 358 queue_signal(env, info.si_signo, &info); 359 } 360 break; 361 case EXCP0E_PAGE: 362 info.si_signo = SIGSEGV; 363 info.si_errno = 0; 364 if (!(env->error_code & 1)) 365 info.si_code = TARGET_SEGV_MAPERR; 366 else 367 info.si_code = TARGET_SEGV_ACCERR; 368 info._sifields._sigfault._addr = env->cr[2]; 369 queue_signal(env, info.si_signo, &info); 370 break; 371 case EXCP00_DIVZ: 372 #ifndef TARGET_X86_64 373 if (env->eflags & VM_MASK) { 374 handle_vm86_trap(env, trapnr); 375 } else 376 #endif 377 { 378 /* division by zero */ 379 info.si_signo = SIGFPE; 380 info.si_errno = 0; 381 info.si_code = TARGET_FPE_INTDIV; 382 info._sifields._sigfault._addr = env->eip; 383 queue_signal(env, info.si_signo, &info); 384 } 385 break; 386 case EXCP01_DB: 387 case EXCP03_INT3: 388 #ifndef TARGET_X86_64 389 if (env->eflags & VM_MASK) { 390 handle_vm86_trap(env, trapnr); 391 } else 392 #endif 393 { 394 info.si_signo = SIGTRAP; 395 info.si_errno = 0; 396 if (trapnr == EXCP01_DB) { 397 info.si_code = TARGET_TRAP_BRKPT; 398 info._sifields._sigfault._addr = env->eip; 399 } else { 400 info.si_code = TARGET_SI_KERNEL; 401 info._sifields._sigfault._addr = 0; 402 } 403 queue_signal(env, info.si_signo, &info); 404 } 405 break; 406 case EXCP04_INTO: 407 case EXCP05_BOUND: 408 #ifndef TARGET_X86_64 409 if (env->eflags & VM_MASK) { 410 handle_vm86_trap(env, trapnr); 411 } else 412 #endif 413 { 414 info.si_signo = SIGSEGV; 415 info.si_errno = 0; 416 info.si_code = TARGET_SI_KERNEL; 417 info._sifields._sigfault._addr = 0; 418 queue_signal(env, info.si_signo, &info); 419 } 420 break; 421 case EXCP06_ILLOP: 422 info.si_signo = SIGILL; 423 info.si_errno = 0; 424 info.si_code = TARGET_ILL_ILLOPN; 425 info._sifields._sigfault._addr = env->eip; 426 queue_signal(env, info.si_signo, &info); 427 break; 428 case EXCP_INTERRUPT: 429 /* just indicate that signals should be handled asap */ 430 break; 431 case EXCP_DEBUG: 432 { 433 int sig; 434 435 sig = gdb_handlesig (env, TARGET_SIGTRAP); 436 if (sig) 437 { 438 info.si_signo = sig; 439 info.si_errno = 0; 440 info.si_code = TARGET_TRAP_BRKPT; 441 queue_signal(env, info.si_signo, &info); 442 } 443 } 444 break; 445 default: 446 pc = env->segs[R_CS].base + env->eip; 447 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 448 (long)pc, trapnr); 449 abort(); 450 } 451 process_pending_signals(env); 452 } 453 } 454 #endif 455 456 #ifdef TARGET_ARM 457 458 static void arm_cache_flush(abi_ulong start, abi_ulong last) 459 { 460 abi_ulong addr, last1; 461 462 if (last < start) 463 return; 464 addr = start; 465 for(;;) { 466 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1; 467 if (last1 > last) 468 last1 = last; 469 tb_invalidate_page_range(addr, last1 + 1); 470 if (last1 == last) 471 break; 472 addr = last1 + 1; 473 } 474 } 475 476 /* Handle a jump to the kernel code page. */ 477 static int 478 do_kernel_trap(CPUARMState *env) 479 { 480 uint32_t addr; 481 uint32_t cpsr; 482 uint32_t val; 483 484 switch (env->regs[15]) { 485 case 0xffff0fa0: /* __kernel_memory_barrier */ 486 /* ??? No-op. Will need to do better for SMP. */ 487 break; 488 case 0xffff0fc0: /* __kernel_cmpxchg */ 489 /* XXX: This only works between threads, not between processes. 490 It's probably possible to implement this with native host 491 operations. However things like ldrex/strex are much harder so 492 there's not much point trying. */ 493 start_exclusive(); 494 cpsr = cpsr_read(env); 495 addr = env->regs[2]; 496 /* FIXME: This should SEGV if the access fails. */ 497 if (get_user_u32(val, addr)) 498 val = ~env->regs[0]; 499 if (val == env->regs[0]) { 500 val = env->regs[1]; 501 /* FIXME: Check for segfaults. */ 502 put_user_u32(val, addr); 503 env->regs[0] = 0; 504 cpsr |= CPSR_C; 505 } else { 506 env->regs[0] = -1; 507 cpsr &= ~CPSR_C; 508 } 509 cpsr_write(env, cpsr, CPSR_C); 510 end_exclusive(); 511 break; 512 case 0xffff0fe0: /* __kernel_get_tls */ 513 env->regs[0] = env->cp15.c13_tls2; 514 break; 515 default: 516 return 1; 517 } 518 /* Jump back to the caller. */ 519 addr = env->regs[14]; 520 if (addr & 1) { 521 env->thumb = 1; 522 addr &= ~1; 523 } 524 env->regs[15] = addr; 525 526 return 0; 527 } 528 529 static int do_strex(CPUARMState *env) 530 { 531 uint32_t val; 532 int size; 533 int rc = 1; 534 int segv = 0; 535 uint32_t addr; 536 start_exclusive(); 537 addr = env->exclusive_addr; 538 if (addr != env->exclusive_test) { 539 goto fail; 540 } 541 size = env->exclusive_info & 0xf; 542 switch (size) { 543 case 0: 544 segv = get_user_u8(val, addr); 545 break; 546 case 1: 547 segv = get_user_u16(val, addr); 548 break; 549 case 2: 550 case 3: 551 segv = get_user_u32(val, addr); 552 break; 553 default: 554 abort(); 555 } 556 if (segv) { 557 env->cp15.c6_data = addr; 558 goto done; 559 } 560 if (val != env->exclusive_val) { 561 goto fail; 562 } 563 if (size == 3) { 564 segv = get_user_u32(val, addr + 4); 565 if (segv) { 566 env->cp15.c6_data = addr + 4; 567 goto done; 568 } 569 if (val != env->exclusive_high) { 570 goto fail; 571 } 572 } 573 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 574 switch (size) { 575 case 0: 576 segv = put_user_u8(val, addr); 577 break; 578 case 1: 579 segv = put_user_u16(val, addr); 580 break; 581 case 2: 582 case 3: 583 segv = put_user_u32(val, addr); 584 break; 585 } 586 if (segv) { 587 env->cp15.c6_data = addr; 588 goto done; 589 } 590 if (size == 3) { 591 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 592 segv = put_user_u32(val, addr + 4); 593 if (segv) { 594 env->cp15.c6_data = addr + 4; 595 goto done; 596 } 597 } 598 rc = 0; 599 fail: 600 env->regs[15] += 4; 601 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 602 done: 603 end_exclusive(); 604 return segv; 605 } 606 607 void cpu_loop(CPUARMState *env) 608 { 609 int trapnr; 610 unsigned int n, insn; 611 target_siginfo_t info; 612 uint32_t addr; 613 614 for(;;) { 615 cpu_exec_start(env); 616 trapnr = cpu_arm_exec(env); 617 cpu_exec_end(env); 618 switch(trapnr) { 619 case EXCP_UDEF: 620 { 621 TaskState *ts = env->opaque; 622 uint32_t opcode; 623 int rc; 624 625 /* we handle the FPU emulation here, as Linux */ 626 /* we get the opcode */ 627 /* FIXME - what to do if get_user() fails? */ 628 get_user_u32(opcode, env->regs[15]); 629 630 rc = EmulateAll(opcode, &ts->fpa, env); 631 if (rc == 0) { /* illegal instruction */ 632 info.si_signo = SIGILL; 633 info.si_errno = 0; 634 info.si_code = TARGET_ILL_ILLOPN; 635 info._sifields._sigfault._addr = env->regs[15]; 636 queue_signal(env, info.si_signo, &info); 637 } else if (rc < 0) { /* FP exception */ 638 int arm_fpe=0; 639 640 /* translate softfloat flags to FPSR flags */ 641 if (-rc & float_flag_invalid) 642 arm_fpe |= BIT_IOC; 643 if (-rc & float_flag_divbyzero) 644 arm_fpe |= BIT_DZC; 645 if (-rc & float_flag_overflow) 646 arm_fpe |= BIT_OFC; 647 if (-rc & float_flag_underflow) 648 arm_fpe |= BIT_UFC; 649 if (-rc & float_flag_inexact) 650 arm_fpe |= BIT_IXC; 651 652 FPSR fpsr = ts->fpa.fpsr; 653 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 654 655 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 656 info.si_signo = SIGFPE; 657 info.si_errno = 0; 658 659 /* ordered by priority, least first */ 660 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 661 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 662 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 663 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 664 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 665 666 info._sifields._sigfault._addr = env->regs[15]; 667 queue_signal(env, info.si_signo, &info); 668 } else { 669 env->regs[15] += 4; 670 } 671 672 /* accumulate unenabled exceptions */ 673 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 674 fpsr |= BIT_IXC; 675 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 676 fpsr |= BIT_UFC; 677 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 678 fpsr |= BIT_OFC; 679 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 680 fpsr |= BIT_DZC; 681 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 682 fpsr |= BIT_IOC; 683 ts->fpa.fpsr=fpsr; 684 } else { /* everything OK */ 685 /* increment PC */ 686 env->regs[15] += 4; 687 } 688 } 689 break; 690 case EXCP_SWI: 691 case EXCP_BKPT: 692 { 693 env->eabi = 1; 694 /* system call */ 695 if (trapnr == EXCP_BKPT) { 696 if (env->thumb) { 697 /* FIXME - what to do if get_user() fails? */ 698 get_user_u16(insn, env->regs[15]); 699 n = insn & 0xff; 700 env->regs[15] += 2; 701 } else { 702 /* FIXME - what to do if get_user() fails? */ 703 get_user_u32(insn, env->regs[15]); 704 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 705 env->regs[15] += 4; 706 } 707 } else { 708 if (env->thumb) { 709 /* FIXME - what to do if get_user() fails? */ 710 get_user_u16(insn, env->regs[15] - 2); 711 n = insn & 0xff; 712 } else { 713 /* FIXME - what to do if get_user() fails? */ 714 get_user_u32(insn, env->regs[15] - 4); 715 n = insn & 0xffffff; 716 } 717 } 718 719 if (n == ARM_NR_cacheflush) { 720 arm_cache_flush(env->regs[0], env->regs[1]); 721 } else if (n == ARM_NR_semihosting 722 || n == ARM_NR_thumb_semihosting) { 723 env->regs[0] = do_arm_semihosting (env); 724 } else if (n == 0 || n >= ARM_SYSCALL_BASE 725 || (env->thumb && n == ARM_THUMB_SYSCALL)) { 726 /* linux syscall */ 727 if (env->thumb || n == 0) { 728 n = env->regs[7]; 729 } else { 730 n -= ARM_SYSCALL_BASE; 731 env->eabi = 0; 732 } 733 if ( n > ARM_NR_BASE) { 734 switch (n) { 735 case ARM_NR_cacheflush: 736 arm_cache_flush(env->regs[0], env->regs[1]); 737 break; 738 case ARM_NR_set_tls: 739 cpu_set_tls(env, env->regs[0]); 740 env->regs[0] = 0; 741 break; 742 default: 743 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 744 n); 745 env->regs[0] = -TARGET_ENOSYS; 746 break; 747 } 748 } else { 749 env->regs[0] = do_syscall(env, 750 n, 751 env->regs[0], 752 env->regs[1], 753 env->regs[2], 754 env->regs[3], 755 env->regs[4], 756 env->regs[5]); 757 } 758 } else { 759 goto error; 760 } 761 } 762 break; 763 case EXCP_INTERRUPT: 764 /* just indicate that signals should be handled asap */ 765 break; 766 case EXCP_PREFETCH_ABORT: 767 addr = env->cp15.c6_insn; 768 goto do_segv; 769 case EXCP_DATA_ABORT: 770 addr = env->cp15.c6_data; 771 goto do_segv; 772 do_segv: 773 { 774 info.si_signo = SIGSEGV; 775 info.si_errno = 0; 776 /* XXX: check env->error_code */ 777 info.si_code = TARGET_SEGV_MAPERR; 778 info._sifields._sigfault._addr = addr; 779 queue_signal(env, info.si_signo, &info); 780 } 781 break; 782 case EXCP_DEBUG: 783 { 784 int sig; 785 786 sig = gdb_handlesig (env, TARGET_SIGTRAP); 787 if (sig) 788 { 789 info.si_signo = sig; 790 info.si_errno = 0; 791 info.si_code = TARGET_TRAP_BRKPT; 792 queue_signal(env, info.si_signo, &info); 793 } 794 } 795 break; 796 case EXCP_KERNEL_TRAP: 797 if (do_kernel_trap(env)) 798 goto error; 799 break; 800 case EXCP_STREX: 801 if (do_strex(env)) { 802 addr = env->cp15.c6_data; 803 goto do_segv; 804 } 805 break; 806 default: 807 error: 808 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 809 trapnr); 810 cpu_dump_state(env, stderr, fprintf, 0); 811 abort(); 812 } 813 process_pending_signals(env); 814 } 815 } 816 817 #endif 818 819 #ifdef TARGET_UNICORE32 820 821 void cpu_loop(CPUState *env) 822 { 823 int trapnr; 824 unsigned int n, insn; 825 target_siginfo_t info; 826 827 for (;;) { 828 cpu_exec_start(env); 829 trapnr = uc32_cpu_exec(env); 830 cpu_exec_end(env); 831 switch (trapnr) { 832 case UC32_EXCP_PRIV: 833 { 834 /* system call */ 835 get_user_u32(insn, env->regs[31] - 4); 836 n = insn & 0xffffff; 837 838 if (n >= UC32_SYSCALL_BASE) { 839 /* linux syscall */ 840 n -= UC32_SYSCALL_BASE; 841 if (n == UC32_SYSCALL_NR_set_tls) { 842 cpu_set_tls(env, env->regs[0]); 843 env->regs[0] = 0; 844 } else { 845 env->regs[0] = do_syscall(env, 846 n, 847 env->regs[0], 848 env->regs[1], 849 env->regs[2], 850 env->regs[3], 851 env->regs[4], 852 env->regs[5]); 853 } 854 } else { 855 goto error; 856 } 857 } 858 break; 859 case UC32_EXCP_TRAP: 860 info.si_signo = SIGSEGV; 861 info.si_errno = 0; 862 /* XXX: check env->error_code */ 863 info.si_code = TARGET_SEGV_MAPERR; 864 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 865 queue_signal(env, info.si_signo, &info); 866 break; 867 case EXCP_INTERRUPT: 868 /* just indicate that signals should be handled asap */ 869 break; 870 case EXCP_DEBUG: 871 { 872 int sig; 873 874 sig = gdb_handlesig(env, TARGET_SIGTRAP); 875 if (sig) { 876 info.si_signo = sig; 877 info.si_errno = 0; 878 info.si_code = TARGET_TRAP_BRKPT; 879 queue_signal(env, info.si_signo, &info); 880 } 881 } 882 break; 883 default: 884 goto error; 885 } 886 process_pending_signals(env); 887 } 888 889 error: 890 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 891 cpu_dump_state(env, stderr, fprintf, 0); 892 abort(); 893 } 894 #endif 895 896 #ifdef TARGET_SPARC 897 #define SPARC64_STACK_BIAS 2047 898 899 //#define DEBUG_WIN 900 901 /* WARNING: dealing with register windows _is_ complicated. More info 902 can be found at http://www.sics.se/~psm/sparcstack.html */ 903 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 904 { 905 index = (index + cwp * 16) % (16 * env->nwindows); 906 /* wrap handling : if cwp is on the last window, then we use the 907 registers 'after' the end */ 908 if (index < 8 && env->cwp == env->nwindows - 1) 909 index += 16 * env->nwindows; 910 return index; 911 } 912 913 /* save the register window 'cwp1' */ 914 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 915 { 916 unsigned int i; 917 abi_ulong sp_ptr; 918 919 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 920 #ifdef TARGET_SPARC64 921 if (sp_ptr & 3) 922 sp_ptr += SPARC64_STACK_BIAS; 923 #endif 924 #if defined(DEBUG_WIN) 925 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 926 sp_ptr, cwp1); 927 #endif 928 for(i = 0; i < 16; i++) { 929 /* FIXME - what to do if put_user() fails? */ 930 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 931 sp_ptr += sizeof(abi_ulong); 932 } 933 } 934 935 static void save_window(CPUSPARCState *env) 936 { 937 #ifndef TARGET_SPARC64 938 unsigned int new_wim; 939 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 940 ((1LL << env->nwindows) - 1); 941 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 942 env->wim = new_wim; 943 #else 944 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 945 env->cansave++; 946 env->canrestore--; 947 #endif 948 } 949 950 static void restore_window(CPUSPARCState *env) 951 { 952 #ifndef TARGET_SPARC64 953 unsigned int new_wim; 954 #endif 955 unsigned int i, cwp1; 956 abi_ulong sp_ptr; 957 958 #ifndef TARGET_SPARC64 959 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 960 ((1LL << env->nwindows) - 1); 961 #endif 962 963 /* restore the invalid window */ 964 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 965 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 966 #ifdef TARGET_SPARC64 967 if (sp_ptr & 3) 968 sp_ptr += SPARC64_STACK_BIAS; 969 #endif 970 #if defined(DEBUG_WIN) 971 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 972 sp_ptr, cwp1); 973 #endif 974 for(i = 0; i < 16; i++) { 975 /* FIXME - what to do if get_user() fails? */ 976 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 977 sp_ptr += sizeof(abi_ulong); 978 } 979 #ifdef TARGET_SPARC64 980 env->canrestore++; 981 if (env->cleanwin < env->nwindows - 1) 982 env->cleanwin++; 983 env->cansave--; 984 #else 985 env->wim = new_wim; 986 #endif 987 } 988 989 static void flush_windows(CPUSPARCState *env) 990 { 991 int offset, cwp1; 992 993 offset = 1; 994 for(;;) { 995 /* if restore would invoke restore_window(), then we can stop */ 996 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 997 #ifndef TARGET_SPARC64 998 if (env->wim & (1 << cwp1)) 999 break; 1000 #else 1001 if (env->canrestore == 0) 1002 break; 1003 env->cansave++; 1004 env->canrestore--; 1005 #endif 1006 save_window_offset(env, cwp1); 1007 offset++; 1008 } 1009 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1010 #ifndef TARGET_SPARC64 1011 /* set wim so that restore will reload the registers */ 1012 env->wim = 1 << cwp1; 1013 #endif 1014 #if defined(DEBUG_WIN) 1015 printf("flush_windows: nb=%d\n", offset - 1); 1016 #endif 1017 } 1018 1019 void cpu_loop (CPUSPARCState *env) 1020 { 1021 int trapnr; 1022 abi_long ret; 1023 target_siginfo_t info; 1024 1025 while (1) { 1026 trapnr = cpu_sparc_exec (env); 1027 1028 switch (trapnr) { 1029 #ifndef TARGET_SPARC64 1030 case 0x88: 1031 case 0x90: 1032 #else 1033 case 0x110: 1034 case 0x16d: 1035 #endif 1036 ret = do_syscall (env, env->gregs[1], 1037 env->regwptr[0], env->regwptr[1], 1038 env->regwptr[2], env->regwptr[3], 1039 env->regwptr[4], env->regwptr[5]); 1040 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1041 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1042 env->xcc |= PSR_CARRY; 1043 #else 1044 env->psr |= PSR_CARRY; 1045 #endif 1046 ret = -ret; 1047 } else { 1048 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1049 env->xcc &= ~PSR_CARRY; 1050 #else 1051 env->psr &= ~PSR_CARRY; 1052 #endif 1053 } 1054 env->regwptr[0] = ret; 1055 /* next instruction */ 1056 env->pc = env->npc; 1057 env->npc = env->npc + 4; 1058 break; 1059 case 0x83: /* flush windows */ 1060 #ifdef TARGET_ABI32 1061 case 0x103: 1062 #endif 1063 flush_windows(env); 1064 /* next instruction */ 1065 env->pc = env->npc; 1066 env->npc = env->npc + 4; 1067 break; 1068 #ifndef TARGET_SPARC64 1069 case TT_WIN_OVF: /* window overflow */ 1070 save_window(env); 1071 break; 1072 case TT_WIN_UNF: /* window underflow */ 1073 restore_window(env); 1074 break; 1075 case TT_TFAULT: 1076 case TT_DFAULT: 1077 { 1078 info.si_signo = SIGSEGV; 1079 info.si_errno = 0; 1080 /* XXX: check env->error_code */ 1081 info.si_code = TARGET_SEGV_MAPERR; 1082 info._sifields._sigfault._addr = env->mmuregs[4]; 1083 queue_signal(env, info.si_signo, &info); 1084 } 1085 break; 1086 #else 1087 case TT_SPILL: /* window overflow */ 1088 save_window(env); 1089 break; 1090 case TT_FILL: /* window underflow */ 1091 restore_window(env); 1092 break; 1093 case TT_TFAULT: 1094 case TT_DFAULT: 1095 { 1096 info.si_signo = SIGSEGV; 1097 info.si_errno = 0; 1098 /* XXX: check env->error_code */ 1099 info.si_code = TARGET_SEGV_MAPERR; 1100 if (trapnr == TT_DFAULT) 1101 info._sifields._sigfault._addr = env->dmmuregs[4]; 1102 else 1103 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1104 queue_signal(env, info.si_signo, &info); 1105 } 1106 break; 1107 #ifndef TARGET_ABI32 1108 case 0x16e: 1109 flush_windows(env); 1110 sparc64_get_context(env); 1111 break; 1112 case 0x16f: 1113 flush_windows(env); 1114 sparc64_set_context(env); 1115 break; 1116 #endif 1117 #endif 1118 case EXCP_INTERRUPT: 1119 /* just indicate that signals should be handled asap */ 1120 break; 1121 case EXCP_DEBUG: 1122 { 1123 int sig; 1124 1125 sig = gdb_handlesig (env, TARGET_SIGTRAP); 1126 if (sig) 1127 { 1128 info.si_signo = sig; 1129 info.si_errno = 0; 1130 info.si_code = TARGET_TRAP_BRKPT; 1131 queue_signal(env, info.si_signo, &info); 1132 } 1133 } 1134 break; 1135 default: 1136 printf ("Unhandled trap: 0x%x\n", trapnr); 1137 cpu_dump_state(env, stderr, fprintf, 0); 1138 exit (1); 1139 } 1140 process_pending_signals (env); 1141 } 1142 } 1143 1144 #endif 1145 1146 #ifdef TARGET_PPC 1147 static inline uint64_t cpu_ppc_get_tb (CPUState *env) 1148 { 1149 /* TO FIX */ 1150 return 0; 1151 } 1152 1153 uint64_t cpu_ppc_load_tbl (CPUState *env) 1154 { 1155 return cpu_ppc_get_tb(env); 1156 } 1157 1158 uint32_t cpu_ppc_load_tbu (CPUState *env) 1159 { 1160 return cpu_ppc_get_tb(env) >> 32; 1161 } 1162 1163 uint64_t cpu_ppc_load_atbl (CPUState *env) 1164 { 1165 return cpu_ppc_get_tb(env); 1166 } 1167 1168 uint32_t cpu_ppc_load_atbu (CPUState *env) 1169 { 1170 return cpu_ppc_get_tb(env) >> 32; 1171 } 1172 1173 uint32_t cpu_ppc601_load_rtcu (CPUState *env) 1174 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1175 1176 uint32_t cpu_ppc601_load_rtcl (CPUState *env) 1177 { 1178 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1179 } 1180 1181 /* XXX: to be fixed */ 1182 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1183 { 1184 return -1; 1185 } 1186 1187 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1188 { 1189 return -1; 1190 } 1191 1192 #define EXCP_DUMP(env, fmt, ...) \ 1193 do { \ 1194 fprintf(stderr, fmt , ## __VA_ARGS__); \ 1195 cpu_dump_state(env, stderr, fprintf, 0); \ 1196 qemu_log(fmt, ## __VA_ARGS__); \ 1197 if (logfile) \ 1198 log_cpu_state(env, 0); \ 1199 } while (0) 1200 1201 static int do_store_exclusive(CPUPPCState *env) 1202 { 1203 target_ulong addr; 1204 target_ulong page_addr; 1205 target_ulong val; 1206 int flags; 1207 int segv = 0; 1208 1209 addr = env->reserve_ea; 1210 page_addr = addr & TARGET_PAGE_MASK; 1211 start_exclusive(); 1212 mmap_lock(); 1213 flags = page_get_flags(page_addr); 1214 if ((flags & PAGE_READ) == 0) { 1215 segv = 1; 1216 } else { 1217 int reg = env->reserve_info & 0x1f; 1218 int size = (env->reserve_info >> 5) & 0xf; 1219 int stored = 0; 1220 1221 if (addr == env->reserve_addr) { 1222 switch (size) { 1223 case 1: segv = get_user_u8(val, addr); break; 1224 case 2: segv = get_user_u16(val, addr); break; 1225 case 4: segv = get_user_u32(val, addr); break; 1226 #if defined(TARGET_PPC64) 1227 case 8: segv = get_user_u64(val, addr); break; 1228 #endif 1229 default: abort(); 1230 } 1231 if (!segv && val == env->reserve_val) { 1232 val = env->gpr[reg]; 1233 switch (size) { 1234 case 1: segv = put_user_u8(val, addr); break; 1235 case 2: segv = put_user_u16(val, addr); break; 1236 case 4: segv = put_user_u32(val, addr); break; 1237 #if defined(TARGET_PPC64) 1238 case 8: segv = put_user_u64(val, addr); break; 1239 #endif 1240 default: abort(); 1241 } 1242 if (!segv) { 1243 stored = 1; 1244 } 1245 } 1246 } 1247 env->crf[0] = (stored << 1) | xer_so; 1248 env->reserve_addr = (target_ulong)-1; 1249 } 1250 if (!segv) { 1251 env->nip += 4; 1252 } 1253 mmap_unlock(); 1254 end_exclusive(); 1255 return segv; 1256 } 1257 1258 void cpu_loop(CPUPPCState *env) 1259 { 1260 target_siginfo_t info; 1261 int trapnr; 1262 uint32_t ret; 1263 1264 for(;;) { 1265 cpu_exec_start(env); 1266 trapnr = cpu_ppc_exec(env); 1267 cpu_exec_end(env); 1268 switch(trapnr) { 1269 case POWERPC_EXCP_NONE: 1270 /* Just go on */ 1271 break; 1272 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1273 cpu_abort(env, "Critical interrupt while in user mode. " 1274 "Aborting\n"); 1275 break; 1276 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1277 cpu_abort(env, "Machine check exception while in user mode. " 1278 "Aborting\n"); 1279 break; 1280 case POWERPC_EXCP_DSI: /* Data storage exception */ 1281 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", 1282 env->spr[SPR_DAR]); 1283 /* XXX: check this. Seems bugged */ 1284 switch (env->error_code & 0xFF000000) { 1285 case 0x40000000: 1286 info.si_signo = TARGET_SIGSEGV; 1287 info.si_errno = 0; 1288 info.si_code = TARGET_SEGV_MAPERR; 1289 break; 1290 case 0x04000000: 1291 info.si_signo = TARGET_SIGILL; 1292 info.si_errno = 0; 1293 info.si_code = TARGET_ILL_ILLADR; 1294 break; 1295 case 0x08000000: 1296 info.si_signo = TARGET_SIGSEGV; 1297 info.si_errno = 0; 1298 info.si_code = TARGET_SEGV_ACCERR; 1299 break; 1300 default: 1301 /* Let's send a regular segfault... */ 1302 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1303 env->error_code); 1304 info.si_signo = TARGET_SIGSEGV; 1305 info.si_errno = 0; 1306 info.si_code = TARGET_SEGV_MAPERR; 1307 break; 1308 } 1309 info._sifields._sigfault._addr = env->nip; 1310 queue_signal(env, info.si_signo, &info); 1311 break; 1312 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1313 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx 1314 "\n", env->spr[SPR_SRR0]); 1315 /* XXX: check this */ 1316 switch (env->error_code & 0xFF000000) { 1317 case 0x40000000: 1318 info.si_signo = TARGET_SIGSEGV; 1319 info.si_errno = 0; 1320 info.si_code = TARGET_SEGV_MAPERR; 1321 break; 1322 case 0x10000000: 1323 case 0x08000000: 1324 info.si_signo = TARGET_SIGSEGV; 1325 info.si_errno = 0; 1326 info.si_code = TARGET_SEGV_ACCERR; 1327 break; 1328 default: 1329 /* Let's send a regular segfault... */ 1330 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1331 env->error_code); 1332 info.si_signo = TARGET_SIGSEGV; 1333 info.si_errno = 0; 1334 info.si_code = TARGET_SEGV_MAPERR; 1335 break; 1336 } 1337 info._sifields._sigfault._addr = env->nip - 4; 1338 queue_signal(env, info.si_signo, &info); 1339 break; 1340 case POWERPC_EXCP_EXTERNAL: /* External input */ 1341 cpu_abort(env, "External interrupt while in user mode. " 1342 "Aborting\n"); 1343 break; 1344 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1345 EXCP_DUMP(env, "Unaligned memory access\n"); 1346 /* XXX: check this */ 1347 info.si_signo = TARGET_SIGBUS; 1348 info.si_errno = 0; 1349 info.si_code = TARGET_BUS_ADRALN; 1350 info._sifields._sigfault._addr = env->nip - 4; 1351 queue_signal(env, info.si_signo, &info); 1352 break; 1353 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1354 /* XXX: check this */ 1355 switch (env->error_code & ~0xF) { 1356 case POWERPC_EXCP_FP: 1357 EXCP_DUMP(env, "Floating point program exception\n"); 1358 info.si_signo = TARGET_SIGFPE; 1359 info.si_errno = 0; 1360 switch (env->error_code & 0xF) { 1361 case POWERPC_EXCP_FP_OX: 1362 info.si_code = TARGET_FPE_FLTOVF; 1363 break; 1364 case POWERPC_EXCP_FP_UX: 1365 info.si_code = TARGET_FPE_FLTUND; 1366 break; 1367 case POWERPC_EXCP_FP_ZX: 1368 case POWERPC_EXCP_FP_VXZDZ: 1369 info.si_code = TARGET_FPE_FLTDIV; 1370 break; 1371 case POWERPC_EXCP_FP_XX: 1372 info.si_code = TARGET_FPE_FLTRES; 1373 break; 1374 case POWERPC_EXCP_FP_VXSOFT: 1375 info.si_code = TARGET_FPE_FLTINV; 1376 break; 1377 case POWERPC_EXCP_FP_VXSNAN: 1378 case POWERPC_EXCP_FP_VXISI: 1379 case POWERPC_EXCP_FP_VXIDI: 1380 case POWERPC_EXCP_FP_VXIMZ: 1381 case POWERPC_EXCP_FP_VXVC: 1382 case POWERPC_EXCP_FP_VXSQRT: 1383 case POWERPC_EXCP_FP_VXCVI: 1384 info.si_code = TARGET_FPE_FLTSUB; 1385 break; 1386 default: 1387 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1388 env->error_code); 1389 break; 1390 } 1391 break; 1392 case POWERPC_EXCP_INVAL: 1393 EXCP_DUMP(env, "Invalid instruction\n"); 1394 info.si_signo = TARGET_SIGILL; 1395 info.si_errno = 0; 1396 switch (env->error_code & 0xF) { 1397 case POWERPC_EXCP_INVAL_INVAL: 1398 info.si_code = TARGET_ILL_ILLOPC; 1399 break; 1400 case POWERPC_EXCP_INVAL_LSWX: 1401 info.si_code = TARGET_ILL_ILLOPN; 1402 break; 1403 case POWERPC_EXCP_INVAL_SPR: 1404 info.si_code = TARGET_ILL_PRVREG; 1405 break; 1406 case POWERPC_EXCP_INVAL_FP: 1407 info.si_code = TARGET_ILL_COPROC; 1408 break; 1409 default: 1410 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1411 env->error_code & 0xF); 1412 info.si_code = TARGET_ILL_ILLADR; 1413 break; 1414 } 1415 break; 1416 case POWERPC_EXCP_PRIV: 1417 EXCP_DUMP(env, "Privilege violation\n"); 1418 info.si_signo = TARGET_SIGILL; 1419 info.si_errno = 0; 1420 switch (env->error_code & 0xF) { 1421 case POWERPC_EXCP_PRIV_OPC: 1422 info.si_code = TARGET_ILL_PRVOPC; 1423 break; 1424 case POWERPC_EXCP_PRIV_REG: 1425 info.si_code = TARGET_ILL_PRVREG; 1426 break; 1427 default: 1428 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1429 env->error_code & 0xF); 1430 info.si_code = TARGET_ILL_PRVOPC; 1431 break; 1432 } 1433 break; 1434 case POWERPC_EXCP_TRAP: 1435 cpu_abort(env, "Tried to call a TRAP\n"); 1436 break; 1437 default: 1438 /* Should not happen ! */ 1439 cpu_abort(env, "Unknown program exception (%02x)\n", 1440 env->error_code); 1441 break; 1442 } 1443 info._sifields._sigfault._addr = env->nip - 4; 1444 queue_signal(env, info.si_signo, &info); 1445 break; 1446 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1447 EXCP_DUMP(env, "No floating point allowed\n"); 1448 info.si_signo = TARGET_SIGILL; 1449 info.si_errno = 0; 1450 info.si_code = TARGET_ILL_COPROC; 1451 info._sifields._sigfault._addr = env->nip - 4; 1452 queue_signal(env, info.si_signo, &info); 1453 break; 1454 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1455 cpu_abort(env, "Syscall exception while in user mode. " 1456 "Aborting\n"); 1457 break; 1458 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1459 EXCP_DUMP(env, "No APU instruction allowed\n"); 1460 info.si_signo = TARGET_SIGILL; 1461 info.si_errno = 0; 1462 info.si_code = TARGET_ILL_COPROC; 1463 info._sifields._sigfault._addr = env->nip - 4; 1464 queue_signal(env, info.si_signo, &info); 1465 break; 1466 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1467 cpu_abort(env, "Decrementer interrupt while in user mode. " 1468 "Aborting\n"); 1469 break; 1470 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1471 cpu_abort(env, "Fix interval timer interrupt while in user mode. " 1472 "Aborting\n"); 1473 break; 1474 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1475 cpu_abort(env, "Watchdog timer interrupt while in user mode. " 1476 "Aborting\n"); 1477 break; 1478 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1479 cpu_abort(env, "Data TLB exception while in user mode. " 1480 "Aborting\n"); 1481 break; 1482 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1483 cpu_abort(env, "Instruction TLB exception while in user mode. " 1484 "Aborting\n"); 1485 break; 1486 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1487 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1488 info.si_signo = TARGET_SIGILL; 1489 info.si_errno = 0; 1490 info.si_code = TARGET_ILL_COPROC; 1491 info._sifields._sigfault._addr = env->nip - 4; 1492 queue_signal(env, info.si_signo, &info); 1493 break; 1494 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1495 cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); 1496 break; 1497 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1498 cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); 1499 break; 1500 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1501 cpu_abort(env, "Performance monitor exception not handled\n"); 1502 break; 1503 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1504 cpu_abort(env, "Doorbell interrupt while in user mode. " 1505 "Aborting\n"); 1506 break; 1507 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1508 cpu_abort(env, "Doorbell critical interrupt while in user mode. " 1509 "Aborting\n"); 1510 break; 1511 case POWERPC_EXCP_RESET: /* System reset exception */ 1512 cpu_abort(env, "Reset interrupt while in user mode. " 1513 "Aborting\n"); 1514 break; 1515 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1516 cpu_abort(env, "Data segment exception while in user mode. " 1517 "Aborting\n"); 1518 break; 1519 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1520 cpu_abort(env, "Instruction segment exception " 1521 "while in user mode. Aborting\n"); 1522 break; 1523 /* PowerPC 64 with hypervisor mode support */ 1524 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1525 cpu_abort(env, "Hypervisor decrementer interrupt " 1526 "while in user mode. Aborting\n"); 1527 break; 1528 case POWERPC_EXCP_TRACE: /* Trace exception */ 1529 /* Nothing to do: 1530 * we use this exception to emulate step-by-step execution mode. 1531 */ 1532 break; 1533 /* PowerPC 64 with hypervisor mode support */ 1534 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1535 cpu_abort(env, "Hypervisor data storage exception " 1536 "while in user mode. Aborting\n"); 1537 break; 1538 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1539 cpu_abort(env, "Hypervisor instruction storage exception " 1540 "while in user mode. Aborting\n"); 1541 break; 1542 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1543 cpu_abort(env, "Hypervisor data segment exception " 1544 "while in user mode. Aborting\n"); 1545 break; 1546 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1547 cpu_abort(env, "Hypervisor instruction segment exception " 1548 "while in user mode. Aborting\n"); 1549 break; 1550 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1551 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1552 info.si_signo = TARGET_SIGILL; 1553 info.si_errno = 0; 1554 info.si_code = TARGET_ILL_COPROC; 1555 info._sifields._sigfault._addr = env->nip - 4; 1556 queue_signal(env, info.si_signo, &info); 1557 break; 1558 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1559 cpu_abort(env, "Programable interval timer interrupt " 1560 "while in user mode. Aborting\n"); 1561 break; 1562 case POWERPC_EXCP_IO: /* IO error exception */ 1563 cpu_abort(env, "IO error exception while in user mode. " 1564 "Aborting\n"); 1565 break; 1566 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1567 cpu_abort(env, "Run mode exception while in user mode. " 1568 "Aborting\n"); 1569 break; 1570 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1571 cpu_abort(env, "Emulation trap exception not handled\n"); 1572 break; 1573 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1574 cpu_abort(env, "Instruction fetch TLB exception " 1575 "while in user-mode. Aborting"); 1576 break; 1577 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1578 cpu_abort(env, "Data load TLB exception while in user-mode. " 1579 "Aborting"); 1580 break; 1581 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1582 cpu_abort(env, "Data store TLB exception while in user-mode. " 1583 "Aborting"); 1584 break; 1585 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1586 cpu_abort(env, "Floating-point assist exception not handled\n"); 1587 break; 1588 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1589 cpu_abort(env, "Instruction address breakpoint exception " 1590 "not handled\n"); 1591 break; 1592 case POWERPC_EXCP_SMI: /* System management interrupt */ 1593 cpu_abort(env, "System management interrupt while in user mode. " 1594 "Aborting\n"); 1595 break; 1596 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1597 cpu_abort(env, "Thermal interrupt interrupt while in user mode. " 1598 "Aborting\n"); 1599 break; 1600 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1601 cpu_abort(env, "Performance monitor exception not handled\n"); 1602 break; 1603 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1604 cpu_abort(env, "Vector assist exception not handled\n"); 1605 break; 1606 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1607 cpu_abort(env, "Soft patch exception not handled\n"); 1608 break; 1609 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1610 cpu_abort(env, "Maintenance exception while in user mode. " 1611 "Aborting\n"); 1612 break; 1613 case POWERPC_EXCP_STOP: /* stop translation */ 1614 /* We did invalidate the instruction cache. Go on */ 1615 break; 1616 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1617 /* We just stopped because of a branch. Go on */ 1618 break; 1619 case POWERPC_EXCP_SYSCALL_USER: 1620 /* system call in user-mode emulation */ 1621 /* WARNING: 1622 * PPC ABI uses overflow flag in cr0 to signal an error 1623 * in syscalls. 1624 */ 1625 #if 0 1626 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0], 1627 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]); 1628 #endif 1629 env->crf[0] &= ~0x1; 1630 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1631 env->gpr[5], env->gpr[6], env->gpr[7], 1632 env->gpr[8]); 1633 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) { 1634 /* Returning from a successful sigreturn syscall. 1635 Avoid corrupting register state. */ 1636 break; 1637 } 1638 if (ret > (uint32_t)(-515)) { 1639 env->crf[0] |= 0x1; 1640 ret = -ret; 1641 } 1642 env->gpr[3] = ret; 1643 #if 0 1644 printf("syscall returned 0x%08x (%d)\n", ret, ret); 1645 #endif 1646 break; 1647 case POWERPC_EXCP_STCX: 1648 if (do_store_exclusive(env)) { 1649 info.si_signo = TARGET_SIGSEGV; 1650 info.si_errno = 0; 1651 info.si_code = TARGET_SEGV_MAPERR; 1652 info._sifields._sigfault._addr = env->nip; 1653 queue_signal(env, info.si_signo, &info); 1654 } 1655 break; 1656 case EXCP_DEBUG: 1657 { 1658 int sig; 1659 1660 sig = gdb_handlesig(env, TARGET_SIGTRAP); 1661 if (sig) { 1662 info.si_signo = sig; 1663 info.si_errno = 0; 1664 info.si_code = TARGET_TRAP_BRKPT; 1665 queue_signal(env, info.si_signo, &info); 1666 } 1667 } 1668 break; 1669 case EXCP_INTERRUPT: 1670 /* just indicate that signals should be handled asap */ 1671 break; 1672 default: 1673 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); 1674 break; 1675 } 1676 process_pending_signals(env); 1677 } 1678 } 1679 #endif 1680 1681 #ifdef TARGET_MIPS 1682 1683 #define MIPS_SYS(name, args) args, 1684 1685 static const uint8_t mips_syscall_args[] = { 1686 MIPS_SYS(sys_syscall , 0) /* 4000 */ 1687 MIPS_SYS(sys_exit , 1) 1688 MIPS_SYS(sys_fork , 0) 1689 MIPS_SYS(sys_read , 3) 1690 MIPS_SYS(sys_write , 3) 1691 MIPS_SYS(sys_open , 3) /* 4005 */ 1692 MIPS_SYS(sys_close , 1) 1693 MIPS_SYS(sys_waitpid , 3) 1694 MIPS_SYS(sys_creat , 2) 1695 MIPS_SYS(sys_link , 2) 1696 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1697 MIPS_SYS(sys_execve , 0) 1698 MIPS_SYS(sys_chdir , 1) 1699 MIPS_SYS(sys_time , 1) 1700 MIPS_SYS(sys_mknod , 3) 1701 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1702 MIPS_SYS(sys_lchown , 3) 1703 MIPS_SYS(sys_ni_syscall , 0) 1704 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1705 MIPS_SYS(sys_lseek , 3) 1706 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1707 MIPS_SYS(sys_mount , 5) 1708 MIPS_SYS(sys_oldumount , 1) 1709 MIPS_SYS(sys_setuid , 1) 1710 MIPS_SYS(sys_getuid , 0) 1711 MIPS_SYS(sys_stime , 1) /* 4025 */ 1712 MIPS_SYS(sys_ptrace , 4) 1713 MIPS_SYS(sys_alarm , 1) 1714 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1715 MIPS_SYS(sys_pause , 0) 1716 MIPS_SYS(sys_utime , 2) /* 4030 */ 1717 MIPS_SYS(sys_ni_syscall , 0) 1718 MIPS_SYS(sys_ni_syscall , 0) 1719 MIPS_SYS(sys_access , 2) 1720 MIPS_SYS(sys_nice , 1) 1721 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 1722 MIPS_SYS(sys_sync , 0) 1723 MIPS_SYS(sys_kill , 2) 1724 MIPS_SYS(sys_rename , 2) 1725 MIPS_SYS(sys_mkdir , 2) 1726 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 1727 MIPS_SYS(sys_dup , 1) 1728 MIPS_SYS(sys_pipe , 0) 1729 MIPS_SYS(sys_times , 1) 1730 MIPS_SYS(sys_ni_syscall , 0) 1731 MIPS_SYS(sys_brk , 1) /* 4045 */ 1732 MIPS_SYS(sys_setgid , 1) 1733 MIPS_SYS(sys_getgid , 0) 1734 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 1735 MIPS_SYS(sys_geteuid , 0) 1736 MIPS_SYS(sys_getegid , 0) /* 4050 */ 1737 MIPS_SYS(sys_acct , 0) 1738 MIPS_SYS(sys_umount , 2) 1739 MIPS_SYS(sys_ni_syscall , 0) 1740 MIPS_SYS(sys_ioctl , 3) 1741 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 1742 MIPS_SYS(sys_ni_syscall , 2) 1743 MIPS_SYS(sys_setpgid , 2) 1744 MIPS_SYS(sys_ni_syscall , 0) 1745 MIPS_SYS(sys_olduname , 1) 1746 MIPS_SYS(sys_umask , 1) /* 4060 */ 1747 MIPS_SYS(sys_chroot , 1) 1748 MIPS_SYS(sys_ustat , 2) 1749 MIPS_SYS(sys_dup2 , 2) 1750 MIPS_SYS(sys_getppid , 0) 1751 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 1752 MIPS_SYS(sys_setsid , 0) 1753 MIPS_SYS(sys_sigaction , 3) 1754 MIPS_SYS(sys_sgetmask , 0) 1755 MIPS_SYS(sys_ssetmask , 1) 1756 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 1757 MIPS_SYS(sys_setregid , 2) 1758 MIPS_SYS(sys_sigsuspend , 0) 1759 MIPS_SYS(sys_sigpending , 1) 1760 MIPS_SYS(sys_sethostname , 2) 1761 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 1762 MIPS_SYS(sys_getrlimit , 2) 1763 MIPS_SYS(sys_getrusage , 2) 1764 MIPS_SYS(sys_gettimeofday, 2) 1765 MIPS_SYS(sys_settimeofday, 2) 1766 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 1767 MIPS_SYS(sys_setgroups , 2) 1768 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 1769 MIPS_SYS(sys_symlink , 2) 1770 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 1771 MIPS_SYS(sys_readlink , 3) /* 4085 */ 1772 MIPS_SYS(sys_uselib , 1) 1773 MIPS_SYS(sys_swapon , 2) 1774 MIPS_SYS(sys_reboot , 3) 1775 MIPS_SYS(old_readdir , 3) 1776 MIPS_SYS(old_mmap , 6) /* 4090 */ 1777 MIPS_SYS(sys_munmap , 2) 1778 MIPS_SYS(sys_truncate , 2) 1779 MIPS_SYS(sys_ftruncate , 2) 1780 MIPS_SYS(sys_fchmod , 2) 1781 MIPS_SYS(sys_fchown , 3) /* 4095 */ 1782 MIPS_SYS(sys_getpriority , 2) 1783 MIPS_SYS(sys_setpriority , 3) 1784 MIPS_SYS(sys_ni_syscall , 0) 1785 MIPS_SYS(sys_statfs , 2) 1786 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 1787 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 1788 MIPS_SYS(sys_socketcall , 2) 1789 MIPS_SYS(sys_syslog , 3) 1790 MIPS_SYS(sys_setitimer , 3) 1791 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 1792 MIPS_SYS(sys_newstat , 2) 1793 MIPS_SYS(sys_newlstat , 2) 1794 MIPS_SYS(sys_newfstat , 2) 1795 MIPS_SYS(sys_uname , 1) 1796 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 1797 MIPS_SYS(sys_vhangup , 0) 1798 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 1799 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 1800 MIPS_SYS(sys_wait4 , 4) 1801 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 1802 MIPS_SYS(sys_sysinfo , 1) 1803 MIPS_SYS(sys_ipc , 6) 1804 MIPS_SYS(sys_fsync , 1) 1805 MIPS_SYS(sys_sigreturn , 0) 1806 MIPS_SYS(sys_clone , 6) /* 4120 */ 1807 MIPS_SYS(sys_setdomainname, 2) 1808 MIPS_SYS(sys_newuname , 1) 1809 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 1810 MIPS_SYS(sys_adjtimex , 1) 1811 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 1812 MIPS_SYS(sys_sigprocmask , 3) 1813 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 1814 MIPS_SYS(sys_init_module , 5) 1815 MIPS_SYS(sys_delete_module, 1) 1816 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 1817 MIPS_SYS(sys_quotactl , 0) 1818 MIPS_SYS(sys_getpgid , 1) 1819 MIPS_SYS(sys_fchdir , 1) 1820 MIPS_SYS(sys_bdflush , 2) 1821 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 1822 MIPS_SYS(sys_personality , 1) 1823 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 1824 MIPS_SYS(sys_setfsuid , 1) 1825 MIPS_SYS(sys_setfsgid , 1) 1826 MIPS_SYS(sys_llseek , 5) /* 4140 */ 1827 MIPS_SYS(sys_getdents , 3) 1828 MIPS_SYS(sys_select , 5) 1829 MIPS_SYS(sys_flock , 2) 1830 MIPS_SYS(sys_msync , 3) 1831 MIPS_SYS(sys_readv , 3) /* 4145 */ 1832 MIPS_SYS(sys_writev , 3) 1833 MIPS_SYS(sys_cacheflush , 3) 1834 MIPS_SYS(sys_cachectl , 3) 1835 MIPS_SYS(sys_sysmips , 4) 1836 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 1837 MIPS_SYS(sys_getsid , 1) 1838 MIPS_SYS(sys_fdatasync , 0) 1839 MIPS_SYS(sys_sysctl , 1) 1840 MIPS_SYS(sys_mlock , 2) 1841 MIPS_SYS(sys_munlock , 2) /* 4155 */ 1842 MIPS_SYS(sys_mlockall , 1) 1843 MIPS_SYS(sys_munlockall , 0) 1844 MIPS_SYS(sys_sched_setparam, 2) 1845 MIPS_SYS(sys_sched_getparam, 2) 1846 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 1847 MIPS_SYS(sys_sched_getscheduler, 1) 1848 MIPS_SYS(sys_sched_yield , 0) 1849 MIPS_SYS(sys_sched_get_priority_max, 1) 1850 MIPS_SYS(sys_sched_get_priority_min, 1) 1851 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 1852 MIPS_SYS(sys_nanosleep, 2) 1853 MIPS_SYS(sys_mremap , 4) 1854 MIPS_SYS(sys_accept , 3) 1855 MIPS_SYS(sys_bind , 3) 1856 MIPS_SYS(sys_connect , 3) /* 4170 */ 1857 MIPS_SYS(sys_getpeername , 3) 1858 MIPS_SYS(sys_getsockname , 3) 1859 MIPS_SYS(sys_getsockopt , 5) 1860 MIPS_SYS(sys_listen , 2) 1861 MIPS_SYS(sys_recv , 4) /* 4175 */ 1862 MIPS_SYS(sys_recvfrom , 6) 1863 MIPS_SYS(sys_recvmsg , 3) 1864 MIPS_SYS(sys_send , 4) 1865 MIPS_SYS(sys_sendmsg , 3) 1866 MIPS_SYS(sys_sendto , 6) /* 4180 */ 1867 MIPS_SYS(sys_setsockopt , 5) 1868 MIPS_SYS(sys_shutdown , 2) 1869 MIPS_SYS(sys_socket , 3) 1870 MIPS_SYS(sys_socketpair , 4) 1871 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 1872 MIPS_SYS(sys_getresuid , 3) 1873 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 1874 MIPS_SYS(sys_poll , 3) 1875 MIPS_SYS(sys_nfsservctl , 3) 1876 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 1877 MIPS_SYS(sys_getresgid , 3) 1878 MIPS_SYS(sys_prctl , 5) 1879 MIPS_SYS(sys_rt_sigreturn, 0) 1880 MIPS_SYS(sys_rt_sigaction, 4) 1881 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 1882 MIPS_SYS(sys_rt_sigpending, 2) 1883 MIPS_SYS(sys_rt_sigtimedwait, 4) 1884 MIPS_SYS(sys_rt_sigqueueinfo, 3) 1885 MIPS_SYS(sys_rt_sigsuspend, 0) 1886 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 1887 MIPS_SYS(sys_pwrite64 , 6) 1888 MIPS_SYS(sys_chown , 3) 1889 MIPS_SYS(sys_getcwd , 2) 1890 MIPS_SYS(sys_capget , 2) 1891 MIPS_SYS(sys_capset , 2) /* 4205 */ 1892 MIPS_SYS(sys_sigaltstack , 0) 1893 MIPS_SYS(sys_sendfile , 4) 1894 MIPS_SYS(sys_ni_syscall , 0) 1895 MIPS_SYS(sys_ni_syscall , 0) 1896 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 1897 MIPS_SYS(sys_truncate64 , 4) 1898 MIPS_SYS(sys_ftruncate64 , 4) 1899 MIPS_SYS(sys_stat64 , 2) 1900 MIPS_SYS(sys_lstat64 , 2) 1901 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 1902 MIPS_SYS(sys_pivot_root , 2) 1903 MIPS_SYS(sys_mincore , 3) 1904 MIPS_SYS(sys_madvise , 3) 1905 MIPS_SYS(sys_getdents64 , 3) 1906 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 1907 MIPS_SYS(sys_ni_syscall , 0) 1908 MIPS_SYS(sys_gettid , 0) 1909 MIPS_SYS(sys_readahead , 5) 1910 MIPS_SYS(sys_setxattr , 5) 1911 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 1912 MIPS_SYS(sys_fsetxattr , 5) 1913 MIPS_SYS(sys_getxattr , 4) 1914 MIPS_SYS(sys_lgetxattr , 4) 1915 MIPS_SYS(sys_fgetxattr , 4) 1916 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 1917 MIPS_SYS(sys_llistxattr , 3) 1918 MIPS_SYS(sys_flistxattr , 3) 1919 MIPS_SYS(sys_removexattr , 2) 1920 MIPS_SYS(sys_lremovexattr, 2) 1921 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 1922 MIPS_SYS(sys_tkill , 2) 1923 MIPS_SYS(sys_sendfile64 , 5) 1924 MIPS_SYS(sys_futex , 2) 1925 MIPS_SYS(sys_sched_setaffinity, 3) 1926 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 1927 MIPS_SYS(sys_io_setup , 2) 1928 MIPS_SYS(sys_io_destroy , 1) 1929 MIPS_SYS(sys_io_getevents, 5) 1930 MIPS_SYS(sys_io_submit , 3) 1931 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 1932 MIPS_SYS(sys_exit_group , 1) 1933 MIPS_SYS(sys_lookup_dcookie, 3) 1934 MIPS_SYS(sys_epoll_create, 1) 1935 MIPS_SYS(sys_epoll_ctl , 4) 1936 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 1937 MIPS_SYS(sys_remap_file_pages, 5) 1938 MIPS_SYS(sys_set_tid_address, 1) 1939 MIPS_SYS(sys_restart_syscall, 0) 1940 MIPS_SYS(sys_fadvise64_64, 7) 1941 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 1942 MIPS_SYS(sys_fstatfs64 , 2) 1943 MIPS_SYS(sys_timer_create, 3) 1944 MIPS_SYS(sys_timer_settime, 4) 1945 MIPS_SYS(sys_timer_gettime, 2) 1946 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 1947 MIPS_SYS(sys_timer_delete, 1) 1948 MIPS_SYS(sys_clock_settime, 2) 1949 MIPS_SYS(sys_clock_gettime, 2) 1950 MIPS_SYS(sys_clock_getres, 2) 1951 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 1952 MIPS_SYS(sys_tgkill , 3) 1953 MIPS_SYS(sys_utimes , 2) 1954 MIPS_SYS(sys_mbind , 4) 1955 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 1956 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 1957 MIPS_SYS(sys_mq_open , 4) 1958 MIPS_SYS(sys_mq_unlink , 1) 1959 MIPS_SYS(sys_mq_timedsend, 5) 1960 MIPS_SYS(sys_mq_timedreceive, 5) 1961 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 1962 MIPS_SYS(sys_mq_getsetattr, 3) 1963 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 1964 MIPS_SYS(sys_waitid , 4) 1965 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 1966 MIPS_SYS(sys_add_key , 5) 1967 MIPS_SYS(sys_request_key, 4) 1968 MIPS_SYS(sys_keyctl , 5) 1969 MIPS_SYS(sys_set_thread_area, 1) 1970 MIPS_SYS(sys_inotify_init, 0) 1971 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 1972 MIPS_SYS(sys_inotify_rm_watch, 2) 1973 MIPS_SYS(sys_migrate_pages, 4) 1974 MIPS_SYS(sys_openat, 4) 1975 MIPS_SYS(sys_mkdirat, 3) 1976 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 1977 MIPS_SYS(sys_fchownat, 5) 1978 MIPS_SYS(sys_futimesat, 3) 1979 MIPS_SYS(sys_fstatat64, 4) 1980 MIPS_SYS(sys_unlinkat, 3) 1981 MIPS_SYS(sys_renameat, 4) /* 4295 */ 1982 MIPS_SYS(sys_linkat, 5) 1983 MIPS_SYS(sys_symlinkat, 3) 1984 MIPS_SYS(sys_readlinkat, 4) 1985 MIPS_SYS(sys_fchmodat, 3) 1986 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 1987 MIPS_SYS(sys_pselect6, 6) 1988 MIPS_SYS(sys_ppoll, 5) 1989 MIPS_SYS(sys_unshare, 1) 1990 MIPS_SYS(sys_splice, 4) 1991 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 1992 MIPS_SYS(sys_tee, 4) 1993 MIPS_SYS(sys_vmsplice, 4) 1994 MIPS_SYS(sys_move_pages, 6) 1995 MIPS_SYS(sys_set_robust_list, 2) 1996 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 1997 MIPS_SYS(sys_kexec_load, 4) 1998 MIPS_SYS(sys_getcpu, 3) 1999 MIPS_SYS(sys_epoll_pwait, 6) 2000 MIPS_SYS(sys_ioprio_set, 3) 2001 MIPS_SYS(sys_ioprio_get, 2) 2002 }; 2003 2004 #undef MIPS_SYS 2005 2006 static int do_store_exclusive(CPUMIPSState *env) 2007 { 2008 target_ulong addr; 2009 target_ulong page_addr; 2010 target_ulong val; 2011 int flags; 2012 int segv = 0; 2013 int reg; 2014 int d; 2015 2016 addr = env->lladdr; 2017 page_addr = addr & TARGET_PAGE_MASK; 2018 start_exclusive(); 2019 mmap_lock(); 2020 flags = page_get_flags(page_addr); 2021 if ((flags & PAGE_READ) == 0) { 2022 segv = 1; 2023 } else { 2024 reg = env->llreg & 0x1f; 2025 d = (env->llreg & 0x20) != 0; 2026 if (d) { 2027 segv = get_user_s64(val, addr); 2028 } else { 2029 segv = get_user_s32(val, addr); 2030 } 2031 if (!segv) { 2032 if (val != env->llval) { 2033 env->active_tc.gpr[reg] = 0; 2034 } else { 2035 if (d) { 2036 segv = put_user_u64(env->llnewval, addr); 2037 } else { 2038 segv = put_user_u32(env->llnewval, addr); 2039 } 2040 if (!segv) { 2041 env->active_tc.gpr[reg] = 1; 2042 } 2043 } 2044 } 2045 } 2046 env->lladdr = -1; 2047 if (!segv) { 2048 env->active_tc.PC += 4; 2049 } 2050 mmap_unlock(); 2051 end_exclusive(); 2052 return segv; 2053 } 2054 2055 void cpu_loop(CPUMIPSState *env) 2056 { 2057 target_siginfo_t info; 2058 int trapnr, ret; 2059 unsigned int syscall_num; 2060 2061 for(;;) { 2062 cpu_exec_start(env); 2063 trapnr = cpu_mips_exec(env); 2064 cpu_exec_end(env); 2065 switch(trapnr) { 2066 case EXCP_SYSCALL: 2067 syscall_num = env->active_tc.gpr[2] - 4000; 2068 env->active_tc.PC += 4; 2069 if (syscall_num >= sizeof(mips_syscall_args)) { 2070 ret = -ENOSYS; 2071 } else { 2072 int nb_args; 2073 abi_ulong sp_reg; 2074 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2075 2076 nb_args = mips_syscall_args[syscall_num]; 2077 sp_reg = env->active_tc.gpr[29]; 2078 switch (nb_args) { 2079 /* these arguments are taken from the stack */ 2080 /* FIXME - what to do if get_user() fails? */ 2081 case 8: get_user_ual(arg8, sp_reg + 28); 2082 case 7: get_user_ual(arg7, sp_reg + 24); 2083 case 6: get_user_ual(arg6, sp_reg + 20); 2084 case 5: get_user_ual(arg5, sp_reg + 16); 2085 default: 2086 break; 2087 } 2088 ret = do_syscall(env, env->active_tc.gpr[2], 2089 env->active_tc.gpr[4], 2090 env->active_tc.gpr[5], 2091 env->active_tc.gpr[6], 2092 env->active_tc.gpr[7], 2093 arg5, arg6/*, arg7, arg8*/); 2094 } 2095 if (ret == -TARGET_QEMU_ESIGRETURN) { 2096 /* Returning from a successful sigreturn syscall. 2097 Avoid clobbering register state. */ 2098 break; 2099 } 2100 if ((unsigned int)ret >= (unsigned int)(-1133)) { 2101 env->active_tc.gpr[7] = 1; /* error flag */ 2102 ret = -ret; 2103 } else { 2104 env->active_tc.gpr[7] = 0; /* error flag */ 2105 } 2106 env->active_tc.gpr[2] = ret; 2107 break; 2108 case EXCP_TLBL: 2109 case EXCP_TLBS: 2110 info.si_signo = TARGET_SIGSEGV; 2111 info.si_errno = 0; 2112 /* XXX: check env->error_code */ 2113 info.si_code = TARGET_SEGV_MAPERR; 2114 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2115 queue_signal(env, info.si_signo, &info); 2116 break; 2117 case EXCP_CpU: 2118 case EXCP_RI: 2119 info.si_signo = TARGET_SIGILL; 2120 info.si_errno = 0; 2121 info.si_code = 0; 2122 queue_signal(env, info.si_signo, &info); 2123 break; 2124 case EXCP_INTERRUPT: 2125 /* just indicate that signals should be handled asap */ 2126 break; 2127 case EXCP_DEBUG: 2128 { 2129 int sig; 2130 2131 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2132 if (sig) 2133 { 2134 info.si_signo = sig; 2135 info.si_errno = 0; 2136 info.si_code = TARGET_TRAP_BRKPT; 2137 queue_signal(env, info.si_signo, &info); 2138 } 2139 } 2140 break; 2141 case EXCP_SC: 2142 if (do_store_exclusive(env)) { 2143 info.si_signo = TARGET_SIGSEGV; 2144 info.si_errno = 0; 2145 info.si_code = TARGET_SEGV_MAPERR; 2146 info._sifields._sigfault._addr = env->active_tc.PC; 2147 queue_signal(env, info.si_signo, &info); 2148 } 2149 break; 2150 default: 2151 // error: 2152 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2153 trapnr); 2154 cpu_dump_state(env, stderr, fprintf, 0); 2155 abort(); 2156 } 2157 process_pending_signals(env); 2158 } 2159 } 2160 #endif 2161 2162 #ifdef TARGET_SH4 2163 void cpu_loop (CPUState *env) 2164 { 2165 int trapnr, ret; 2166 target_siginfo_t info; 2167 2168 while (1) { 2169 trapnr = cpu_sh4_exec (env); 2170 2171 switch (trapnr) { 2172 case 0x160: 2173 env->pc += 2; 2174 ret = do_syscall(env, 2175 env->gregs[3], 2176 env->gregs[4], 2177 env->gregs[5], 2178 env->gregs[6], 2179 env->gregs[7], 2180 env->gregs[0], 2181 env->gregs[1]); 2182 env->gregs[0] = ret; 2183 break; 2184 case EXCP_INTERRUPT: 2185 /* just indicate that signals should be handled asap */ 2186 break; 2187 case EXCP_DEBUG: 2188 { 2189 int sig; 2190 2191 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2192 if (sig) 2193 { 2194 info.si_signo = sig; 2195 info.si_errno = 0; 2196 info.si_code = TARGET_TRAP_BRKPT; 2197 queue_signal(env, info.si_signo, &info); 2198 } 2199 } 2200 break; 2201 case 0xa0: 2202 case 0xc0: 2203 info.si_signo = SIGSEGV; 2204 info.si_errno = 0; 2205 info.si_code = TARGET_SEGV_MAPERR; 2206 info._sifields._sigfault._addr = env->tea; 2207 queue_signal(env, info.si_signo, &info); 2208 break; 2209 2210 default: 2211 printf ("Unhandled trap: 0x%x\n", trapnr); 2212 cpu_dump_state(env, stderr, fprintf, 0); 2213 exit (1); 2214 } 2215 process_pending_signals (env); 2216 } 2217 } 2218 #endif 2219 2220 #ifdef TARGET_CRIS 2221 void cpu_loop (CPUState *env) 2222 { 2223 int trapnr, ret; 2224 target_siginfo_t info; 2225 2226 while (1) { 2227 trapnr = cpu_cris_exec (env); 2228 switch (trapnr) { 2229 case 0xaa: 2230 { 2231 info.si_signo = SIGSEGV; 2232 info.si_errno = 0; 2233 /* XXX: check env->error_code */ 2234 info.si_code = TARGET_SEGV_MAPERR; 2235 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2236 queue_signal(env, info.si_signo, &info); 2237 } 2238 break; 2239 case EXCP_INTERRUPT: 2240 /* just indicate that signals should be handled asap */ 2241 break; 2242 case EXCP_BREAK: 2243 ret = do_syscall(env, 2244 env->regs[9], 2245 env->regs[10], 2246 env->regs[11], 2247 env->regs[12], 2248 env->regs[13], 2249 env->pregs[7], 2250 env->pregs[11]); 2251 env->regs[10] = ret; 2252 break; 2253 case EXCP_DEBUG: 2254 { 2255 int sig; 2256 2257 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2258 if (sig) 2259 { 2260 info.si_signo = sig; 2261 info.si_errno = 0; 2262 info.si_code = TARGET_TRAP_BRKPT; 2263 queue_signal(env, info.si_signo, &info); 2264 } 2265 } 2266 break; 2267 default: 2268 printf ("Unhandled trap: 0x%x\n", trapnr); 2269 cpu_dump_state(env, stderr, fprintf, 0); 2270 exit (1); 2271 } 2272 process_pending_signals (env); 2273 } 2274 } 2275 #endif 2276 2277 #ifdef TARGET_MICROBLAZE 2278 void cpu_loop (CPUState *env) 2279 { 2280 int trapnr, ret; 2281 target_siginfo_t info; 2282 2283 while (1) { 2284 trapnr = cpu_mb_exec (env); 2285 switch (trapnr) { 2286 case 0xaa: 2287 { 2288 info.si_signo = SIGSEGV; 2289 info.si_errno = 0; 2290 /* XXX: check env->error_code */ 2291 info.si_code = TARGET_SEGV_MAPERR; 2292 info._sifields._sigfault._addr = 0; 2293 queue_signal(env, info.si_signo, &info); 2294 } 2295 break; 2296 case EXCP_INTERRUPT: 2297 /* just indicate that signals should be handled asap */ 2298 break; 2299 case EXCP_BREAK: 2300 /* Return address is 4 bytes after the call. */ 2301 env->regs[14] += 4; 2302 ret = do_syscall(env, 2303 env->regs[12], 2304 env->regs[5], 2305 env->regs[6], 2306 env->regs[7], 2307 env->regs[8], 2308 env->regs[9], 2309 env->regs[10]); 2310 env->regs[3] = ret; 2311 env->sregs[SR_PC] = env->regs[14]; 2312 break; 2313 case EXCP_HW_EXCP: 2314 env->regs[17] = env->sregs[SR_PC] + 4; 2315 if (env->iflags & D_FLAG) { 2316 env->sregs[SR_ESR] |= 1 << 12; 2317 env->sregs[SR_PC] -= 4; 2318 /* FIXME: if branch was immed, replay the imm aswell. */ 2319 } 2320 2321 env->iflags &= ~(IMM_FLAG | D_FLAG); 2322 2323 switch (env->sregs[SR_ESR] & 31) { 2324 case ESR_EC_FPU: 2325 info.si_signo = SIGFPE; 2326 info.si_errno = 0; 2327 if (env->sregs[SR_FSR] & FSR_IO) { 2328 info.si_code = TARGET_FPE_FLTINV; 2329 } 2330 if (env->sregs[SR_FSR] & FSR_DZ) { 2331 info.si_code = TARGET_FPE_FLTDIV; 2332 } 2333 info._sifields._sigfault._addr = 0; 2334 queue_signal(env, info.si_signo, &info); 2335 break; 2336 default: 2337 printf ("Unhandled hw-exception: 0x%x\n", 2338 env->sregs[SR_ESR] & ESR_EC_MASK); 2339 cpu_dump_state(env, stderr, fprintf, 0); 2340 exit (1); 2341 break; 2342 } 2343 break; 2344 case EXCP_DEBUG: 2345 { 2346 int sig; 2347 2348 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2349 if (sig) 2350 { 2351 info.si_signo = sig; 2352 info.si_errno = 0; 2353 info.si_code = TARGET_TRAP_BRKPT; 2354 queue_signal(env, info.si_signo, &info); 2355 } 2356 } 2357 break; 2358 default: 2359 printf ("Unhandled trap: 0x%x\n", trapnr); 2360 cpu_dump_state(env, stderr, fprintf, 0); 2361 exit (1); 2362 } 2363 process_pending_signals (env); 2364 } 2365 } 2366 #endif 2367 2368 #ifdef TARGET_M68K 2369 2370 void cpu_loop(CPUM68KState *env) 2371 { 2372 int trapnr; 2373 unsigned int n; 2374 target_siginfo_t info; 2375 TaskState *ts = env->opaque; 2376 2377 for(;;) { 2378 trapnr = cpu_m68k_exec(env); 2379 switch(trapnr) { 2380 case EXCP_ILLEGAL: 2381 { 2382 if (ts->sim_syscalls) { 2383 uint16_t nr; 2384 nr = lduw(env->pc + 2); 2385 env->pc += 4; 2386 do_m68k_simcall(env, nr); 2387 } else { 2388 goto do_sigill; 2389 } 2390 } 2391 break; 2392 case EXCP_HALT_INSN: 2393 /* Semihosing syscall. */ 2394 env->pc += 4; 2395 do_m68k_semihosting(env, env->dregs[0]); 2396 break; 2397 case EXCP_LINEA: 2398 case EXCP_LINEF: 2399 case EXCP_UNSUPPORTED: 2400 do_sigill: 2401 info.si_signo = SIGILL; 2402 info.si_errno = 0; 2403 info.si_code = TARGET_ILL_ILLOPN; 2404 info._sifields._sigfault._addr = env->pc; 2405 queue_signal(env, info.si_signo, &info); 2406 break; 2407 case EXCP_TRAP0: 2408 { 2409 ts->sim_syscalls = 0; 2410 n = env->dregs[0]; 2411 env->pc += 2; 2412 env->dregs[0] = do_syscall(env, 2413 n, 2414 env->dregs[1], 2415 env->dregs[2], 2416 env->dregs[3], 2417 env->dregs[4], 2418 env->dregs[5], 2419 env->aregs[0]); 2420 } 2421 break; 2422 case EXCP_INTERRUPT: 2423 /* just indicate that signals should be handled asap */ 2424 break; 2425 case EXCP_ACCESS: 2426 { 2427 info.si_signo = SIGSEGV; 2428 info.si_errno = 0; 2429 /* XXX: check env->error_code */ 2430 info.si_code = TARGET_SEGV_MAPERR; 2431 info._sifields._sigfault._addr = env->mmu.ar; 2432 queue_signal(env, info.si_signo, &info); 2433 } 2434 break; 2435 case EXCP_DEBUG: 2436 { 2437 int sig; 2438 2439 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2440 if (sig) 2441 { 2442 info.si_signo = sig; 2443 info.si_errno = 0; 2444 info.si_code = TARGET_TRAP_BRKPT; 2445 queue_signal(env, info.si_signo, &info); 2446 } 2447 } 2448 break; 2449 default: 2450 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2451 trapnr); 2452 cpu_dump_state(env, stderr, fprintf, 0); 2453 abort(); 2454 } 2455 process_pending_signals(env); 2456 } 2457 } 2458 #endif /* TARGET_M68K */ 2459 2460 #ifdef TARGET_ALPHA 2461 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 2462 { 2463 target_ulong addr, val, tmp; 2464 target_siginfo_t info; 2465 int ret = 0; 2466 2467 addr = env->lock_addr; 2468 tmp = env->lock_st_addr; 2469 env->lock_addr = -1; 2470 env->lock_st_addr = 0; 2471 2472 start_exclusive(); 2473 mmap_lock(); 2474 2475 if (addr == tmp) { 2476 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 2477 goto do_sigsegv; 2478 } 2479 2480 if (val == env->lock_value) { 2481 tmp = env->ir[reg]; 2482 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 2483 goto do_sigsegv; 2484 } 2485 ret = 1; 2486 } 2487 } 2488 env->ir[reg] = ret; 2489 env->pc += 4; 2490 2491 mmap_unlock(); 2492 end_exclusive(); 2493 return; 2494 2495 do_sigsegv: 2496 mmap_unlock(); 2497 end_exclusive(); 2498 2499 info.si_signo = TARGET_SIGSEGV; 2500 info.si_errno = 0; 2501 info.si_code = TARGET_SEGV_MAPERR; 2502 info._sifields._sigfault._addr = addr; 2503 queue_signal(env, TARGET_SIGSEGV, &info); 2504 } 2505 2506 void cpu_loop (CPUState *env) 2507 { 2508 int trapnr; 2509 target_siginfo_t info; 2510 abi_long sysret; 2511 2512 while (1) { 2513 trapnr = cpu_alpha_exec (env); 2514 2515 /* All of the traps imply a transition through PALcode, which 2516 implies an REI instruction has been executed. Which means 2517 that the intr_flag should be cleared. */ 2518 env->intr_flag = 0; 2519 2520 switch (trapnr) { 2521 case EXCP_RESET: 2522 fprintf(stderr, "Reset requested. Exit\n"); 2523 exit(1); 2524 break; 2525 case EXCP_MCHK: 2526 fprintf(stderr, "Machine check exception. Exit\n"); 2527 exit(1); 2528 break; 2529 case EXCP_ARITH: 2530 env->lock_addr = -1; 2531 info.si_signo = TARGET_SIGFPE; 2532 info.si_errno = 0; 2533 info.si_code = TARGET_FPE_FLTINV; 2534 info._sifields._sigfault._addr = env->pc; 2535 queue_signal(env, info.si_signo, &info); 2536 break; 2537 case EXCP_HW_INTERRUPT: 2538 fprintf(stderr, "External interrupt. Exit\n"); 2539 exit(1); 2540 break; 2541 case EXCP_DFAULT: 2542 env->lock_addr = -1; 2543 info.si_signo = TARGET_SIGSEGV; 2544 info.si_errno = 0; 2545 info.si_code = (page_get_flags(env->ipr[IPR_EXC_ADDR]) & PAGE_VALID 2546 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 2547 info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR]; 2548 queue_signal(env, info.si_signo, &info); 2549 break; 2550 case EXCP_DTB_MISS_PAL: 2551 fprintf(stderr, "MMU data TLB miss in PALcode\n"); 2552 exit(1); 2553 break; 2554 case EXCP_ITB_MISS: 2555 fprintf(stderr, "MMU instruction TLB miss\n"); 2556 exit(1); 2557 break; 2558 case EXCP_ITB_ACV: 2559 fprintf(stderr, "MMU instruction access violation\n"); 2560 exit(1); 2561 break; 2562 case EXCP_DTB_MISS_NATIVE: 2563 fprintf(stderr, "MMU data TLB miss\n"); 2564 exit(1); 2565 break; 2566 case EXCP_UNALIGN: 2567 env->lock_addr = -1; 2568 info.si_signo = TARGET_SIGBUS; 2569 info.si_errno = 0; 2570 info.si_code = TARGET_BUS_ADRALN; 2571 info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR]; 2572 queue_signal(env, info.si_signo, &info); 2573 break; 2574 case EXCP_OPCDEC: 2575 do_sigill: 2576 env->lock_addr = -1; 2577 info.si_signo = TARGET_SIGILL; 2578 info.si_errno = 0; 2579 info.si_code = TARGET_ILL_ILLOPC; 2580 info._sifields._sigfault._addr = env->pc; 2581 queue_signal(env, info.si_signo, &info); 2582 break; 2583 case EXCP_FEN: 2584 /* No-op. Linux simply re-enables the FPU. */ 2585 break; 2586 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1): 2587 env->lock_addr = -1; 2588 switch ((trapnr >> 6) | 0x80) { 2589 case 0x80: 2590 /* BPT */ 2591 info.si_signo = TARGET_SIGTRAP; 2592 info.si_errno = 0; 2593 info.si_code = TARGET_TRAP_BRKPT; 2594 info._sifields._sigfault._addr = env->pc; 2595 queue_signal(env, info.si_signo, &info); 2596 break; 2597 case 0x81: 2598 /* BUGCHK */ 2599 info.si_signo = TARGET_SIGTRAP; 2600 info.si_errno = 0; 2601 info.si_code = 0; 2602 info._sifields._sigfault._addr = env->pc; 2603 queue_signal(env, info.si_signo, &info); 2604 break; 2605 case 0x83: 2606 /* CALLSYS */ 2607 trapnr = env->ir[IR_V0]; 2608 sysret = do_syscall(env, trapnr, 2609 env->ir[IR_A0], env->ir[IR_A1], 2610 env->ir[IR_A2], env->ir[IR_A3], 2611 env->ir[IR_A4], env->ir[IR_A5]); 2612 if (trapnr == TARGET_NR_sigreturn 2613 || trapnr == TARGET_NR_rt_sigreturn) { 2614 break; 2615 } 2616 /* Syscall writes 0 to V0 to bypass error check, similar 2617 to how this is handled internal to Linux kernel. */ 2618 if (env->ir[IR_V0] == 0) { 2619 env->ir[IR_V0] = sysret; 2620 } else { 2621 env->ir[IR_V0] = (sysret < 0 ? -sysret : sysret); 2622 env->ir[IR_A3] = (sysret < 0); 2623 } 2624 break; 2625 case 0x86: 2626 /* IMB */ 2627 /* ??? We can probably elide the code using page_unprotect 2628 that is checking for self-modifying code. Instead we 2629 could simply call tb_flush here. Until we work out the 2630 changes required to turn off the extra write protection, 2631 this can be a no-op. */ 2632 break; 2633 case 0x9E: 2634 /* RDUNIQUE */ 2635 /* Handled in the translator for usermode. */ 2636 abort(); 2637 case 0x9F: 2638 /* WRUNIQUE */ 2639 /* Handled in the translator for usermode. */ 2640 abort(); 2641 case 0xAA: 2642 /* GENTRAP */ 2643 info.si_signo = TARGET_SIGFPE; 2644 switch (env->ir[IR_A0]) { 2645 case TARGET_GEN_INTOVF: 2646 info.si_code = TARGET_FPE_INTOVF; 2647 break; 2648 case TARGET_GEN_INTDIV: 2649 info.si_code = TARGET_FPE_INTDIV; 2650 break; 2651 case TARGET_GEN_FLTOVF: 2652 info.si_code = TARGET_FPE_FLTOVF; 2653 break; 2654 case TARGET_GEN_FLTUND: 2655 info.si_code = TARGET_FPE_FLTUND; 2656 break; 2657 case TARGET_GEN_FLTINV: 2658 info.si_code = TARGET_FPE_FLTINV; 2659 break; 2660 case TARGET_GEN_FLTINE: 2661 info.si_code = TARGET_FPE_FLTRES; 2662 break; 2663 case TARGET_GEN_ROPRAND: 2664 info.si_code = 0; 2665 break; 2666 default: 2667 info.si_signo = TARGET_SIGTRAP; 2668 info.si_code = 0; 2669 break; 2670 } 2671 info.si_errno = 0; 2672 info._sifields._sigfault._addr = env->pc; 2673 queue_signal(env, info.si_signo, &info); 2674 break; 2675 default: 2676 goto do_sigill; 2677 } 2678 break; 2679 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1): 2680 goto do_sigill; 2681 case EXCP_DEBUG: 2682 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP); 2683 if (info.si_signo) { 2684 env->lock_addr = -1; 2685 info.si_errno = 0; 2686 info.si_code = TARGET_TRAP_BRKPT; 2687 queue_signal(env, info.si_signo, &info); 2688 } 2689 break; 2690 case EXCP_STL_C: 2691 case EXCP_STQ_C: 2692 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 2693 break; 2694 default: 2695 printf ("Unhandled trap: 0x%x\n", trapnr); 2696 cpu_dump_state(env, stderr, fprintf, 0); 2697 exit (1); 2698 } 2699 process_pending_signals (env); 2700 } 2701 } 2702 #endif /* TARGET_ALPHA */ 2703 2704 static void version(void) 2705 { 2706 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION 2707 ", Copyright (c) 2003-2008 Fabrice Bellard\n"); 2708 } 2709 2710 static void usage(void) 2711 { 2712 version(); 2713 printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n" 2714 "Linux CPU emulator (compiled for %s emulation)\n" 2715 "\n" 2716 "Standard options:\n" 2717 "-h print this help\n" 2718 "-version display version information and exit\n" 2719 "-g port wait gdb connection to port\n" 2720 "-L path set the elf interpreter prefix (default=%s)\n" 2721 "-s size set the stack size in bytes (default=%ld)\n" 2722 "-cpu model select CPU (-cpu ? for list)\n" 2723 "-drop-ld-preload drop LD_PRELOAD for target process\n" 2724 "-E var=value sets/modifies targets environment variable(s)\n" 2725 "-U var unsets targets environment variable(s)\n" 2726 "-0 argv0 forces target process argv[0] to be argv0\n" 2727 #if defined(CONFIG_USE_GUEST_BASE) 2728 "-B address set guest_base address to address\n" 2729 "-R size reserve size bytes for guest virtual address space\n" 2730 #endif 2731 "\n" 2732 "Debug options:\n" 2733 "-d options activate log (logfile=%s)\n" 2734 "-p pagesize set the host page size to 'pagesize'\n" 2735 "-singlestep always run in singlestep mode\n" 2736 "-strace log system calls\n" 2737 "\n" 2738 "Environment variables:\n" 2739 "QEMU_STRACE Print system calls and arguments similar to the\n" 2740 " 'strace' program. Enable by setting to any value.\n" 2741 "You can use -E and -U options to set/unset environment variables\n" 2742 "for target process. It is possible to provide several variables\n" 2743 "by repeating the option. For example:\n" 2744 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 2745 "Note that if you provide several changes to single variable\n" 2746 "last change will stay in effect.\n" 2747 , 2748 TARGET_ARCH, 2749 interp_prefix, 2750 guest_stack_size, 2751 DEBUG_LOGFILE); 2752 exit(1); 2753 } 2754 2755 THREAD CPUState *thread_env; 2756 2757 void task_settid(TaskState *ts) 2758 { 2759 if (ts->ts_tid == 0) { 2760 #ifdef CONFIG_USE_NPTL 2761 ts->ts_tid = (pid_t)syscall(SYS_gettid); 2762 #else 2763 /* when no threads are used, tid becomes pid */ 2764 ts->ts_tid = getpid(); 2765 #endif 2766 } 2767 } 2768 2769 void stop_all_tasks(void) 2770 { 2771 /* 2772 * We trust that when using NPTL, start_exclusive() 2773 * handles thread stopping correctly. 2774 */ 2775 start_exclusive(); 2776 } 2777 2778 /* Assumes contents are already zeroed. */ 2779 void init_task_state(TaskState *ts) 2780 { 2781 int i; 2782 2783 ts->used = 1; 2784 ts->first_free = ts->sigqueue_table; 2785 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 2786 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 2787 } 2788 ts->sigqueue_table[i].next = NULL; 2789 } 2790 2791 int main(int argc, char **argv, char **envp) 2792 { 2793 const char *filename; 2794 const char *cpu_model; 2795 struct target_pt_regs regs1, *regs = ®s1; 2796 struct image_info info1, *info = &info1; 2797 struct linux_binprm bprm; 2798 TaskState *ts; 2799 CPUState *env; 2800 int optind; 2801 const char *r; 2802 int gdbstub_port = 0; 2803 char **target_environ, **wrk; 2804 char **target_argv; 2805 int target_argc; 2806 envlist_t *envlist = NULL; 2807 const char *argv0 = NULL; 2808 int i; 2809 int ret; 2810 2811 if (argc <= 1) 2812 usage(); 2813 2814 qemu_cache_utils_init(envp); 2815 2816 /* init debug */ 2817 cpu_set_log_filename(DEBUG_LOGFILE); 2818 2819 if ((envlist = envlist_create()) == NULL) { 2820 (void) fprintf(stderr, "Unable to allocate envlist\n"); 2821 exit(1); 2822 } 2823 2824 /* add current environment into the list */ 2825 for (wrk = environ; *wrk != NULL; wrk++) { 2826 (void) envlist_setenv(envlist, *wrk); 2827 } 2828 2829 /* Read the stack limit from the kernel. If it's "unlimited", 2830 then we can do little else besides use the default. */ 2831 { 2832 struct rlimit lim; 2833 if (getrlimit(RLIMIT_STACK, &lim) == 0 2834 && lim.rlim_cur != RLIM_INFINITY 2835 && lim.rlim_cur == (target_long)lim.rlim_cur) { 2836 guest_stack_size = lim.rlim_cur; 2837 } 2838 } 2839 2840 cpu_model = NULL; 2841 #if defined(cpudef_setup) 2842 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ 2843 #endif 2844 2845 optind = 1; 2846 for(;;) { 2847 if (optind >= argc) 2848 break; 2849 r = argv[optind]; 2850 if (r[0] != '-') 2851 break; 2852 optind++; 2853 r++; 2854 if (!strcmp(r, "-")) { 2855 break; 2856 } else if (!strcmp(r, "d")) { 2857 int mask; 2858 const CPULogItem *item; 2859 2860 if (optind >= argc) 2861 break; 2862 2863 r = argv[optind++]; 2864 mask = cpu_str_to_log_mask(r); 2865 if (!mask) { 2866 printf("Log items (comma separated):\n"); 2867 for(item = cpu_log_items; item->mask != 0; item++) { 2868 printf("%-10s %s\n", item->name, item->help); 2869 } 2870 exit(1); 2871 } 2872 cpu_set_log(mask); 2873 } else if (!strcmp(r, "E")) { 2874 r = argv[optind++]; 2875 if (envlist_setenv(envlist, r) != 0) 2876 usage(); 2877 } else if (!strcmp(r, "ignore-environment")) { 2878 envlist_free(envlist); 2879 if ((envlist = envlist_create()) == NULL) { 2880 (void) fprintf(stderr, "Unable to allocate envlist\n"); 2881 exit(1); 2882 } 2883 } else if (!strcmp(r, "U")) { 2884 r = argv[optind++]; 2885 if (envlist_unsetenv(envlist, r) != 0) 2886 usage(); 2887 } else if (!strcmp(r, "0")) { 2888 r = argv[optind++]; 2889 argv0 = r; 2890 } else if (!strcmp(r, "s")) { 2891 if (optind >= argc) 2892 break; 2893 r = argv[optind++]; 2894 guest_stack_size = strtoul(r, (char **)&r, 0); 2895 if (guest_stack_size == 0) 2896 usage(); 2897 if (*r == 'M') 2898 guest_stack_size *= 1024 * 1024; 2899 else if (*r == 'k' || *r == 'K') 2900 guest_stack_size *= 1024; 2901 } else if (!strcmp(r, "L")) { 2902 interp_prefix = argv[optind++]; 2903 } else if (!strcmp(r, "p")) { 2904 if (optind >= argc) 2905 break; 2906 qemu_host_page_size = atoi(argv[optind++]); 2907 if (qemu_host_page_size == 0 || 2908 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 2909 fprintf(stderr, "page size must be a power of two\n"); 2910 exit(1); 2911 } 2912 } else if (!strcmp(r, "g")) { 2913 if (optind >= argc) 2914 break; 2915 gdbstub_port = atoi(argv[optind++]); 2916 } else if (!strcmp(r, "r")) { 2917 qemu_uname_release = argv[optind++]; 2918 } else if (!strcmp(r, "cpu")) { 2919 cpu_model = argv[optind++]; 2920 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) { 2921 /* XXX: implement xxx_cpu_list for targets that still miss it */ 2922 #if defined(cpu_list_id) 2923 cpu_list_id(stdout, &fprintf, ""); 2924 #elif defined(cpu_list) 2925 cpu_list(stdout, &fprintf); /* deprecated */ 2926 #endif 2927 exit(1); 2928 } 2929 #if defined(CONFIG_USE_GUEST_BASE) 2930 } else if (!strcmp(r, "B")) { 2931 guest_base = strtol(argv[optind++], NULL, 0); 2932 have_guest_base = 1; 2933 } else if (!strcmp(r, "R")) { 2934 char *p; 2935 int shift = 0; 2936 reserved_va = strtoul(argv[optind++], &p, 0); 2937 switch (*p) { 2938 case 'k': 2939 case 'K': 2940 shift = 10; 2941 break; 2942 case 'M': 2943 shift = 20; 2944 break; 2945 case 'G': 2946 shift = 30; 2947 break; 2948 } 2949 if (shift) { 2950 unsigned long unshifted = reserved_va; 2951 p++; 2952 reserved_va <<= shift; 2953 if (((reserved_va >> shift) != unshifted) 2954 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 2955 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 2956 #endif 2957 ) { 2958 fprintf(stderr, "Reserved virtual address too big\n"); 2959 exit(1); 2960 } 2961 } 2962 if (*p) { 2963 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 2964 exit(1); 2965 } 2966 #endif 2967 } else if (!strcmp(r, "drop-ld-preload")) { 2968 (void) envlist_unsetenv(envlist, "LD_PRELOAD"); 2969 } else if (!strcmp(r, "singlestep")) { 2970 singlestep = 1; 2971 } else if (!strcmp(r, "strace")) { 2972 do_strace = 1; 2973 } else if (!strcmp(r, "version")) { 2974 version(); 2975 exit(0); 2976 } else { 2977 usage(); 2978 } 2979 } 2980 if (optind >= argc) 2981 usage(); 2982 filename = argv[optind]; 2983 exec_path = argv[optind]; 2984 2985 /* Zero out regs */ 2986 memset(regs, 0, sizeof(struct target_pt_regs)); 2987 2988 /* Zero out image_info */ 2989 memset(info, 0, sizeof(struct image_info)); 2990 2991 memset(&bprm, 0, sizeof (bprm)); 2992 2993 /* Scan interp_prefix dir for replacement files. */ 2994 init_paths(interp_prefix); 2995 2996 if (cpu_model == NULL) { 2997 #if defined(TARGET_I386) 2998 #ifdef TARGET_X86_64 2999 cpu_model = "qemu64"; 3000 #else 3001 cpu_model = "qemu32"; 3002 #endif 3003 #elif defined(TARGET_ARM) 3004 cpu_model = "any"; 3005 #elif defined(TARGET_UNICORE32) 3006 cpu_model = "any"; 3007 #elif defined(TARGET_M68K) 3008 cpu_model = "any"; 3009 #elif defined(TARGET_SPARC) 3010 #ifdef TARGET_SPARC64 3011 cpu_model = "TI UltraSparc II"; 3012 #else 3013 cpu_model = "Fujitsu MB86904"; 3014 #endif 3015 #elif defined(TARGET_MIPS) 3016 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 3017 cpu_model = "20Kc"; 3018 #else 3019 cpu_model = "24Kf"; 3020 #endif 3021 #elif defined(TARGET_PPC) 3022 #ifdef TARGET_PPC64 3023 cpu_model = "970fx"; 3024 #else 3025 cpu_model = "750"; 3026 #endif 3027 #else 3028 cpu_model = "any"; 3029 #endif 3030 } 3031 cpu_exec_init_all(0); 3032 /* NOTE: we need to init the CPU at this stage to get 3033 qemu_host_page_size */ 3034 env = cpu_init(cpu_model); 3035 if (!env) { 3036 fprintf(stderr, "Unable to find CPU definition\n"); 3037 exit(1); 3038 } 3039 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) 3040 cpu_reset(env); 3041 #endif 3042 3043 thread_env = env; 3044 3045 if (getenv("QEMU_STRACE")) { 3046 do_strace = 1; 3047 } 3048 3049 target_environ = envlist_to_environ(envlist, NULL); 3050 envlist_free(envlist); 3051 3052 #if defined(CONFIG_USE_GUEST_BASE) 3053 /* 3054 * Now that page sizes are configured in cpu_init() we can do 3055 * proper page alignment for guest_base. 3056 */ 3057 guest_base = HOST_PAGE_ALIGN(guest_base); 3058 3059 if (reserved_va) { 3060 void *p; 3061 int flags; 3062 3063 flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE; 3064 if (have_guest_base) { 3065 flags |= MAP_FIXED; 3066 } 3067 p = mmap((void *)guest_base, reserved_va, PROT_NONE, flags, -1, 0); 3068 if (p == MAP_FAILED) { 3069 fprintf(stderr, "Unable to reserve guest address space\n"); 3070 exit(1); 3071 } 3072 guest_base = (unsigned long)p; 3073 /* Make sure the address is properly aligned. */ 3074 if (guest_base & ~qemu_host_page_mask) { 3075 munmap(p, reserved_va); 3076 p = mmap((void *)guest_base, reserved_va + qemu_host_page_size, 3077 PROT_NONE, flags, -1, 0); 3078 if (p == MAP_FAILED) { 3079 fprintf(stderr, "Unable to reserve guest address space\n"); 3080 exit(1); 3081 } 3082 guest_base = HOST_PAGE_ALIGN((unsigned long)p); 3083 } 3084 qemu_log("Reserved 0x%lx bytes of guest address space\n", reserved_va); 3085 } 3086 #endif /* CONFIG_USE_GUEST_BASE */ 3087 3088 /* 3089 * Read in mmap_min_addr kernel parameter. This value is used 3090 * When loading the ELF image to determine whether guest_base 3091 * is needed. It is also used in mmap_find_vma. 3092 */ 3093 { 3094 FILE *fp; 3095 3096 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 3097 unsigned long tmp; 3098 if (fscanf(fp, "%lu", &tmp) == 1) { 3099 mmap_min_addr = tmp; 3100 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); 3101 } 3102 fclose(fp); 3103 } 3104 } 3105 3106 /* 3107 * Prepare copy of argv vector for target. 3108 */ 3109 target_argc = argc - optind; 3110 target_argv = calloc(target_argc + 1, sizeof (char *)); 3111 if (target_argv == NULL) { 3112 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 3113 exit(1); 3114 } 3115 3116 /* 3117 * If argv0 is specified (using '-0' switch) we replace 3118 * argv[0] pointer with the given one. 3119 */ 3120 i = 0; 3121 if (argv0 != NULL) { 3122 target_argv[i++] = strdup(argv0); 3123 } 3124 for (; i < target_argc; i++) { 3125 target_argv[i] = strdup(argv[optind + i]); 3126 } 3127 target_argv[target_argc] = NULL; 3128 3129 ts = qemu_mallocz (sizeof(TaskState)); 3130 init_task_state(ts); 3131 /* build Task State */ 3132 ts->info = info; 3133 ts->bprm = &bprm; 3134 env->opaque = ts; 3135 task_settid(ts); 3136 3137 ret = loader_exec(filename, target_argv, target_environ, regs, 3138 info, &bprm); 3139 if (ret != 0) { 3140 printf("Error %d while loading %s\n", ret, filename); 3141 _exit(1); 3142 } 3143 3144 for (i = 0; i < target_argc; i++) { 3145 free(target_argv[i]); 3146 } 3147 free(target_argv); 3148 3149 for (wrk = target_environ; *wrk; wrk++) { 3150 free(*wrk); 3151 } 3152 3153 free(target_environ); 3154 3155 if (qemu_log_enabled()) { 3156 #if defined(CONFIG_USE_GUEST_BASE) 3157 qemu_log("guest_base 0x%lx\n", guest_base); 3158 #endif 3159 log_page_dump(); 3160 3161 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 3162 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 3163 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 3164 info->start_code); 3165 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 3166 info->start_data); 3167 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 3168 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 3169 info->start_stack); 3170 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 3171 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 3172 } 3173 3174 target_set_brk(info->brk); 3175 syscall_init(); 3176 signal_init(); 3177 3178 #if defined(CONFIG_USE_GUEST_BASE) 3179 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 3180 generating the prologue until now so that the prologue can take 3181 the real value of GUEST_BASE into account. */ 3182 tcg_prologue_init(&tcg_ctx); 3183 #endif 3184 3185 #if defined(TARGET_I386) 3186 cpu_x86_set_cpl(env, 3); 3187 3188 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 3189 env->hflags |= HF_PE_MASK; 3190 if (env->cpuid_features & CPUID_SSE) { 3191 env->cr[4] |= CR4_OSFXSR_MASK; 3192 env->hflags |= HF_OSFXSR_MASK; 3193 } 3194 #ifndef TARGET_ABI32 3195 /* enable 64 bit mode if possible */ 3196 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) { 3197 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 3198 exit(1); 3199 } 3200 env->cr[4] |= CR4_PAE_MASK; 3201 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 3202 env->hflags |= HF_LMA_MASK; 3203 #endif 3204 3205 /* flags setup : we activate the IRQs by default as in user mode */ 3206 env->eflags |= IF_MASK; 3207 3208 /* linux register setup */ 3209 #ifndef TARGET_ABI32 3210 env->regs[R_EAX] = regs->rax; 3211 env->regs[R_EBX] = regs->rbx; 3212 env->regs[R_ECX] = regs->rcx; 3213 env->regs[R_EDX] = regs->rdx; 3214 env->regs[R_ESI] = regs->rsi; 3215 env->regs[R_EDI] = regs->rdi; 3216 env->regs[R_EBP] = regs->rbp; 3217 env->regs[R_ESP] = regs->rsp; 3218 env->eip = regs->rip; 3219 #else 3220 env->regs[R_EAX] = regs->eax; 3221 env->regs[R_EBX] = regs->ebx; 3222 env->regs[R_ECX] = regs->ecx; 3223 env->regs[R_EDX] = regs->edx; 3224 env->regs[R_ESI] = regs->esi; 3225 env->regs[R_EDI] = regs->edi; 3226 env->regs[R_EBP] = regs->ebp; 3227 env->regs[R_ESP] = regs->esp; 3228 env->eip = regs->eip; 3229 #endif 3230 3231 /* linux interrupt setup */ 3232 #ifndef TARGET_ABI32 3233 env->idt.limit = 511; 3234 #else 3235 env->idt.limit = 255; 3236 #endif 3237 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 3238 PROT_READ|PROT_WRITE, 3239 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 3240 idt_table = g2h(env->idt.base); 3241 set_idt(0, 0); 3242 set_idt(1, 0); 3243 set_idt(2, 0); 3244 set_idt(3, 3); 3245 set_idt(4, 3); 3246 set_idt(5, 0); 3247 set_idt(6, 0); 3248 set_idt(7, 0); 3249 set_idt(8, 0); 3250 set_idt(9, 0); 3251 set_idt(10, 0); 3252 set_idt(11, 0); 3253 set_idt(12, 0); 3254 set_idt(13, 0); 3255 set_idt(14, 0); 3256 set_idt(15, 0); 3257 set_idt(16, 0); 3258 set_idt(17, 0); 3259 set_idt(18, 0); 3260 set_idt(19, 0); 3261 set_idt(0x80, 3); 3262 3263 /* linux segment setup */ 3264 { 3265 uint64_t *gdt_table; 3266 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 3267 PROT_READ|PROT_WRITE, 3268 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 3269 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 3270 gdt_table = g2h(env->gdt.base); 3271 #ifdef TARGET_ABI32 3272 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 3273 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 3274 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 3275 #else 3276 /* 64 bit code segment */ 3277 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 3278 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 3279 DESC_L_MASK | 3280 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 3281 #endif 3282 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 3283 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 3284 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 3285 } 3286 cpu_x86_load_seg(env, R_CS, __USER_CS); 3287 cpu_x86_load_seg(env, R_SS, __USER_DS); 3288 #ifdef TARGET_ABI32 3289 cpu_x86_load_seg(env, R_DS, __USER_DS); 3290 cpu_x86_load_seg(env, R_ES, __USER_DS); 3291 cpu_x86_load_seg(env, R_FS, __USER_DS); 3292 cpu_x86_load_seg(env, R_GS, __USER_DS); 3293 /* This hack makes Wine work... */ 3294 env->segs[R_FS].selector = 0; 3295 #else 3296 cpu_x86_load_seg(env, R_DS, 0); 3297 cpu_x86_load_seg(env, R_ES, 0); 3298 cpu_x86_load_seg(env, R_FS, 0); 3299 cpu_x86_load_seg(env, R_GS, 0); 3300 #endif 3301 #elif defined(TARGET_ARM) 3302 { 3303 int i; 3304 cpsr_write(env, regs->uregs[16], 0xffffffff); 3305 for(i = 0; i < 16; i++) { 3306 env->regs[i] = regs->uregs[i]; 3307 } 3308 } 3309 #elif defined(TARGET_UNICORE32) 3310 { 3311 int i; 3312 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 3313 for (i = 0; i < 32; i++) { 3314 env->regs[i] = regs->uregs[i]; 3315 } 3316 } 3317 #elif defined(TARGET_SPARC) 3318 { 3319 int i; 3320 env->pc = regs->pc; 3321 env->npc = regs->npc; 3322 env->y = regs->y; 3323 for(i = 0; i < 8; i++) 3324 env->gregs[i] = regs->u_regs[i]; 3325 for(i = 0; i < 8; i++) 3326 env->regwptr[i] = regs->u_regs[i + 8]; 3327 } 3328 #elif defined(TARGET_PPC) 3329 { 3330 int i; 3331 3332 #if defined(TARGET_PPC64) 3333 #if defined(TARGET_ABI32) 3334 env->msr &= ~((target_ulong)1 << MSR_SF); 3335 #else 3336 env->msr |= (target_ulong)1 << MSR_SF; 3337 #endif 3338 #endif 3339 env->nip = regs->nip; 3340 for(i = 0; i < 32; i++) { 3341 env->gpr[i] = regs->gpr[i]; 3342 } 3343 } 3344 #elif defined(TARGET_M68K) 3345 { 3346 env->pc = regs->pc; 3347 env->dregs[0] = regs->d0; 3348 env->dregs[1] = regs->d1; 3349 env->dregs[2] = regs->d2; 3350 env->dregs[3] = regs->d3; 3351 env->dregs[4] = regs->d4; 3352 env->dregs[5] = regs->d5; 3353 env->dregs[6] = regs->d6; 3354 env->dregs[7] = regs->d7; 3355 env->aregs[0] = regs->a0; 3356 env->aregs[1] = regs->a1; 3357 env->aregs[2] = regs->a2; 3358 env->aregs[3] = regs->a3; 3359 env->aregs[4] = regs->a4; 3360 env->aregs[5] = regs->a5; 3361 env->aregs[6] = regs->a6; 3362 env->aregs[7] = regs->usp; 3363 env->sr = regs->sr; 3364 ts->sim_syscalls = 1; 3365 } 3366 #elif defined(TARGET_MICROBLAZE) 3367 { 3368 env->regs[0] = regs->r0; 3369 env->regs[1] = regs->r1; 3370 env->regs[2] = regs->r2; 3371 env->regs[3] = regs->r3; 3372 env->regs[4] = regs->r4; 3373 env->regs[5] = regs->r5; 3374 env->regs[6] = regs->r6; 3375 env->regs[7] = regs->r7; 3376 env->regs[8] = regs->r8; 3377 env->regs[9] = regs->r9; 3378 env->regs[10] = regs->r10; 3379 env->regs[11] = regs->r11; 3380 env->regs[12] = regs->r12; 3381 env->regs[13] = regs->r13; 3382 env->regs[14] = regs->r14; 3383 env->regs[15] = regs->r15; 3384 env->regs[16] = regs->r16; 3385 env->regs[17] = regs->r17; 3386 env->regs[18] = regs->r18; 3387 env->regs[19] = regs->r19; 3388 env->regs[20] = regs->r20; 3389 env->regs[21] = regs->r21; 3390 env->regs[22] = regs->r22; 3391 env->regs[23] = regs->r23; 3392 env->regs[24] = regs->r24; 3393 env->regs[25] = regs->r25; 3394 env->regs[26] = regs->r26; 3395 env->regs[27] = regs->r27; 3396 env->regs[28] = regs->r28; 3397 env->regs[29] = regs->r29; 3398 env->regs[30] = regs->r30; 3399 env->regs[31] = regs->r31; 3400 env->sregs[SR_PC] = regs->pc; 3401 } 3402 #elif defined(TARGET_MIPS) 3403 { 3404 int i; 3405 3406 for(i = 0; i < 32; i++) { 3407 env->active_tc.gpr[i] = regs->regs[i]; 3408 } 3409 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 3410 if (regs->cp0_epc & 1) { 3411 env->hflags |= MIPS_HFLAG_M16; 3412 } 3413 } 3414 #elif defined(TARGET_SH4) 3415 { 3416 int i; 3417 3418 for(i = 0; i < 16; i++) { 3419 env->gregs[i] = regs->regs[i]; 3420 } 3421 env->pc = regs->pc; 3422 } 3423 #elif defined(TARGET_ALPHA) 3424 { 3425 int i; 3426 3427 for(i = 0; i < 28; i++) { 3428 env->ir[i] = ((abi_ulong *)regs)[i]; 3429 } 3430 env->ir[IR_SP] = regs->usp; 3431 env->pc = regs->pc; 3432 } 3433 #elif defined(TARGET_CRIS) 3434 { 3435 env->regs[0] = regs->r0; 3436 env->regs[1] = regs->r1; 3437 env->regs[2] = regs->r2; 3438 env->regs[3] = regs->r3; 3439 env->regs[4] = regs->r4; 3440 env->regs[5] = regs->r5; 3441 env->regs[6] = regs->r6; 3442 env->regs[7] = regs->r7; 3443 env->regs[8] = regs->r8; 3444 env->regs[9] = regs->r9; 3445 env->regs[10] = regs->r10; 3446 env->regs[11] = regs->r11; 3447 env->regs[12] = regs->r12; 3448 env->regs[13] = regs->r13; 3449 env->regs[14] = info->start_stack; 3450 env->regs[15] = regs->acr; 3451 env->pc = regs->erp; 3452 } 3453 #else 3454 #error unsupported target CPU 3455 #endif 3456 3457 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 3458 ts->stack_base = info->start_stack; 3459 ts->heap_base = info->brk; 3460 /* This will be filled in on the first SYS_HEAPINFO call. */ 3461 ts->heap_limit = 0; 3462 #endif 3463 3464 if (gdbstub_port) { 3465 gdbserver_start (gdbstub_port); 3466 gdb_handlesig(env, 0); 3467 } 3468 cpu_loop(env); 3469 /* never exits */ 3470 return 0; 3471 } 3472