1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include <sys/mman.h> 21 #include <sys/syscall.h> 22 #include <sys/resource.h> 23 24 #include "qemu.h" 25 #include "qemu/path.h" 26 #include "qemu/cutils.h" 27 #include "qemu/help_option.h" 28 #include "cpu.h" 29 #include "exec/exec-all.h" 30 #include "tcg.h" 31 #include "qemu/timer.h" 32 #include "qemu/envlist.h" 33 #include "elf.h" 34 #include "exec/log.h" 35 36 char *exec_path; 37 38 int singlestep; 39 static const char *filename; 40 static const char *argv0; 41 static int gdbstub_port; 42 static envlist_t *envlist; 43 static const char *cpu_model; 44 unsigned long mmap_min_addr; 45 unsigned long guest_base; 46 int have_guest_base; 47 48 #define EXCP_DUMP(env, fmt, ...) \ 49 do { \ 50 CPUState *cs = ENV_GET_CPU(env); \ 51 fprintf(stderr, fmt , ## __VA_ARGS__); \ 52 cpu_dump_state(cs, stderr, fprintf, 0); \ 53 if (qemu_log_separate()) { \ 54 qemu_log(fmt, ## __VA_ARGS__); \ 55 log_cpu_state(cs, 0); \ 56 } \ 57 } while (0) 58 59 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 60 /* 61 * When running 32-on-64 we should make sure we can fit all of the possible 62 * guest address space into a contiguous chunk of virtual host memory. 63 * 64 * This way we will never overlap with our own libraries or binaries or stack 65 * or anything else that QEMU maps. 66 */ 67 # ifdef TARGET_MIPS 68 /* MIPS only supports 31 bits of virtual address space for user space */ 69 unsigned long reserved_va = 0x77000000; 70 # else 71 unsigned long reserved_va = 0xf7000000; 72 # endif 73 #else 74 unsigned long reserved_va; 75 #endif 76 77 static void usage(int exitcode); 78 79 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 80 const char *qemu_uname_release; 81 82 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 83 we allocate a bigger stack. Need a better solution, for example 84 by remapping the process stack directly at the right place */ 85 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 86 87 void gemu_log(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vfprintf(stderr, fmt, ap); 93 va_end(ap); 94 } 95 96 #if defined(TARGET_I386) 97 int cpu_get_pic_interrupt(CPUX86State *env) 98 { 99 return -1; 100 } 101 #endif 102 103 /***********************************************************/ 104 /* Helper routines for implementing atomic operations. */ 105 106 /* To implement exclusive operations we force all cpus to syncronise. 107 We don't require a full sync, only that no cpus are executing guest code. 108 The alternative is to map target atomic ops onto host equivalents, 109 which requires quite a lot of per host/target work. */ 110 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; 111 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 112 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 113 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 114 static int pending_cpus; 115 116 /* Make sure everything is in a consistent state for calling fork(). */ 117 void fork_start(void) 118 { 119 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 120 pthread_mutex_lock(&exclusive_lock); 121 mmap_fork_start(); 122 } 123 124 void fork_end(int child) 125 { 126 mmap_fork_end(child); 127 if (child) { 128 CPUState *cpu, *next_cpu; 129 /* Child processes created by fork() only have a single thread. 130 Discard information about the parent threads. */ 131 CPU_FOREACH_SAFE(cpu, next_cpu) { 132 if (cpu != thread_cpu) { 133 QTAILQ_REMOVE(&cpus, thread_cpu, node); 134 } 135 } 136 pending_cpus = 0; 137 pthread_mutex_init(&exclusive_lock, NULL); 138 pthread_mutex_init(&cpu_list_mutex, NULL); 139 pthread_cond_init(&exclusive_cond, NULL); 140 pthread_cond_init(&exclusive_resume, NULL); 141 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); 142 gdbserver_fork(thread_cpu); 143 } else { 144 pthread_mutex_unlock(&exclusive_lock); 145 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 146 } 147 } 148 149 /* Wait for pending exclusive operations to complete. The exclusive lock 150 must be held. */ 151 static inline void exclusive_idle(void) 152 { 153 while (pending_cpus) { 154 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 155 } 156 } 157 158 /* Start an exclusive operation. 159 Must only be called from outside cpu_arm_exec. */ 160 static inline void start_exclusive(void) 161 { 162 CPUState *other_cpu; 163 164 pthread_mutex_lock(&exclusive_lock); 165 exclusive_idle(); 166 167 pending_cpus = 1; 168 /* Make all other cpus stop executing. */ 169 CPU_FOREACH(other_cpu) { 170 if (other_cpu->running) { 171 pending_cpus++; 172 cpu_exit(other_cpu); 173 } 174 } 175 if (pending_cpus > 1) { 176 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 177 } 178 } 179 180 /* Finish an exclusive operation. */ 181 static inline void __attribute__((unused)) end_exclusive(void) 182 { 183 pending_cpus = 0; 184 pthread_cond_broadcast(&exclusive_resume); 185 pthread_mutex_unlock(&exclusive_lock); 186 } 187 188 /* Wait for exclusive ops to finish, and begin cpu execution. */ 189 static inline void cpu_exec_start(CPUState *cpu) 190 { 191 pthread_mutex_lock(&exclusive_lock); 192 exclusive_idle(); 193 cpu->running = true; 194 pthread_mutex_unlock(&exclusive_lock); 195 } 196 197 /* Mark cpu as not executing, and release pending exclusive ops. */ 198 static inline void cpu_exec_end(CPUState *cpu) 199 { 200 pthread_mutex_lock(&exclusive_lock); 201 cpu->running = false; 202 if (pending_cpus > 1) { 203 pending_cpus--; 204 if (pending_cpus == 1) { 205 pthread_cond_signal(&exclusive_cond); 206 } 207 } 208 exclusive_idle(); 209 pthread_mutex_unlock(&exclusive_lock); 210 } 211 212 void cpu_list_lock(void) 213 { 214 pthread_mutex_lock(&cpu_list_mutex); 215 } 216 217 void cpu_list_unlock(void) 218 { 219 pthread_mutex_unlock(&cpu_list_mutex); 220 } 221 222 223 #ifdef TARGET_I386 224 /***********************************************************/ 225 /* CPUX86 core interface */ 226 227 uint64_t cpu_get_tsc(CPUX86State *env) 228 { 229 return cpu_get_host_ticks(); 230 } 231 232 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 233 int flags) 234 { 235 unsigned int e1, e2; 236 uint32_t *p; 237 e1 = (addr << 16) | (limit & 0xffff); 238 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 239 e2 |= flags; 240 p = ptr; 241 p[0] = tswap32(e1); 242 p[1] = tswap32(e2); 243 } 244 245 static uint64_t *idt_table; 246 #ifdef TARGET_X86_64 247 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 248 uint64_t addr, unsigned int sel) 249 { 250 uint32_t *p, e1, e2; 251 e1 = (addr & 0xffff) | (sel << 16); 252 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 253 p = ptr; 254 p[0] = tswap32(e1); 255 p[1] = tswap32(e2); 256 p[2] = tswap32(addr >> 32); 257 p[3] = 0; 258 } 259 /* only dpl matters as we do only user space emulation */ 260 static void set_idt(int n, unsigned int dpl) 261 { 262 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 263 } 264 #else 265 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 266 uint32_t addr, unsigned int sel) 267 { 268 uint32_t *p, e1, e2; 269 e1 = (addr & 0xffff) | (sel << 16); 270 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 271 p = ptr; 272 p[0] = tswap32(e1); 273 p[1] = tswap32(e2); 274 } 275 276 /* only dpl matters as we do only user space emulation */ 277 static void set_idt(int n, unsigned int dpl) 278 { 279 set_gate(idt_table + n, 0, dpl, 0, 0); 280 } 281 #endif 282 283 void cpu_loop(CPUX86State *env) 284 { 285 CPUState *cs = CPU(x86_env_get_cpu(env)); 286 int trapnr; 287 abi_ulong pc; 288 target_siginfo_t info; 289 290 for(;;) { 291 cpu_exec_start(cs); 292 trapnr = cpu_x86_exec(cs); 293 cpu_exec_end(cs); 294 switch(trapnr) { 295 case 0x80: 296 /* linux syscall from int $0x80 */ 297 env->regs[R_EAX] = do_syscall(env, 298 env->regs[R_EAX], 299 env->regs[R_EBX], 300 env->regs[R_ECX], 301 env->regs[R_EDX], 302 env->regs[R_ESI], 303 env->regs[R_EDI], 304 env->regs[R_EBP], 305 0, 0); 306 break; 307 #ifndef TARGET_ABI32 308 case EXCP_SYSCALL: 309 /* linux syscall from syscall instruction */ 310 env->regs[R_EAX] = do_syscall(env, 311 env->regs[R_EAX], 312 env->regs[R_EDI], 313 env->regs[R_ESI], 314 env->regs[R_EDX], 315 env->regs[10], 316 env->regs[8], 317 env->regs[9], 318 0, 0); 319 break; 320 #endif 321 case EXCP0B_NOSEG: 322 case EXCP0C_STACK: 323 info.si_signo = TARGET_SIGBUS; 324 info.si_errno = 0; 325 info.si_code = TARGET_SI_KERNEL; 326 info._sifields._sigfault._addr = 0; 327 queue_signal(env, info.si_signo, &info); 328 break; 329 case EXCP0D_GPF: 330 /* XXX: potential problem if ABI32 */ 331 #ifndef TARGET_X86_64 332 if (env->eflags & VM_MASK) { 333 handle_vm86_fault(env); 334 } else 335 #endif 336 { 337 info.si_signo = TARGET_SIGSEGV; 338 info.si_errno = 0; 339 info.si_code = TARGET_SI_KERNEL; 340 info._sifields._sigfault._addr = 0; 341 queue_signal(env, info.si_signo, &info); 342 } 343 break; 344 case EXCP0E_PAGE: 345 info.si_signo = TARGET_SIGSEGV; 346 info.si_errno = 0; 347 if (!(env->error_code & 1)) 348 info.si_code = TARGET_SEGV_MAPERR; 349 else 350 info.si_code = TARGET_SEGV_ACCERR; 351 info._sifields._sigfault._addr = env->cr[2]; 352 queue_signal(env, info.si_signo, &info); 353 break; 354 case EXCP00_DIVZ: 355 #ifndef TARGET_X86_64 356 if (env->eflags & VM_MASK) { 357 handle_vm86_trap(env, trapnr); 358 } else 359 #endif 360 { 361 /* division by zero */ 362 info.si_signo = TARGET_SIGFPE; 363 info.si_errno = 0; 364 info.si_code = TARGET_FPE_INTDIV; 365 info._sifields._sigfault._addr = env->eip; 366 queue_signal(env, info.si_signo, &info); 367 } 368 break; 369 case EXCP01_DB: 370 case EXCP03_INT3: 371 #ifndef TARGET_X86_64 372 if (env->eflags & VM_MASK) { 373 handle_vm86_trap(env, trapnr); 374 } else 375 #endif 376 { 377 info.si_signo = TARGET_SIGTRAP; 378 info.si_errno = 0; 379 if (trapnr == EXCP01_DB) { 380 info.si_code = TARGET_TRAP_BRKPT; 381 info._sifields._sigfault._addr = env->eip; 382 } else { 383 info.si_code = TARGET_SI_KERNEL; 384 info._sifields._sigfault._addr = 0; 385 } 386 queue_signal(env, info.si_signo, &info); 387 } 388 break; 389 case EXCP04_INTO: 390 case EXCP05_BOUND: 391 #ifndef TARGET_X86_64 392 if (env->eflags & VM_MASK) { 393 handle_vm86_trap(env, trapnr); 394 } else 395 #endif 396 { 397 info.si_signo = TARGET_SIGSEGV; 398 info.si_errno = 0; 399 info.si_code = TARGET_SI_KERNEL; 400 info._sifields._sigfault._addr = 0; 401 queue_signal(env, info.si_signo, &info); 402 } 403 break; 404 case EXCP06_ILLOP: 405 info.si_signo = TARGET_SIGILL; 406 info.si_errno = 0; 407 info.si_code = TARGET_ILL_ILLOPN; 408 info._sifields._sigfault._addr = env->eip; 409 queue_signal(env, info.si_signo, &info); 410 break; 411 case EXCP_INTERRUPT: 412 /* just indicate that signals should be handled asap */ 413 break; 414 case EXCP_DEBUG: 415 { 416 int sig; 417 418 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 419 if (sig) 420 { 421 info.si_signo = sig; 422 info.si_errno = 0; 423 info.si_code = TARGET_TRAP_BRKPT; 424 queue_signal(env, info.si_signo, &info); 425 } 426 } 427 break; 428 default: 429 pc = env->segs[R_CS].base + env->eip; 430 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 431 (long)pc, trapnr); 432 abort(); 433 } 434 process_pending_signals(env); 435 } 436 } 437 #endif 438 439 #ifdef TARGET_ARM 440 441 #define get_user_code_u32(x, gaddr, env) \ 442 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 443 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 444 (x) = bswap32(x); \ 445 } \ 446 __r; \ 447 }) 448 449 #define get_user_code_u16(x, gaddr, env) \ 450 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 451 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 452 (x) = bswap16(x); \ 453 } \ 454 __r; \ 455 }) 456 457 #define get_user_data_u32(x, gaddr, env) \ 458 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 459 if (!__r && arm_cpu_bswap_data(env)) { \ 460 (x) = bswap32(x); \ 461 } \ 462 __r; \ 463 }) 464 465 #define get_user_data_u16(x, gaddr, env) \ 466 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 467 if (!__r && arm_cpu_bswap_data(env)) { \ 468 (x) = bswap16(x); \ 469 } \ 470 __r; \ 471 }) 472 473 #define put_user_data_u32(x, gaddr, env) \ 474 ({ typeof(x) __x = (x); \ 475 if (arm_cpu_bswap_data(env)) { \ 476 __x = bswap32(__x); \ 477 } \ 478 put_user_u32(__x, (gaddr)); \ 479 }) 480 481 #define put_user_data_u16(x, gaddr, env) \ 482 ({ typeof(x) __x = (x); \ 483 if (arm_cpu_bswap_data(env)) { \ 484 __x = bswap16(__x); \ 485 } \ 486 put_user_u16(__x, (gaddr)); \ 487 }) 488 489 #ifdef TARGET_ABI32 490 /* Commpage handling -- there is no commpage for AArch64 */ 491 492 /* 493 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 494 * Input: 495 * r0 = pointer to oldval 496 * r1 = pointer to newval 497 * r2 = pointer to target value 498 * 499 * Output: 500 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 501 * C set if *ptr was changed, clear if no exchange happened 502 * 503 * Note segv's in kernel helpers are a bit tricky, we can set the 504 * data address sensibly but the PC address is just the entry point. 505 */ 506 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 507 { 508 uint64_t oldval, newval, val; 509 uint32_t addr, cpsr; 510 target_siginfo_t info; 511 512 /* Based on the 32 bit code in do_kernel_trap */ 513 514 /* XXX: This only works between threads, not between processes. 515 It's probably possible to implement this with native host 516 operations. However things like ldrex/strex are much harder so 517 there's not much point trying. */ 518 start_exclusive(); 519 cpsr = cpsr_read(env); 520 addr = env->regs[2]; 521 522 if (get_user_u64(oldval, env->regs[0])) { 523 env->exception.vaddress = env->regs[0]; 524 goto segv; 525 }; 526 527 if (get_user_u64(newval, env->regs[1])) { 528 env->exception.vaddress = env->regs[1]; 529 goto segv; 530 }; 531 532 if (get_user_u64(val, addr)) { 533 env->exception.vaddress = addr; 534 goto segv; 535 } 536 537 if (val == oldval) { 538 val = newval; 539 540 if (put_user_u64(val, addr)) { 541 env->exception.vaddress = addr; 542 goto segv; 543 }; 544 545 env->regs[0] = 0; 546 cpsr |= CPSR_C; 547 } else { 548 env->regs[0] = -1; 549 cpsr &= ~CPSR_C; 550 } 551 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 552 end_exclusive(); 553 return; 554 555 segv: 556 end_exclusive(); 557 /* We get the PC of the entry address - which is as good as anything, 558 on a real kernel what you get depends on which mode it uses. */ 559 info.si_signo = TARGET_SIGSEGV; 560 info.si_errno = 0; 561 /* XXX: check env->error_code */ 562 info.si_code = TARGET_SEGV_MAPERR; 563 info._sifields._sigfault._addr = env->exception.vaddress; 564 queue_signal(env, info.si_signo, &info); 565 } 566 567 /* Handle a jump to the kernel code page. */ 568 static int 569 do_kernel_trap(CPUARMState *env) 570 { 571 uint32_t addr; 572 uint32_t cpsr; 573 uint32_t val; 574 575 switch (env->regs[15]) { 576 case 0xffff0fa0: /* __kernel_memory_barrier */ 577 /* ??? No-op. Will need to do better for SMP. */ 578 break; 579 case 0xffff0fc0: /* __kernel_cmpxchg */ 580 /* XXX: This only works between threads, not between processes. 581 It's probably possible to implement this with native host 582 operations. However things like ldrex/strex are much harder so 583 there's not much point trying. */ 584 start_exclusive(); 585 cpsr = cpsr_read(env); 586 addr = env->regs[2]; 587 /* FIXME: This should SEGV if the access fails. */ 588 if (get_user_u32(val, addr)) 589 val = ~env->regs[0]; 590 if (val == env->regs[0]) { 591 val = env->regs[1]; 592 /* FIXME: Check for segfaults. */ 593 put_user_u32(val, addr); 594 env->regs[0] = 0; 595 cpsr |= CPSR_C; 596 } else { 597 env->regs[0] = -1; 598 cpsr &= ~CPSR_C; 599 } 600 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 601 end_exclusive(); 602 break; 603 case 0xffff0fe0: /* __kernel_get_tls */ 604 env->regs[0] = cpu_get_tls(env); 605 break; 606 case 0xffff0f60: /* __kernel_cmpxchg64 */ 607 arm_kernel_cmpxchg64_helper(env); 608 break; 609 610 default: 611 return 1; 612 } 613 /* Jump back to the caller. */ 614 addr = env->regs[14]; 615 if (addr & 1) { 616 env->thumb = 1; 617 addr &= ~1; 618 } 619 env->regs[15] = addr; 620 621 return 0; 622 } 623 624 /* Store exclusive handling for AArch32 */ 625 static int do_strex(CPUARMState *env) 626 { 627 uint64_t val; 628 int size; 629 int rc = 1; 630 int segv = 0; 631 uint32_t addr; 632 start_exclusive(); 633 if (env->exclusive_addr != env->exclusive_test) { 634 goto fail; 635 } 636 /* We know we're always AArch32 so the address is in uint32_t range 637 * unless it was the -1 exclusive-monitor-lost value (which won't 638 * match exclusive_test above). 639 */ 640 assert(extract64(env->exclusive_addr, 32, 32) == 0); 641 addr = env->exclusive_addr; 642 size = env->exclusive_info & 0xf; 643 switch (size) { 644 case 0: 645 segv = get_user_u8(val, addr); 646 break; 647 case 1: 648 segv = get_user_data_u16(val, addr, env); 649 break; 650 case 2: 651 case 3: 652 segv = get_user_data_u32(val, addr, env); 653 break; 654 default: 655 abort(); 656 } 657 if (segv) { 658 env->exception.vaddress = addr; 659 goto done; 660 } 661 if (size == 3) { 662 uint32_t valhi; 663 segv = get_user_data_u32(valhi, addr + 4, env); 664 if (segv) { 665 env->exception.vaddress = addr + 4; 666 goto done; 667 } 668 if (arm_cpu_bswap_data(env)) { 669 val = deposit64((uint64_t)valhi, 32, 32, val); 670 } else { 671 val = deposit64(val, 32, 32, valhi); 672 } 673 } 674 if (val != env->exclusive_val) { 675 goto fail; 676 } 677 678 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 679 switch (size) { 680 case 0: 681 segv = put_user_u8(val, addr); 682 break; 683 case 1: 684 segv = put_user_data_u16(val, addr, env); 685 break; 686 case 2: 687 case 3: 688 segv = put_user_data_u32(val, addr, env); 689 break; 690 } 691 if (segv) { 692 env->exception.vaddress = addr; 693 goto done; 694 } 695 if (size == 3) { 696 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 697 segv = put_user_data_u32(val, addr + 4, env); 698 if (segv) { 699 env->exception.vaddress = addr + 4; 700 goto done; 701 } 702 } 703 rc = 0; 704 fail: 705 env->regs[15] += 4; 706 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 707 done: 708 end_exclusive(); 709 return segv; 710 } 711 712 void cpu_loop(CPUARMState *env) 713 { 714 CPUState *cs = CPU(arm_env_get_cpu(env)); 715 int trapnr; 716 unsigned int n, insn; 717 target_siginfo_t info; 718 uint32_t addr; 719 720 for(;;) { 721 cpu_exec_start(cs); 722 trapnr = cpu_arm_exec(cs); 723 cpu_exec_end(cs); 724 switch(trapnr) { 725 case EXCP_UDEF: 726 { 727 TaskState *ts = cs->opaque; 728 uint32_t opcode; 729 int rc; 730 731 /* we handle the FPU emulation here, as Linux */ 732 /* we get the opcode */ 733 /* FIXME - what to do if get_user() fails? */ 734 get_user_code_u32(opcode, env->regs[15], env); 735 736 rc = EmulateAll(opcode, &ts->fpa, env); 737 if (rc == 0) { /* illegal instruction */ 738 info.si_signo = TARGET_SIGILL; 739 info.si_errno = 0; 740 info.si_code = TARGET_ILL_ILLOPN; 741 info._sifields._sigfault._addr = env->regs[15]; 742 queue_signal(env, info.si_signo, &info); 743 } else if (rc < 0) { /* FP exception */ 744 int arm_fpe=0; 745 746 /* translate softfloat flags to FPSR flags */ 747 if (-rc & float_flag_invalid) 748 arm_fpe |= BIT_IOC; 749 if (-rc & float_flag_divbyzero) 750 arm_fpe |= BIT_DZC; 751 if (-rc & float_flag_overflow) 752 arm_fpe |= BIT_OFC; 753 if (-rc & float_flag_underflow) 754 arm_fpe |= BIT_UFC; 755 if (-rc & float_flag_inexact) 756 arm_fpe |= BIT_IXC; 757 758 FPSR fpsr = ts->fpa.fpsr; 759 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 760 761 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 762 info.si_signo = TARGET_SIGFPE; 763 info.si_errno = 0; 764 765 /* ordered by priority, least first */ 766 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 767 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 768 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 769 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 770 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 771 772 info._sifields._sigfault._addr = env->regs[15]; 773 queue_signal(env, info.si_signo, &info); 774 } else { 775 env->regs[15] += 4; 776 } 777 778 /* accumulate unenabled exceptions */ 779 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 780 fpsr |= BIT_IXC; 781 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 782 fpsr |= BIT_UFC; 783 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 784 fpsr |= BIT_OFC; 785 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 786 fpsr |= BIT_DZC; 787 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 788 fpsr |= BIT_IOC; 789 ts->fpa.fpsr=fpsr; 790 } else { /* everything OK */ 791 /* increment PC */ 792 env->regs[15] += 4; 793 } 794 } 795 break; 796 case EXCP_SWI: 797 case EXCP_BKPT: 798 { 799 env->eabi = 1; 800 /* system call */ 801 if (trapnr == EXCP_BKPT) { 802 if (env->thumb) { 803 /* FIXME - what to do if get_user() fails? */ 804 get_user_code_u16(insn, env->regs[15], env); 805 n = insn & 0xff; 806 env->regs[15] += 2; 807 } else { 808 /* FIXME - what to do if get_user() fails? */ 809 get_user_code_u32(insn, env->regs[15], env); 810 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 811 env->regs[15] += 4; 812 } 813 } else { 814 if (env->thumb) { 815 /* FIXME - what to do if get_user() fails? */ 816 get_user_code_u16(insn, env->regs[15] - 2, env); 817 n = insn & 0xff; 818 } else { 819 /* FIXME - what to do if get_user() fails? */ 820 get_user_code_u32(insn, env->regs[15] - 4, env); 821 n = insn & 0xffffff; 822 } 823 } 824 825 if (n == ARM_NR_cacheflush) { 826 /* nop */ 827 } else if (n == ARM_NR_semihosting 828 || n == ARM_NR_thumb_semihosting) { 829 env->regs[0] = do_arm_semihosting (env); 830 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 831 /* linux syscall */ 832 if (env->thumb || n == 0) { 833 n = env->regs[7]; 834 } else { 835 n -= ARM_SYSCALL_BASE; 836 env->eabi = 0; 837 } 838 if ( n > ARM_NR_BASE) { 839 switch (n) { 840 case ARM_NR_cacheflush: 841 /* nop */ 842 break; 843 case ARM_NR_set_tls: 844 cpu_set_tls(env, env->regs[0]); 845 env->regs[0] = 0; 846 break; 847 case ARM_NR_breakpoint: 848 env->regs[15] -= env->thumb ? 2 : 4; 849 goto excp_debug; 850 default: 851 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 852 n); 853 env->regs[0] = -TARGET_ENOSYS; 854 break; 855 } 856 } else { 857 env->regs[0] = do_syscall(env, 858 n, 859 env->regs[0], 860 env->regs[1], 861 env->regs[2], 862 env->regs[3], 863 env->regs[4], 864 env->regs[5], 865 0, 0); 866 } 867 } else { 868 goto error; 869 } 870 } 871 break; 872 case EXCP_INTERRUPT: 873 /* just indicate that signals should be handled asap */ 874 break; 875 case EXCP_STREX: 876 if (!do_strex(env)) { 877 break; 878 } 879 /* fall through for segv */ 880 case EXCP_PREFETCH_ABORT: 881 case EXCP_DATA_ABORT: 882 addr = env->exception.vaddress; 883 { 884 info.si_signo = TARGET_SIGSEGV; 885 info.si_errno = 0; 886 /* XXX: check env->error_code */ 887 info.si_code = TARGET_SEGV_MAPERR; 888 info._sifields._sigfault._addr = addr; 889 queue_signal(env, info.si_signo, &info); 890 } 891 break; 892 case EXCP_DEBUG: 893 excp_debug: 894 { 895 int sig; 896 897 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 898 if (sig) 899 { 900 info.si_signo = sig; 901 info.si_errno = 0; 902 info.si_code = TARGET_TRAP_BRKPT; 903 queue_signal(env, info.si_signo, &info); 904 } 905 } 906 break; 907 case EXCP_KERNEL_TRAP: 908 if (do_kernel_trap(env)) 909 goto error; 910 break; 911 case EXCP_YIELD: 912 /* nothing to do here for user-mode, just resume guest code */ 913 break; 914 default: 915 error: 916 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 917 abort(); 918 } 919 process_pending_signals(env); 920 } 921 } 922 923 #else 924 925 /* 926 * Handle AArch64 store-release exclusive 927 * 928 * rs = gets the status result of store exclusive 929 * rt = is the register that is stored 930 * rt2 = is the second register store (in STP) 931 * 932 */ 933 static int do_strex_a64(CPUARMState *env) 934 { 935 uint64_t val; 936 int size; 937 bool is_pair; 938 int rc = 1; 939 int segv = 0; 940 uint64_t addr; 941 int rs, rt, rt2; 942 943 start_exclusive(); 944 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ 945 size = extract32(env->exclusive_info, 0, 2); 946 is_pair = extract32(env->exclusive_info, 2, 1); 947 rs = extract32(env->exclusive_info, 4, 5); 948 rt = extract32(env->exclusive_info, 9, 5); 949 rt2 = extract32(env->exclusive_info, 14, 5); 950 951 addr = env->exclusive_addr; 952 953 if (addr != env->exclusive_test) { 954 goto finish; 955 } 956 957 switch (size) { 958 case 0: 959 segv = get_user_u8(val, addr); 960 break; 961 case 1: 962 segv = get_user_u16(val, addr); 963 break; 964 case 2: 965 segv = get_user_u32(val, addr); 966 break; 967 case 3: 968 segv = get_user_u64(val, addr); 969 break; 970 default: 971 abort(); 972 } 973 if (segv) { 974 env->exception.vaddress = addr; 975 goto error; 976 } 977 if (val != env->exclusive_val) { 978 goto finish; 979 } 980 if (is_pair) { 981 if (size == 2) { 982 segv = get_user_u32(val, addr + 4); 983 } else { 984 segv = get_user_u64(val, addr + 8); 985 } 986 if (segv) { 987 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 988 goto error; 989 } 990 if (val != env->exclusive_high) { 991 goto finish; 992 } 993 } 994 /* handle the zero register */ 995 val = rt == 31 ? 0 : env->xregs[rt]; 996 switch (size) { 997 case 0: 998 segv = put_user_u8(val, addr); 999 break; 1000 case 1: 1001 segv = put_user_u16(val, addr); 1002 break; 1003 case 2: 1004 segv = put_user_u32(val, addr); 1005 break; 1006 case 3: 1007 segv = put_user_u64(val, addr); 1008 break; 1009 } 1010 if (segv) { 1011 goto error; 1012 } 1013 if (is_pair) { 1014 /* handle the zero register */ 1015 val = rt2 == 31 ? 0 : env->xregs[rt2]; 1016 if (size == 2) { 1017 segv = put_user_u32(val, addr + 4); 1018 } else { 1019 segv = put_user_u64(val, addr + 8); 1020 } 1021 if (segv) { 1022 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 1023 goto error; 1024 } 1025 } 1026 rc = 0; 1027 finish: 1028 env->pc += 4; 1029 /* rs == 31 encodes a write to the ZR, thus throwing away 1030 * the status return. This is rather silly but valid. 1031 */ 1032 if (rs < 31) { 1033 env->xregs[rs] = rc; 1034 } 1035 error: 1036 /* instruction faulted, PC does not advance */ 1037 /* either way a strex releases any exclusive lock we have */ 1038 env->exclusive_addr = -1; 1039 end_exclusive(); 1040 return segv; 1041 } 1042 1043 /* AArch64 main loop */ 1044 void cpu_loop(CPUARMState *env) 1045 { 1046 CPUState *cs = CPU(arm_env_get_cpu(env)); 1047 int trapnr, sig; 1048 target_siginfo_t info; 1049 1050 for (;;) { 1051 cpu_exec_start(cs); 1052 trapnr = cpu_arm_exec(cs); 1053 cpu_exec_end(cs); 1054 1055 switch (trapnr) { 1056 case EXCP_SWI: 1057 env->xregs[0] = do_syscall(env, 1058 env->xregs[8], 1059 env->xregs[0], 1060 env->xregs[1], 1061 env->xregs[2], 1062 env->xregs[3], 1063 env->xregs[4], 1064 env->xregs[5], 1065 0, 0); 1066 break; 1067 case EXCP_INTERRUPT: 1068 /* just indicate that signals should be handled asap */ 1069 break; 1070 case EXCP_UDEF: 1071 info.si_signo = TARGET_SIGILL; 1072 info.si_errno = 0; 1073 info.si_code = TARGET_ILL_ILLOPN; 1074 info._sifields._sigfault._addr = env->pc; 1075 queue_signal(env, info.si_signo, &info); 1076 break; 1077 case EXCP_STREX: 1078 if (!do_strex_a64(env)) { 1079 break; 1080 } 1081 /* fall through for segv */ 1082 case EXCP_PREFETCH_ABORT: 1083 case EXCP_DATA_ABORT: 1084 info.si_signo = TARGET_SIGSEGV; 1085 info.si_errno = 0; 1086 /* XXX: check env->error_code */ 1087 info.si_code = TARGET_SEGV_MAPERR; 1088 info._sifields._sigfault._addr = env->exception.vaddress; 1089 queue_signal(env, info.si_signo, &info); 1090 break; 1091 case EXCP_DEBUG: 1092 case EXCP_BKPT: 1093 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1094 if (sig) { 1095 info.si_signo = sig; 1096 info.si_errno = 0; 1097 info.si_code = TARGET_TRAP_BRKPT; 1098 queue_signal(env, info.si_signo, &info); 1099 } 1100 break; 1101 case EXCP_SEMIHOST: 1102 env->xregs[0] = do_arm_semihosting(env); 1103 break; 1104 case EXCP_YIELD: 1105 /* nothing to do here for user-mode, just resume guest code */ 1106 break; 1107 default: 1108 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1109 abort(); 1110 } 1111 process_pending_signals(env); 1112 /* Exception return on AArch64 always clears the exclusive monitor, 1113 * so any return to running guest code implies this. 1114 * A strex (successful or otherwise) also clears the monitor, so 1115 * we don't need to specialcase EXCP_STREX. 1116 */ 1117 env->exclusive_addr = -1; 1118 } 1119 } 1120 #endif /* ndef TARGET_ABI32 */ 1121 1122 #endif 1123 1124 #ifdef TARGET_UNICORE32 1125 1126 void cpu_loop(CPUUniCore32State *env) 1127 { 1128 CPUState *cs = CPU(uc32_env_get_cpu(env)); 1129 int trapnr; 1130 unsigned int n, insn; 1131 target_siginfo_t info; 1132 1133 for (;;) { 1134 cpu_exec_start(cs); 1135 trapnr = uc32_cpu_exec(cs); 1136 cpu_exec_end(cs); 1137 switch (trapnr) { 1138 case UC32_EXCP_PRIV: 1139 { 1140 /* system call */ 1141 get_user_u32(insn, env->regs[31] - 4); 1142 n = insn & 0xffffff; 1143 1144 if (n >= UC32_SYSCALL_BASE) { 1145 /* linux syscall */ 1146 n -= UC32_SYSCALL_BASE; 1147 if (n == UC32_SYSCALL_NR_set_tls) { 1148 cpu_set_tls(env, env->regs[0]); 1149 env->regs[0] = 0; 1150 } else { 1151 env->regs[0] = do_syscall(env, 1152 n, 1153 env->regs[0], 1154 env->regs[1], 1155 env->regs[2], 1156 env->regs[3], 1157 env->regs[4], 1158 env->regs[5], 1159 0, 0); 1160 } 1161 } else { 1162 goto error; 1163 } 1164 } 1165 break; 1166 case UC32_EXCP_DTRAP: 1167 case UC32_EXCP_ITRAP: 1168 info.si_signo = TARGET_SIGSEGV; 1169 info.si_errno = 0; 1170 /* XXX: check env->error_code */ 1171 info.si_code = TARGET_SEGV_MAPERR; 1172 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 1173 queue_signal(env, info.si_signo, &info); 1174 break; 1175 case EXCP_INTERRUPT: 1176 /* just indicate that signals should be handled asap */ 1177 break; 1178 case EXCP_DEBUG: 1179 { 1180 int sig; 1181 1182 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1183 if (sig) { 1184 info.si_signo = sig; 1185 info.si_errno = 0; 1186 info.si_code = TARGET_TRAP_BRKPT; 1187 queue_signal(env, info.si_signo, &info); 1188 } 1189 } 1190 break; 1191 default: 1192 goto error; 1193 } 1194 process_pending_signals(env); 1195 } 1196 1197 error: 1198 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1199 abort(); 1200 } 1201 #endif 1202 1203 #ifdef TARGET_SPARC 1204 #define SPARC64_STACK_BIAS 2047 1205 1206 //#define DEBUG_WIN 1207 1208 /* WARNING: dealing with register windows _is_ complicated. More info 1209 can be found at http://www.sics.se/~psm/sparcstack.html */ 1210 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 1211 { 1212 index = (index + cwp * 16) % (16 * env->nwindows); 1213 /* wrap handling : if cwp is on the last window, then we use the 1214 registers 'after' the end */ 1215 if (index < 8 && env->cwp == env->nwindows - 1) 1216 index += 16 * env->nwindows; 1217 return index; 1218 } 1219 1220 /* save the register window 'cwp1' */ 1221 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1222 { 1223 unsigned int i; 1224 abi_ulong sp_ptr; 1225 1226 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1227 #ifdef TARGET_SPARC64 1228 if (sp_ptr & 3) 1229 sp_ptr += SPARC64_STACK_BIAS; 1230 #endif 1231 #if defined(DEBUG_WIN) 1232 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1233 sp_ptr, cwp1); 1234 #endif 1235 for(i = 0; i < 16; i++) { 1236 /* FIXME - what to do if put_user() fails? */ 1237 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1238 sp_ptr += sizeof(abi_ulong); 1239 } 1240 } 1241 1242 static void save_window(CPUSPARCState *env) 1243 { 1244 #ifndef TARGET_SPARC64 1245 unsigned int new_wim; 1246 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1247 ((1LL << env->nwindows) - 1); 1248 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1249 env->wim = new_wim; 1250 #else 1251 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1252 env->cansave++; 1253 env->canrestore--; 1254 #endif 1255 } 1256 1257 static void restore_window(CPUSPARCState *env) 1258 { 1259 #ifndef TARGET_SPARC64 1260 unsigned int new_wim; 1261 #endif 1262 unsigned int i, cwp1; 1263 abi_ulong sp_ptr; 1264 1265 #ifndef TARGET_SPARC64 1266 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1267 ((1LL << env->nwindows) - 1); 1268 #endif 1269 1270 /* restore the invalid window */ 1271 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1272 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1273 #ifdef TARGET_SPARC64 1274 if (sp_ptr & 3) 1275 sp_ptr += SPARC64_STACK_BIAS; 1276 #endif 1277 #if defined(DEBUG_WIN) 1278 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1279 sp_ptr, cwp1); 1280 #endif 1281 for(i = 0; i < 16; i++) { 1282 /* FIXME - what to do if get_user() fails? */ 1283 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1284 sp_ptr += sizeof(abi_ulong); 1285 } 1286 #ifdef TARGET_SPARC64 1287 env->canrestore++; 1288 if (env->cleanwin < env->nwindows - 1) 1289 env->cleanwin++; 1290 env->cansave--; 1291 #else 1292 env->wim = new_wim; 1293 #endif 1294 } 1295 1296 static void flush_windows(CPUSPARCState *env) 1297 { 1298 int offset, cwp1; 1299 1300 offset = 1; 1301 for(;;) { 1302 /* if restore would invoke restore_window(), then we can stop */ 1303 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1304 #ifndef TARGET_SPARC64 1305 if (env->wim & (1 << cwp1)) 1306 break; 1307 #else 1308 if (env->canrestore == 0) 1309 break; 1310 env->cansave++; 1311 env->canrestore--; 1312 #endif 1313 save_window_offset(env, cwp1); 1314 offset++; 1315 } 1316 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1317 #ifndef TARGET_SPARC64 1318 /* set wim so that restore will reload the registers */ 1319 env->wim = 1 << cwp1; 1320 #endif 1321 #if defined(DEBUG_WIN) 1322 printf("flush_windows: nb=%d\n", offset - 1); 1323 #endif 1324 } 1325 1326 void cpu_loop (CPUSPARCState *env) 1327 { 1328 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1329 int trapnr; 1330 abi_long ret; 1331 target_siginfo_t info; 1332 1333 while (1) { 1334 cpu_exec_start(cs); 1335 trapnr = cpu_sparc_exec(cs); 1336 cpu_exec_end(cs); 1337 1338 /* Compute PSR before exposing state. */ 1339 if (env->cc_op != CC_OP_FLAGS) { 1340 cpu_get_psr(env); 1341 } 1342 1343 switch (trapnr) { 1344 #ifndef TARGET_SPARC64 1345 case 0x88: 1346 case 0x90: 1347 #else 1348 case 0x110: 1349 case 0x16d: 1350 #endif 1351 ret = do_syscall (env, env->gregs[1], 1352 env->regwptr[0], env->regwptr[1], 1353 env->regwptr[2], env->regwptr[3], 1354 env->regwptr[4], env->regwptr[5], 1355 0, 0); 1356 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1357 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1358 env->xcc |= PSR_CARRY; 1359 #else 1360 env->psr |= PSR_CARRY; 1361 #endif 1362 ret = -ret; 1363 } else { 1364 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1365 env->xcc &= ~PSR_CARRY; 1366 #else 1367 env->psr &= ~PSR_CARRY; 1368 #endif 1369 } 1370 env->regwptr[0] = ret; 1371 /* next instruction */ 1372 env->pc = env->npc; 1373 env->npc = env->npc + 4; 1374 break; 1375 case 0x83: /* flush windows */ 1376 #ifdef TARGET_ABI32 1377 case 0x103: 1378 #endif 1379 flush_windows(env); 1380 /* next instruction */ 1381 env->pc = env->npc; 1382 env->npc = env->npc + 4; 1383 break; 1384 #ifndef TARGET_SPARC64 1385 case TT_WIN_OVF: /* window overflow */ 1386 save_window(env); 1387 break; 1388 case TT_WIN_UNF: /* window underflow */ 1389 restore_window(env); 1390 break; 1391 case TT_TFAULT: 1392 case TT_DFAULT: 1393 { 1394 info.si_signo = TARGET_SIGSEGV; 1395 info.si_errno = 0; 1396 /* XXX: check env->error_code */ 1397 info.si_code = TARGET_SEGV_MAPERR; 1398 info._sifields._sigfault._addr = env->mmuregs[4]; 1399 queue_signal(env, info.si_signo, &info); 1400 } 1401 break; 1402 #else 1403 case TT_SPILL: /* window overflow */ 1404 save_window(env); 1405 break; 1406 case TT_FILL: /* window underflow */ 1407 restore_window(env); 1408 break; 1409 case TT_TFAULT: 1410 case TT_DFAULT: 1411 { 1412 info.si_signo = TARGET_SIGSEGV; 1413 info.si_errno = 0; 1414 /* XXX: check env->error_code */ 1415 info.si_code = TARGET_SEGV_MAPERR; 1416 if (trapnr == TT_DFAULT) 1417 info._sifields._sigfault._addr = env->dmmuregs[4]; 1418 else 1419 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1420 queue_signal(env, info.si_signo, &info); 1421 } 1422 break; 1423 #ifndef TARGET_ABI32 1424 case 0x16e: 1425 flush_windows(env); 1426 sparc64_get_context(env); 1427 break; 1428 case 0x16f: 1429 flush_windows(env); 1430 sparc64_set_context(env); 1431 break; 1432 #endif 1433 #endif 1434 case EXCP_INTERRUPT: 1435 /* just indicate that signals should be handled asap */ 1436 break; 1437 case TT_ILL_INSN: 1438 { 1439 info.si_signo = TARGET_SIGILL; 1440 info.si_errno = 0; 1441 info.si_code = TARGET_ILL_ILLOPC; 1442 info._sifields._sigfault._addr = env->pc; 1443 queue_signal(env, info.si_signo, &info); 1444 } 1445 break; 1446 case EXCP_DEBUG: 1447 { 1448 int sig; 1449 1450 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1451 if (sig) 1452 { 1453 info.si_signo = sig; 1454 info.si_errno = 0; 1455 info.si_code = TARGET_TRAP_BRKPT; 1456 queue_signal(env, info.si_signo, &info); 1457 } 1458 } 1459 break; 1460 default: 1461 printf ("Unhandled trap: 0x%x\n", trapnr); 1462 cpu_dump_state(cs, stderr, fprintf, 0); 1463 exit(EXIT_FAILURE); 1464 } 1465 process_pending_signals (env); 1466 } 1467 } 1468 1469 #endif 1470 1471 #ifdef TARGET_PPC 1472 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1473 { 1474 return cpu_get_host_ticks(); 1475 } 1476 1477 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1478 { 1479 return cpu_ppc_get_tb(env); 1480 } 1481 1482 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1483 { 1484 return cpu_ppc_get_tb(env) >> 32; 1485 } 1486 1487 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1488 { 1489 return cpu_ppc_get_tb(env); 1490 } 1491 1492 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1493 { 1494 return cpu_ppc_get_tb(env) >> 32; 1495 } 1496 1497 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1498 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1499 1500 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1501 { 1502 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1503 } 1504 1505 /* XXX: to be fixed */ 1506 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1507 { 1508 return -1; 1509 } 1510 1511 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1512 { 1513 return -1; 1514 } 1515 1516 static int do_store_exclusive(CPUPPCState *env) 1517 { 1518 target_ulong addr; 1519 target_ulong page_addr; 1520 target_ulong val, val2 __attribute__((unused)) = 0; 1521 int flags; 1522 int segv = 0; 1523 1524 addr = env->reserve_ea; 1525 page_addr = addr & TARGET_PAGE_MASK; 1526 start_exclusive(); 1527 mmap_lock(); 1528 flags = page_get_flags(page_addr); 1529 if ((flags & PAGE_READ) == 0) { 1530 segv = 1; 1531 } else { 1532 int reg = env->reserve_info & 0x1f; 1533 int size = env->reserve_info >> 5; 1534 int stored = 0; 1535 1536 if (addr == env->reserve_addr) { 1537 switch (size) { 1538 case 1: segv = get_user_u8(val, addr); break; 1539 case 2: segv = get_user_u16(val, addr); break; 1540 case 4: segv = get_user_u32(val, addr); break; 1541 #if defined(TARGET_PPC64) 1542 case 8: segv = get_user_u64(val, addr); break; 1543 case 16: { 1544 segv = get_user_u64(val, addr); 1545 if (!segv) { 1546 segv = get_user_u64(val2, addr + 8); 1547 } 1548 break; 1549 } 1550 #endif 1551 default: abort(); 1552 } 1553 if (!segv && val == env->reserve_val) { 1554 val = env->gpr[reg]; 1555 switch (size) { 1556 case 1: segv = put_user_u8(val, addr); break; 1557 case 2: segv = put_user_u16(val, addr); break; 1558 case 4: segv = put_user_u32(val, addr); break; 1559 #if defined(TARGET_PPC64) 1560 case 8: segv = put_user_u64(val, addr); break; 1561 case 16: { 1562 if (val2 == env->reserve_val2) { 1563 if (msr_le) { 1564 val2 = val; 1565 val = env->gpr[reg+1]; 1566 } else { 1567 val2 = env->gpr[reg+1]; 1568 } 1569 segv = put_user_u64(val, addr); 1570 if (!segv) { 1571 segv = put_user_u64(val2, addr + 8); 1572 } 1573 } 1574 break; 1575 } 1576 #endif 1577 default: abort(); 1578 } 1579 if (!segv) { 1580 stored = 1; 1581 } 1582 } 1583 } 1584 env->crf[0] = (stored << 1) | xer_so; 1585 env->reserve_addr = (target_ulong)-1; 1586 } 1587 if (!segv) { 1588 env->nip += 4; 1589 } 1590 mmap_unlock(); 1591 end_exclusive(); 1592 return segv; 1593 } 1594 1595 void cpu_loop(CPUPPCState *env) 1596 { 1597 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1598 target_siginfo_t info; 1599 int trapnr; 1600 target_ulong ret; 1601 1602 for(;;) { 1603 cpu_exec_start(cs); 1604 trapnr = cpu_ppc_exec(cs); 1605 cpu_exec_end(cs); 1606 switch(trapnr) { 1607 case POWERPC_EXCP_NONE: 1608 /* Just go on */ 1609 break; 1610 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1611 cpu_abort(cs, "Critical interrupt while in user mode. " 1612 "Aborting\n"); 1613 break; 1614 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1615 cpu_abort(cs, "Machine check exception while in user mode. " 1616 "Aborting\n"); 1617 break; 1618 case POWERPC_EXCP_DSI: /* Data storage exception */ 1619 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", 1620 env->spr[SPR_DAR]); 1621 /* XXX: check this. Seems bugged */ 1622 switch (env->error_code & 0xFF000000) { 1623 case 0x40000000: 1624 info.si_signo = TARGET_SIGSEGV; 1625 info.si_errno = 0; 1626 info.si_code = TARGET_SEGV_MAPERR; 1627 break; 1628 case 0x04000000: 1629 info.si_signo = TARGET_SIGILL; 1630 info.si_errno = 0; 1631 info.si_code = TARGET_ILL_ILLADR; 1632 break; 1633 case 0x08000000: 1634 info.si_signo = TARGET_SIGSEGV; 1635 info.si_errno = 0; 1636 info.si_code = TARGET_SEGV_ACCERR; 1637 break; 1638 default: 1639 /* Let's send a regular segfault... */ 1640 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1641 env->error_code); 1642 info.si_signo = TARGET_SIGSEGV; 1643 info.si_errno = 0; 1644 info.si_code = TARGET_SEGV_MAPERR; 1645 break; 1646 } 1647 info._sifields._sigfault._addr = env->nip; 1648 queue_signal(env, info.si_signo, &info); 1649 break; 1650 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1651 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx 1652 "\n", env->spr[SPR_SRR0]); 1653 /* XXX: check this */ 1654 switch (env->error_code & 0xFF000000) { 1655 case 0x40000000: 1656 info.si_signo = TARGET_SIGSEGV; 1657 info.si_errno = 0; 1658 info.si_code = TARGET_SEGV_MAPERR; 1659 break; 1660 case 0x10000000: 1661 case 0x08000000: 1662 info.si_signo = TARGET_SIGSEGV; 1663 info.si_errno = 0; 1664 info.si_code = TARGET_SEGV_ACCERR; 1665 break; 1666 default: 1667 /* Let's send a regular segfault... */ 1668 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1669 env->error_code); 1670 info.si_signo = TARGET_SIGSEGV; 1671 info.si_errno = 0; 1672 info.si_code = TARGET_SEGV_MAPERR; 1673 break; 1674 } 1675 info._sifields._sigfault._addr = env->nip - 4; 1676 queue_signal(env, info.si_signo, &info); 1677 break; 1678 case POWERPC_EXCP_EXTERNAL: /* External input */ 1679 cpu_abort(cs, "External interrupt while in user mode. " 1680 "Aborting\n"); 1681 break; 1682 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1683 EXCP_DUMP(env, "Unaligned memory access\n"); 1684 /* XXX: check this */ 1685 info.si_signo = TARGET_SIGBUS; 1686 info.si_errno = 0; 1687 info.si_code = TARGET_BUS_ADRALN; 1688 info._sifields._sigfault._addr = env->nip; 1689 queue_signal(env, info.si_signo, &info); 1690 break; 1691 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1692 /* XXX: check this */ 1693 switch (env->error_code & ~0xF) { 1694 case POWERPC_EXCP_FP: 1695 EXCP_DUMP(env, "Floating point program exception\n"); 1696 info.si_signo = TARGET_SIGFPE; 1697 info.si_errno = 0; 1698 switch (env->error_code & 0xF) { 1699 case POWERPC_EXCP_FP_OX: 1700 info.si_code = TARGET_FPE_FLTOVF; 1701 break; 1702 case POWERPC_EXCP_FP_UX: 1703 info.si_code = TARGET_FPE_FLTUND; 1704 break; 1705 case POWERPC_EXCP_FP_ZX: 1706 case POWERPC_EXCP_FP_VXZDZ: 1707 info.si_code = TARGET_FPE_FLTDIV; 1708 break; 1709 case POWERPC_EXCP_FP_XX: 1710 info.si_code = TARGET_FPE_FLTRES; 1711 break; 1712 case POWERPC_EXCP_FP_VXSOFT: 1713 info.si_code = TARGET_FPE_FLTINV; 1714 break; 1715 case POWERPC_EXCP_FP_VXSNAN: 1716 case POWERPC_EXCP_FP_VXISI: 1717 case POWERPC_EXCP_FP_VXIDI: 1718 case POWERPC_EXCP_FP_VXIMZ: 1719 case POWERPC_EXCP_FP_VXVC: 1720 case POWERPC_EXCP_FP_VXSQRT: 1721 case POWERPC_EXCP_FP_VXCVI: 1722 info.si_code = TARGET_FPE_FLTSUB; 1723 break; 1724 default: 1725 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1726 env->error_code); 1727 break; 1728 } 1729 break; 1730 case POWERPC_EXCP_INVAL: 1731 EXCP_DUMP(env, "Invalid instruction\n"); 1732 info.si_signo = TARGET_SIGILL; 1733 info.si_errno = 0; 1734 switch (env->error_code & 0xF) { 1735 case POWERPC_EXCP_INVAL_INVAL: 1736 info.si_code = TARGET_ILL_ILLOPC; 1737 break; 1738 case POWERPC_EXCP_INVAL_LSWX: 1739 info.si_code = TARGET_ILL_ILLOPN; 1740 break; 1741 case POWERPC_EXCP_INVAL_SPR: 1742 info.si_code = TARGET_ILL_PRVREG; 1743 break; 1744 case POWERPC_EXCP_INVAL_FP: 1745 info.si_code = TARGET_ILL_COPROC; 1746 break; 1747 default: 1748 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1749 env->error_code & 0xF); 1750 info.si_code = TARGET_ILL_ILLADR; 1751 break; 1752 } 1753 break; 1754 case POWERPC_EXCP_PRIV: 1755 EXCP_DUMP(env, "Privilege violation\n"); 1756 info.si_signo = TARGET_SIGILL; 1757 info.si_errno = 0; 1758 switch (env->error_code & 0xF) { 1759 case POWERPC_EXCP_PRIV_OPC: 1760 info.si_code = TARGET_ILL_PRVOPC; 1761 break; 1762 case POWERPC_EXCP_PRIV_REG: 1763 info.si_code = TARGET_ILL_PRVREG; 1764 break; 1765 default: 1766 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1767 env->error_code & 0xF); 1768 info.si_code = TARGET_ILL_PRVOPC; 1769 break; 1770 } 1771 break; 1772 case POWERPC_EXCP_TRAP: 1773 cpu_abort(cs, "Tried to call a TRAP\n"); 1774 break; 1775 default: 1776 /* Should not happen ! */ 1777 cpu_abort(cs, "Unknown program exception (%02x)\n", 1778 env->error_code); 1779 break; 1780 } 1781 info._sifields._sigfault._addr = env->nip - 4; 1782 queue_signal(env, info.si_signo, &info); 1783 break; 1784 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1785 EXCP_DUMP(env, "No floating point allowed\n"); 1786 info.si_signo = TARGET_SIGILL; 1787 info.si_errno = 0; 1788 info.si_code = TARGET_ILL_COPROC; 1789 info._sifields._sigfault._addr = env->nip - 4; 1790 queue_signal(env, info.si_signo, &info); 1791 break; 1792 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1793 cpu_abort(cs, "Syscall exception while in user mode. " 1794 "Aborting\n"); 1795 break; 1796 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1797 EXCP_DUMP(env, "No APU instruction allowed\n"); 1798 info.si_signo = TARGET_SIGILL; 1799 info.si_errno = 0; 1800 info.si_code = TARGET_ILL_COPROC; 1801 info._sifields._sigfault._addr = env->nip - 4; 1802 queue_signal(env, info.si_signo, &info); 1803 break; 1804 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1805 cpu_abort(cs, "Decrementer interrupt while in user mode. " 1806 "Aborting\n"); 1807 break; 1808 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1809 cpu_abort(cs, "Fix interval timer interrupt while in user mode. " 1810 "Aborting\n"); 1811 break; 1812 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1813 cpu_abort(cs, "Watchdog timer interrupt while in user mode. " 1814 "Aborting\n"); 1815 break; 1816 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1817 cpu_abort(cs, "Data TLB exception while in user mode. " 1818 "Aborting\n"); 1819 break; 1820 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1821 cpu_abort(cs, "Instruction TLB exception while in user mode. " 1822 "Aborting\n"); 1823 break; 1824 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1825 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1826 info.si_signo = TARGET_SIGILL; 1827 info.si_errno = 0; 1828 info.si_code = TARGET_ILL_COPROC; 1829 info._sifields._sigfault._addr = env->nip - 4; 1830 queue_signal(env, info.si_signo, &info); 1831 break; 1832 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1833 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); 1834 break; 1835 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1836 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); 1837 break; 1838 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1839 cpu_abort(cs, "Performance monitor exception not handled\n"); 1840 break; 1841 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1842 cpu_abort(cs, "Doorbell interrupt while in user mode. " 1843 "Aborting\n"); 1844 break; 1845 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1846 cpu_abort(cs, "Doorbell critical interrupt while in user mode. " 1847 "Aborting\n"); 1848 break; 1849 case POWERPC_EXCP_RESET: /* System reset exception */ 1850 cpu_abort(cs, "Reset interrupt while in user mode. " 1851 "Aborting\n"); 1852 break; 1853 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1854 cpu_abort(cs, "Data segment exception while in user mode. " 1855 "Aborting\n"); 1856 break; 1857 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1858 cpu_abort(cs, "Instruction segment exception " 1859 "while in user mode. Aborting\n"); 1860 break; 1861 /* PowerPC 64 with hypervisor mode support */ 1862 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1863 cpu_abort(cs, "Hypervisor decrementer interrupt " 1864 "while in user mode. Aborting\n"); 1865 break; 1866 case POWERPC_EXCP_TRACE: /* Trace exception */ 1867 /* Nothing to do: 1868 * we use this exception to emulate step-by-step execution mode. 1869 */ 1870 break; 1871 /* PowerPC 64 with hypervisor mode support */ 1872 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1873 cpu_abort(cs, "Hypervisor data storage exception " 1874 "while in user mode. Aborting\n"); 1875 break; 1876 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1877 cpu_abort(cs, "Hypervisor instruction storage exception " 1878 "while in user mode. Aborting\n"); 1879 break; 1880 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1881 cpu_abort(cs, "Hypervisor data segment exception " 1882 "while in user mode. Aborting\n"); 1883 break; 1884 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1885 cpu_abort(cs, "Hypervisor instruction segment exception " 1886 "while in user mode. Aborting\n"); 1887 break; 1888 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1889 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1890 info.si_signo = TARGET_SIGILL; 1891 info.si_errno = 0; 1892 info.si_code = TARGET_ILL_COPROC; 1893 info._sifields._sigfault._addr = env->nip - 4; 1894 queue_signal(env, info.si_signo, &info); 1895 break; 1896 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1897 cpu_abort(cs, "Programmable interval timer interrupt " 1898 "while in user mode. Aborting\n"); 1899 break; 1900 case POWERPC_EXCP_IO: /* IO error exception */ 1901 cpu_abort(cs, "IO error exception while in user mode. " 1902 "Aborting\n"); 1903 break; 1904 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1905 cpu_abort(cs, "Run mode exception while in user mode. " 1906 "Aborting\n"); 1907 break; 1908 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1909 cpu_abort(cs, "Emulation trap exception not handled\n"); 1910 break; 1911 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1912 cpu_abort(cs, "Instruction fetch TLB exception " 1913 "while in user-mode. Aborting"); 1914 break; 1915 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1916 cpu_abort(cs, "Data load TLB exception while in user-mode. " 1917 "Aborting"); 1918 break; 1919 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1920 cpu_abort(cs, "Data store TLB exception while in user-mode. " 1921 "Aborting"); 1922 break; 1923 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1924 cpu_abort(cs, "Floating-point assist exception not handled\n"); 1925 break; 1926 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1927 cpu_abort(cs, "Instruction address breakpoint exception " 1928 "not handled\n"); 1929 break; 1930 case POWERPC_EXCP_SMI: /* System management interrupt */ 1931 cpu_abort(cs, "System management interrupt while in user mode. " 1932 "Aborting\n"); 1933 break; 1934 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1935 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " 1936 "Aborting\n"); 1937 break; 1938 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1939 cpu_abort(cs, "Performance monitor exception not handled\n"); 1940 break; 1941 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1942 cpu_abort(cs, "Vector assist exception not handled\n"); 1943 break; 1944 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1945 cpu_abort(cs, "Soft patch exception not handled\n"); 1946 break; 1947 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1948 cpu_abort(cs, "Maintenance exception while in user mode. " 1949 "Aborting\n"); 1950 break; 1951 case POWERPC_EXCP_STOP: /* stop translation */ 1952 /* We did invalidate the instruction cache. Go on */ 1953 break; 1954 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1955 /* We just stopped because of a branch. Go on */ 1956 break; 1957 case POWERPC_EXCP_SYSCALL_USER: 1958 /* system call in user-mode emulation */ 1959 /* WARNING: 1960 * PPC ABI uses overflow flag in cr0 to signal an error 1961 * in syscalls. 1962 */ 1963 env->crf[0] &= ~0x1; 1964 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1965 env->gpr[5], env->gpr[6], env->gpr[7], 1966 env->gpr[8], 0, 0); 1967 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1968 /* Returning from a successful sigreturn syscall. 1969 Avoid corrupting register state. */ 1970 break; 1971 } 1972 if (ret > (target_ulong)(-515)) { 1973 env->crf[0] |= 0x1; 1974 ret = -ret; 1975 } 1976 env->gpr[3] = ret; 1977 break; 1978 case POWERPC_EXCP_STCX: 1979 if (do_store_exclusive(env)) { 1980 info.si_signo = TARGET_SIGSEGV; 1981 info.si_errno = 0; 1982 info.si_code = TARGET_SEGV_MAPERR; 1983 info._sifields._sigfault._addr = env->nip; 1984 queue_signal(env, info.si_signo, &info); 1985 } 1986 break; 1987 case EXCP_DEBUG: 1988 { 1989 int sig; 1990 1991 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1992 if (sig) { 1993 info.si_signo = sig; 1994 info.si_errno = 0; 1995 info.si_code = TARGET_TRAP_BRKPT; 1996 queue_signal(env, info.si_signo, &info); 1997 } 1998 } 1999 break; 2000 case EXCP_INTERRUPT: 2001 /* just indicate that signals should be handled asap */ 2002 break; 2003 default: 2004 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr); 2005 break; 2006 } 2007 process_pending_signals(env); 2008 } 2009 } 2010 #endif 2011 2012 #ifdef TARGET_MIPS 2013 2014 # ifdef TARGET_ABI_MIPSO32 2015 # define MIPS_SYS(name, args) args, 2016 static const uint8_t mips_syscall_args[] = { 2017 MIPS_SYS(sys_syscall , 8) /* 4000 */ 2018 MIPS_SYS(sys_exit , 1) 2019 MIPS_SYS(sys_fork , 0) 2020 MIPS_SYS(sys_read , 3) 2021 MIPS_SYS(sys_write , 3) 2022 MIPS_SYS(sys_open , 3) /* 4005 */ 2023 MIPS_SYS(sys_close , 1) 2024 MIPS_SYS(sys_waitpid , 3) 2025 MIPS_SYS(sys_creat , 2) 2026 MIPS_SYS(sys_link , 2) 2027 MIPS_SYS(sys_unlink , 1) /* 4010 */ 2028 MIPS_SYS(sys_execve , 0) 2029 MIPS_SYS(sys_chdir , 1) 2030 MIPS_SYS(sys_time , 1) 2031 MIPS_SYS(sys_mknod , 3) 2032 MIPS_SYS(sys_chmod , 2) /* 4015 */ 2033 MIPS_SYS(sys_lchown , 3) 2034 MIPS_SYS(sys_ni_syscall , 0) 2035 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 2036 MIPS_SYS(sys_lseek , 3) 2037 MIPS_SYS(sys_getpid , 0) /* 4020 */ 2038 MIPS_SYS(sys_mount , 5) 2039 MIPS_SYS(sys_umount , 1) 2040 MIPS_SYS(sys_setuid , 1) 2041 MIPS_SYS(sys_getuid , 0) 2042 MIPS_SYS(sys_stime , 1) /* 4025 */ 2043 MIPS_SYS(sys_ptrace , 4) 2044 MIPS_SYS(sys_alarm , 1) 2045 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 2046 MIPS_SYS(sys_pause , 0) 2047 MIPS_SYS(sys_utime , 2) /* 4030 */ 2048 MIPS_SYS(sys_ni_syscall , 0) 2049 MIPS_SYS(sys_ni_syscall , 0) 2050 MIPS_SYS(sys_access , 2) 2051 MIPS_SYS(sys_nice , 1) 2052 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 2053 MIPS_SYS(sys_sync , 0) 2054 MIPS_SYS(sys_kill , 2) 2055 MIPS_SYS(sys_rename , 2) 2056 MIPS_SYS(sys_mkdir , 2) 2057 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 2058 MIPS_SYS(sys_dup , 1) 2059 MIPS_SYS(sys_pipe , 0) 2060 MIPS_SYS(sys_times , 1) 2061 MIPS_SYS(sys_ni_syscall , 0) 2062 MIPS_SYS(sys_brk , 1) /* 4045 */ 2063 MIPS_SYS(sys_setgid , 1) 2064 MIPS_SYS(sys_getgid , 0) 2065 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 2066 MIPS_SYS(sys_geteuid , 0) 2067 MIPS_SYS(sys_getegid , 0) /* 4050 */ 2068 MIPS_SYS(sys_acct , 0) 2069 MIPS_SYS(sys_umount2 , 2) 2070 MIPS_SYS(sys_ni_syscall , 0) 2071 MIPS_SYS(sys_ioctl , 3) 2072 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 2073 MIPS_SYS(sys_ni_syscall , 2) 2074 MIPS_SYS(sys_setpgid , 2) 2075 MIPS_SYS(sys_ni_syscall , 0) 2076 MIPS_SYS(sys_olduname , 1) 2077 MIPS_SYS(sys_umask , 1) /* 4060 */ 2078 MIPS_SYS(sys_chroot , 1) 2079 MIPS_SYS(sys_ustat , 2) 2080 MIPS_SYS(sys_dup2 , 2) 2081 MIPS_SYS(sys_getppid , 0) 2082 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 2083 MIPS_SYS(sys_setsid , 0) 2084 MIPS_SYS(sys_sigaction , 3) 2085 MIPS_SYS(sys_sgetmask , 0) 2086 MIPS_SYS(sys_ssetmask , 1) 2087 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 2088 MIPS_SYS(sys_setregid , 2) 2089 MIPS_SYS(sys_sigsuspend , 0) 2090 MIPS_SYS(sys_sigpending , 1) 2091 MIPS_SYS(sys_sethostname , 2) 2092 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 2093 MIPS_SYS(sys_getrlimit , 2) 2094 MIPS_SYS(sys_getrusage , 2) 2095 MIPS_SYS(sys_gettimeofday, 2) 2096 MIPS_SYS(sys_settimeofday, 2) 2097 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 2098 MIPS_SYS(sys_setgroups , 2) 2099 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 2100 MIPS_SYS(sys_symlink , 2) 2101 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 2102 MIPS_SYS(sys_readlink , 3) /* 4085 */ 2103 MIPS_SYS(sys_uselib , 1) 2104 MIPS_SYS(sys_swapon , 2) 2105 MIPS_SYS(sys_reboot , 3) 2106 MIPS_SYS(old_readdir , 3) 2107 MIPS_SYS(old_mmap , 6) /* 4090 */ 2108 MIPS_SYS(sys_munmap , 2) 2109 MIPS_SYS(sys_truncate , 2) 2110 MIPS_SYS(sys_ftruncate , 2) 2111 MIPS_SYS(sys_fchmod , 2) 2112 MIPS_SYS(sys_fchown , 3) /* 4095 */ 2113 MIPS_SYS(sys_getpriority , 2) 2114 MIPS_SYS(sys_setpriority , 3) 2115 MIPS_SYS(sys_ni_syscall , 0) 2116 MIPS_SYS(sys_statfs , 2) 2117 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 2118 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 2119 MIPS_SYS(sys_socketcall , 2) 2120 MIPS_SYS(sys_syslog , 3) 2121 MIPS_SYS(sys_setitimer , 3) 2122 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 2123 MIPS_SYS(sys_newstat , 2) 2124 MIPS_SYS(sys_newlstat , 2) 2125 MIPS_SYS(sys_newfstat , 2) 2126 MIPS_SYS(sys_uname , 1) 2127 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 2128 MIPS_SYS(sys_vhangup , 0) 2129 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 2130 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 2131 MIPS_SYS(sys_wait4 , 4) 2132 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 2133 MIPS_SYS(sys_sysinfo , 1) 2134 MIPS_SYS(sys_ipc , 6) 2135 MIPS_SYS(sys_fsync , 1) 2136 MIPS_SYS(sys_sigreturn , 0) 2137 MIPS_SYS(sys_clone , 6) /* 4120 */ 2138 MIPS_SYS(sys_setdomainname, 2) 2139 MIPS_SYS(sys_newuname , 1) 2140 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 2141 MIPS_SYS(sys_adjtimex , 1) 2142 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 2143 MIPS_SYS(sys_sigprocmask , 3) 2144 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 2145 MIPS_SYS(sys_init_module , 5) 2146 MIPS_SYS(sys_delete_module, 1) 2147 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 2148 MIPS_SYS(sys_quotactl , 0) 2149 MIPS_SYS(sys_getpgid , 1) 2150 MIPS_SYS(sys_fchdir , 1) 2151 MIPS_SYS(sys_bdflush , 2) 2152 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 2153 MIPS_SYS(sys_personality , 1) 2154 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 2155 MIPS_SYS(sys_setfsuid , 1) 2156 MIPS_SYS(sys_setfsgid , 1) 2157 MIPS_SYS(sys_llseek , 5) /* 4140 */ 2158 MIPS_SYS(sys_getdents , 3) 2159 MIPS_SYS(sys_select , 5) 2160 MIPS_SYS(sys_flock , 2) 2161 MIPS_SYS(sys_msync , 3) 2162 MIPS_SYS(sys_readv , 3) /* 4145 */ 2163 MIPS_SYS(sys_writev , 3) 2164 MIPS_SYS(sys_cacheflush , 3) 2165 MIPS_SYS(sys_cachectl , 3) 2166 MIPS_SYS(sys_sysmips , 4) 2167 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 2168 MIPS_SYS(sys_getsid , 1) 2169 MIPS_SYS(sys_fdatasync , 0) 2170 MIPS_SYS(sys_sysctl , 1) 2171 MIPS_SYS(sys_mlock , 2) 2172 MIPS_SYS(sys_munlock , 2) /* 4155 */ 2173 MIPS_SYS(sys_mlockall , 1) 2174 MIPS_SYS(sys_munlockall , 0) 2175 MIPS_SYS(sys_sched_setparam, 2) 2176 MIPS_SYS(sys_sched_getparam, 2) 2177 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 2178 MIPS_SYS(sys_sched_getscheduler, 1) 2179 MIPS_SYS(sys_sched_yield , 0) 2180 MIPS_SYS(sys_sched_get_priority_max, 1) 2181 MIPS_SYS(sys_sched_get_priority_min, 1) 2182 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 2183 MIPS_SYS(sys_nanosleep, 2) 2184 MIPS_SYS(sys_mremap , 5) 2185 MIPS_SYS(sys_accept , 3) 2186 MIPS_SYS(sys_bind , 3) 2187 MIPS_SYS(sys_connect , 3) /* 4170 */ 2188 MIPS_SYS(sys_getpeername , 3) 2189 MIPS_SYS(sys_getsockname , 3) 2190 MIPS_SYS(sys_getsockopt , 5) 2191 MIPS_SYS(sys_listen , 2) 2192 MIPS_SYS(sys_recv , 4) /* 4175 */ 2193 MIPS_SYS(sys_recvfrom , 6) 2194 MIPS_SYS(sys_recvmsg , 3) 2195 MIPS_SYS(sys_send , 4) 2196 MIPS_SYS(sys_sendmsg , 3) 2197 MIPS_SYS(sys_sendto , 6) /* 4180 */ 2198 MIPS_SYS(sys_setsockopt , 5) 2199 MIPS_SYS(sys_shutdown , 2) 2200 MIPS_SYS(sys_socket , 3) 2201 MIPS_SYS(sys_socketpair , 4) 2202 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 2203 MIPS_SYS(sys_getresuid , 3) 2204 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 2205 MIPS_SYS(sys_poll , 3) 2206 MIPS_SYS(sys_nfsservctl , 3) 2207 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 2208 MIPS_SYS(sys_getresgid , 3) 2209 MIPS_SYS(sys_prctl , 5) 2210 MIPS_SYS(sys_rt_sigreturn, 0) 2211 MIPS_SYS(sys_rt_sigaction, 4) 2212 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 2213 MIPS_SYS(sys_rt_sigpending, 2) 2214 MIPS_SYS(sys_rt_sigtimedwait, 4) 2215 MIPS_SYS(sys_rt_sigqueueinfo, 3) 2216 MIPS_SYS(sys_rt_sigsuspend, 0) 2217 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 2218 MIPS_SYS(sys_pwrite64 , 6) 2219 MIPS_SYS(sys_chown , 3) 2220 MIPS_SYS(sys_getcwd , 2) 2221 MIPS_SYS(sys_capget , 2) 2222 MIPS_SYS(sys_capset , 2) /* 4205 */ 2223 MIPS_SYS(sys_sigaltstack , 2) 2224 MIPS_SYS(sys_sendfile , 4) 2225 MIPS_SYS(sys_ni_syscall , 0) 2226 MIPS_SYS(sys_ni_syscall , 0) 2227 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2228 MIPS_SYS(sys_truncate64 , 4) 2229 MIPS_SYS(sys_ftruncate64 , 4) 2230 MIPS_SYS(sys_stat64 , 2) 2231 MIPS_SYS(sys_lstat64 , 2) 2232 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2233 MIPS_SYS(sys_pivot_root , 2) 2234 MIPS_SYS(sys_mincore , 3) 2235 MIPS_SYS(sys_madvise , 3) 2236 MIPS_SYS(sys_getdents64 , 3) 2237 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2238 MIPS_SYS(sys_ni_syscall , 0) 2239 MIPS_SYS(sys_gettid , 0) 2240 MIPS_SYS(sys_readahead , 5) 2241 MIPS_SYS(sys_setxattr , 5) 2242 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2243 MIPS_SYS(sys_fsetxattr , 5) 2244 MIPS_SYS(sys_getxattr , 4) 2245 MIPS_SYS(sys_lgetxattr , 4) 2246 MIPS_SYS(sys_fgetxattr , 4) 2247 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2248 MIPS_SYS(sys_llistxattr , 3) 2249 MIPS_SYS(sys_flistxattr , 3) 2250 MIPS_SYS(sys_removexattr , 2) 2251 MIPS_SYS(sys_lremovexattr, 2) 2252 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2253 MIPS_SYS(sys_tkill , 2) 2254 MIPS_SYS(sys_sendfile64 , 5) 2255 MIPS_SYS(sys_futex , 6) 2256 MIPS_SYS(sys_sched_setaffinity, 3) 2257 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2258 MIPS_SYS(sys_io_setup , 2) 2259 MIPS_SYS(sys_io_destroy , 1) 2260 MIPS_SYS(sys_io_getevents, 5) 2261 MIPS_SYS(sys_io_submit , 3) 2262 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2263 MIPS_SYS(sys_exit_group , 1) 2264 MIPS_SYS(sys_lookup_dcookie, 3) 2265 MIPS_SYS(sys_epoll_create, 1) 2266 MIPS_SYS(sys_epoll_ctl , 4) 2267 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2268 MIPS_SYS(sys_remap_file_pages, 5) 2269 MIPS_SYS(sys_set_tid_address, 1) 2270 MIPS_SYS(sys_restart_syscall, 0) 2271 MIPS_SYS(sys_fadvise64_64, 7) 2272 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2273 MIPS_SYS(sys_fstatfs64 , 2) 2274 MIPS_SYS(sys_timer_create, 3) 2275 MIPS_SYS(sys_timer_settime, 4) 2276 MIPS_SYS(sys_timer_gettime, 2) 2277 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2278 MIPS_SYS(sys_timer_delete, 1) 2279 MIPS_SYS(sys_clock_settime, 2) 2280 MIPS_SYS(sys_clock_gettime, 2) 2281 MIPS_SYS(sys_clock_getres, 2) 2282 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2283 MIPS_SYS(sys_tgkill , 3) 2284 MIPS_SYS(sys_utimes , 2) 2285 MIPS_SYS(sys_mbind , 4) 2286 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2287 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2288 MIPS_SYS(sys_mq_open , 4) 2289 MIPS_SYS(sys_mq_unlink , 1) 2290 MIPS_SYS(sys_mq_timedsend, 5) 2291 MIPS_SYS(sys_mq_timedreceive, 5) 2292 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2293 MIPS_SYS(sys_mq_getsetattr, 3) 2294 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2295 MIPS_SYS(sys_waitid , 4) 2296 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2297 MIPS_SYS(sys_add_key , 5) 2298 MIPS_SYS(sys_request_key, 4) 2299 MIPS_SYS(sys_keyctl , 5) 2300 MIPS_SYS(sys_set_thread_area, 1) 2301 MIPS_SYS(sys_inotify_init, 0) 2302 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2303 MIPS_SYS(sys_inotify_rm_watch, 2) 2304 MIPS_SYS(sys_migrate_pages, 4) 2305 MIPS_SYS(sys_openat, 4) 2306 MIPS_SYS(sys_mkdirat, 3) 2307 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2308 MIPS_SYS(sys_fchownat, 5) 2309 MIPS_SYS(sys_futimesat, 3) 2310 MIPS_SYS(sys_fstatat64, 4) 2311 MIPS_SYS(sys_unlinkat, 3) 2312 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2313 MIPS_SYS(sys_linkat, 5) 2314 MIPS_SYS(sys_symlinkat, 3) 2315 MIPS_SYS(sys_readlinkat, 4) 2316 MIPS_SYS(sys_fchmodat, 3) 2317 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2318 MIPS_SYS(sys_pselect6, 6) 2319 MIPS_SYS(sys_ppoll, 5) 2320 MIPS_SYS(sys_unshare, 1) 2321 MIPS_SYS(sys_splice, 6) 2322 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2323 MIPS_SYS(sys_tee, 4) 2324 MIPS_SYS(sys_vmsplice, 4) 2325 MIPS_SYS(sys_move_pages, 6) 2326 MIPS_SYS(sys_set_robust_list, 2) 2327 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2328 MIPS_SYS(sys_kexec_load, 4) 2329 MIPS_SYS(sys_getcpu, 3) 2330 MIPS_SYS(sys_epoll_pwait, 6) 2331 MIPS_SYS(sys_ioprio_set, 3) 2332 MIPS_SYS(sys_ioprio_get, 2) 2333 MIPS_SYS(sys_utimensat, 4) 2334 MIPS_SYS(sys_signalfd, 3) 2335 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2336 MIPS_SYS(sys_eventfd, 1) 2337 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2338 MIPS_SYS(sys_timerfd_create, 2) 2339 MIPS_SYS(sys_timerfd_gettime, 2) 2340 MIPS_SYS(sys_timerfd_settime, 4) 2341 MIPS_SYS(sys_signalfd4, 4) 2342 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2343 MIPS_SYS(sys_epoll_create1, 1) 2344 MIPS_SYS(sys_dup3, 3) 2345 MIPS_SYS(sys_pipe2, 2) 2346 MIPS_SYS(sys_inotify_init1, 1) 2347 MIPS_SYS(sys_preadv, 6) /* 4330 */ 2348 MIPS_SYS(sys_pwritev, 6) 2349 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2350 MIPS_SYS(sys_perf_event_open, 5) 2351 MIPS_SYS(sys_accept4, 4) 2352 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2353 MIPS_SYS(sys_fanotify_init, 2) 2354 MIPS_SYS(sys_fanotify_mark, 6) 2355 MIPS_SYS(sys_prlimit64, 4) 2356 MIPS_SYS(sys_name_to_handle_at, 5) 2357 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2358 MIPS_SYS(sys_clock_adjtime, 2) 2359 MIPS_SYS(sys_syncfs, 1) 2360 }; 2361 # undef MIPS_SYS 2362 # endif /* O32 */ 2363 2364 static int do_store_exclusive(CPUMIPSState *env) 2365 { 2366 target_ulong addr; 2367 target_ulong page_addr; 2368 target_ulong val; 2369 int flags; 2370 int segv = 0; 2371 int reg; 2372 int d; 2373 2374 addr = env->lladdr; 2375 page_addr = addr & TARGET_PAGE_MASK; 2376 start_exclusive(); 2377 mmap_lock(); 2378 flags = page_get_flags(page_addr); 2379 if ((flags & PAGE_READ) == 0) { 2380 segv = 1; 2381 } else { 2382 reg = env->llreg & 0x1f; 2383 d = (env->llreg & 0x20) != 0; 2384 if (d) { 2385 segv = get_user_s64(val, addr); 2386 } else { 2387 segv = get_user_s32(val, addr); 2388 } 2389 if (!segv) { 2390 if (val != env->llval) { 2391 env->active_tc.gpr[reg] = 0; 2392 } else { 2393 if (d) { 2394 segv = put_user_u64(env->llnewval, addr); 2395 } else { 2396 segv = put_user_u32(env->llnewval, addr); 2397 } 2398 if (!segv) { 2399 env->active_tc.gpr[reg] = 1; 2400 } 2401 } 2402 } 2403 } 2404 env->lladdr = -1; 2405 if (!segv) { 2406 env->active_tc.PC += 4; 2407 } 2408 mmap_unlock(); 2409 end_exclusive(); 2410 return segv; 2411 } 2412 2413 /* Break codes */ 2414 enum { 2415 BRK_OVERFLOW = 6, 2416 BRK_DIVZERO = 7 2417 }; 2418 2419 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2420 unsigned int code) 2421 { 2422 int ret = -1; 2423 2424 switch (code) { 2425 case BRK_OVERFLOW: 2426 case BRK_DIVZERO: 2427 info->si_signo = TARGET_SIGFPE; 2428 info->si_errno = 0; 2429 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2430 queue_signal(env, info->si_signo, &*info); 2431 ret = 0; 2432 break; 2433 default: 2434 info->si_signo = TARGET_SIGTRAP; 2435 info->si_errno = 0; 2436 queue_signal(env, info->si_signo, &*info); 2437 ret = 0; 2438 break; 2439 } 2440 2441 return ret; 2442 } 2443 2444 void cpu_loop(CPUMIPSState *env) 2445 { 2446 CPUState *cs = CPU(mips_env_get_cpu(env)); 2447 target_siginfo_t info; 2448 int trapnr; 2449 abi_long ret; 2450 # ifdef TARGET_ABI_MIPSO32 2451 unsigned int syscall_num; 2452 # endif 2453 2454 for(;;) { 2455 cpu_exec_start(cs); 2456 trapnr = cpu_mips_exec(cs); 2457 cpu_exec_end(cs); 2458 switch(trapnr) { 2459 case EXCP_SYSCALL: 2460 env->active_tc.PC += 4; 2461 # ifdef TARGET_ABI_MIPSO32 2462 syscall_num = env->active_tc.gpr[2] - 4000; 2463 if (syscall_num >= sizeof(mips_syscall_args)) { 2464 ret = -TARGET_ENOSYS; 2465 } else { 2466 int nb_args; 2467 abi_ulong sp_reg; 2468 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2469 2470 nb_args = mips_syscall_args[syscall_num]; 2471 sp_reg = env->active_tc.gpr[29]; 2472 switch (nb_args) { 2473 /* these arguments are taken from the stack */ 2474 case 8: 2475 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2476 goto done_syscall; 2477 } 2478 case 7: 2479 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2480 goto done_syscall; 2481 } 2482 case 6: 2483 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2484 goto done_syscall; 2485 } 2486 case 5: 2487 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2488 goto done_syscall; 2489 } 2490 default: 2491 break; 2492 } 2493 ret = do_syscall(env, env->active_tc.gpr[2], 2494 env->active_tc.gpr[4], 2495 env->active_tc.gpr[5], 2496 env->active_tc.gpr[6], 2497 env->active_tc.gpr[7], 2498 arg5, arg6, arg7, arg8); 2499 } 2500 done_syscall: 2501 # else 2502 ret = do_syscall(env, env->active_tc.gpr[2], 2503 env->active_tc.gpr[4], env->active_tc.gpr[5], 2504 env->active_tc.gpr[6], env->active_tc.gpr[7], 2505 env->active_tc.gpr[8], env->active_tc.gpr[9], 2506 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2507 # endif /* O32 */ 2508 if (ret == -TARGET_QEMU_ESIGRETURN) { 2509 /* Returning from a successful sigreturn syscall. 2510 Avoid clobbering register state. */ 2511 break; 2512 } 2513 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2514 env->active_tc.gpr[7] = 1; /* error flag */ 2515 ret = -ret; 2516 } else { 2517 env->active_tc.gpr[7] = 0; /* error flag */ 2518 } 2519 env->active_tc.gpr[2] = ret; 2520 break; 2521 case EXCP_TLBL: 2522 case EXCP_TLBS: 2523 case EXCP_AdEL: 2524 case EXCP_AdES: 2525 info.si_signo = TARGET_SIGSEGV; 2526 info.si_errno = 0; 2527 /* XXX: check env->error_code */ 2528 info.si_code = TARGET_SEGV_MAPERR; 2529 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2530 queue_signal(env, info.si_signo, &info); 2531 break; 2532 case EXCP_CpU: 2533 case EXCP_RI: 2534 info.si_signo = TARGET_SIGILL; 2535 info.si_errno = 0; 2536 info.si_code = 0; 2537 queue_signal(env, info.si_signo, &info); 2538 break; 2539 case EXCP_INTERRUPT: 2540 /* just indicate that signals should be handled asap */ 2541 break; 2542 case EXCP_DEBUG: 2543 { 2544 int sig; 2545 2546 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2547 if (sig) 2548 { 2549 info.si_signo = sig; 2550 info.si_errno = 0; 2551 info.si_code = TARGET_TRAP_BRKPT; 2552 queue_signal(env, info.si_signo, &info); 2553 } 2554 } 2555 break; 2556 case EXCP_SC: 2557 if (do_store_exclusive(env)) { 2558 info.si_signo = TARGET_SIGSEGV; 2559 info.si_errno = 0; 2560 info.si_code = TARGET_SEGV_MAPERR; 2561 info._sifields._sigfault._addr = env->active_tc.PC; 2562 queue_signal(env, info.si_signo, &info); 2563 } 2564 break; 2565 case EXCP_DSPDIS: 2566 info.si_signo = TARGET_SIGILL; 2567 info.si_errno = 0; 2568 info.si_code = TARGET_ILL_ILLOPC; 2569 queue_signal(env, info.si_signo, &info); 2570 break; 2571 /* The code below was inspired by the MIPS Linux kernel trap 2572 * handling code in arch/mips/kernel/traps.c. 2573 */ 2574 case EXCP_BREAK: 2575 { 2576 abi_ulong trap_instr; 2577 unsigned int code; 2578 2579 if (env->hflags & MIPS_HFLAG_M16) { 2580 if (env->insn_flags & ASE_MICROMIPS) { 2581 /* microMIPS mode */ 2582 ret = get_user_u16(trap_instr, env->active_tc.PC); 2583 if (ret != 0) { 2584 goto error; 2585 } 2586 2587 if ((trap_instr >> 10) == 0x11) { 2588 /* 16-bit instruction */ 2589 code = trap_instr & 0xf; 2590 } else { 2591 /* 32-bit instruction */ 2592 abi_ulong instr_lo; 2593 2594 ret = get_user_u16(instr_lo, 2595 env->active_tc.PC + 2); 2596 if (ret != 0) { 2597 goto error; 2598 } 2599 trap_instr = (trap_instr << 16) | instr_lo; 2600 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2601 /* Unfortunately, microMIPS also suffers from 2602 the old assembler bug... */ 2603 if (code >= (1 << 10)) { 2604 code >>= 10; 2605 } 2606 } 2607 } else { 2608 /* MIPS16e mode */ 2609 ret = get_user_u16(trap_instr, env->active_tc.PC); 2610 if (ret != 0) { 2611 goto error; 2612 } 2613 code = (trap_instr >> 6) & 0x3f; 2614 } 2615 } else { 2616 ret = get_user_u32(trap_instr, env->active_tc.PC); 2617 if (ret != 0) { 2618 goto error; 2619 } 2620 2621 /* As described in the original Linux kernel code, the 2622 * below checks on 'code' are to work around an old 2623 * assembly bug. 2624 */ 2625 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2626 if (code >= (1 << 10)) { 2627 code >>= 10; 2628 } 2629 } 2630 2631 if (do_break(env, &info, code) != 0) { 2632 goto error; 2633 } 2634 } 2635 break; 2636 case EXCP_TRAP: 2637 { 2638 abi_ulong trap_instr; 2639 unsigned int code = 0; 2640 2641 if (env->hflags & MIPS_HFLAG_M16) { 2642 /* microMIPS mode */ 2643 abi_ulong instr[2]; 2644 2645 ret = get_user_u16(instr[0], env->active_tc.PC) || 2646 get_user_u16(instr[1], env->active_tc.PC + 2); 2647 2648 trap_instr = (instr[0] << 16) | instr[1]; 2649 } else { 2650 ret = get_user_u32(trap_instr, env->active_tc.PC); 2651 } 2652 2653 if (ret != 0) { 2654 goto error; 2655 } 2656 2657 /* The immediate versions don't provide a code. */ 2658 if (!(trap_instr & 0xFC000000)) { 2659 if (env->hflags & MIPS_HFLAG_M16) { 2660 /* microMIPS mode */ 2661 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 2662 } else { 2663 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2664 } 2665 } 2666 2667 if (do_break(env, &info, code) != 0) { 2668 goto error; 2669 } 2670 } 2671 break; 2672 default: 2673 error: 2674 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 2675 abort(); 2676 } 2677 process_pending_signals(env); 2678 } 2679 } 2680 #endif 2681 2682 #ifdef TARGET_OPENRISC 2683 2684 void cpu_loop(CPUOpenRISCState *env) 2685 { 2686 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2687 int trapnr, gdbsig; 2688 2689 for (;;) { 2690 cpu_exec_start(cs); 2691 trapnr = cpu_openrisc_exec(cs); 2692 cpu_exec_end(cs); 2693 gdbsig = 0; 2694 2695 switch (trapnr) { 2696 case EXCP_RESET: 2697 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc); 2698 exit(EXIT_FAILURE); 2699 break; 2700 case EXCP_BUSERR: 2701 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc); 2702 gdbsig = TARGET_SIGBUS; 2703 break; 2704 case EXCP_DPF: 2705 case EXCP_IPF: 2706 cpu_dump_state(cs, stderr, fprintf, 0); 2707 gdbsig = TARGET_SIGSEGV; 2708 break; 2709 case EXCP_TICK: 2710 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc); 2711 break; 2712 case EXCP_ALIGN: 2713 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc); 2714 gdbsig = TARGET_SIGBUS; 2715 break; 2716 case EXCP_ILLEGAL: 2717 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc); 2718 gdbsig = TARGET_SIGILL; 2719 break; 2720 case EXCP_INT: 2721 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc); 2722 break; 2723 case EXCP_DTLBMISS: 2724 case EXCP_ITLBMISS: 2725 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n"); 2726 break; 2727 case EXCP_RANGE: 2728 qemu_log_mask(CPU_LOG_INT, "\nRange\n"); 2729 gdbsig = TARGET_SIGSEGV; 2730 break; 2731 case EXCP_SYSCALL: 2732 env->pc += 4; /* 0xc00; */ 2733 env->gpr[11] = do_syscall(env, 2734 env->gpr[11], /* return value */ 2735 env->gpr[3], /* r3 - r7 are params */ 2736 env->gpr[4], 2737 env->gpr[5], 2738 env->gpr[6], 2739 env->gpr[7], 2740 env->gpr[8], 0, 0); 2741 break; 2742 case EXCP_FPE: 2743 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n"); 2744 break; 2745 case EXCP_TRAP: 2746 qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); 2747 gdbsig = TARGET_SIGTRAP; 2748 break; 2749 case EXCP_NR: 2750 qemu_log_mask(CPU_LOG_INT, "\nNR\n"); 2751 break; 2752 default: 2753 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 2754 trapnr); 2755 gdbsig = TARGET_SIGILL; 2756 break; 2757 } 2758 if (gdbsig) { 2759 gdb_handlesig(cs, gdbsig); 2760 if (gdbsig != TARGET_SIGTRAP) { 2761 exit(EXIT_FAILURE); 2762 } 2763 } 2764 2765 process_pending_signals(env); 2766 } 2767 } 2768 2769 #endif /* TARGET_OPENRISC */ 2770 2771 #ifdef TARGET_SH4 2772 void cpu_loop(CPUSH4State *env) 2773 { 2774 CPUState *cs = CPU(sh_env_get_cpu(env)); 2775 int trapnr, ret; 2776 target_siginfo_t info; 2777 2778 while (1) { 2779 cpu_exec_start(cs); 2780 trapnr = cpu_sh4_exec(cs); 2781 cpu_exec_end(cs); 2782 2783 switch (trapnr) { 2784 case 0x160: 2785 env->pc += 2; 2786 ret = do_syscall(env, 2787 env->gregs[3], 2788 env->gregs[4], 2789 env->gregs[5], 2790 env->gregs[6], 2791 env->gregs[7], 2792 env->gregs[0], 2793 env->gregs[1], 2794 0, 0); 2795 env->gregs[0] = ret; 2796 break; 2797 case EXCP_INTERRUPT: 2798 /* just indicate that signals should be handled asap */ 2799 break; 2800 case EXCP_DEBUG: 2801 { 2802 int sig; 2803 2804 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2805 if (sig) 2806 { 2807 info.si_signo = sig; 2808 info.si_errno = 0; 2809 info.si_code = TARGET_TRAP_BRKPT; 2810 queue_signal(env, info.si_signo, &info); 2811 } 2812 } 2813 break; 2814 case 0xa0: 2815 case 0xc0: 2816 info.si_signo = TARGET_SIGSEGV; 2817 info.si_errno = 0; 2818 info.si_code = TARGET_SEGV_MAPERR; 2819 info._sifields._sigfault._addr = env->tea; 2820 queue_signal(env, info.si_signo, &info); 2821 break; 2822 2823 default: 2824 printf ("Unhandled trap: 0x%x\n", trapnr); 2825 cpu_dump_state(cs, stderr, fprintf, 0); 2826 exit(EXIT_FAILURE); 2827 } 2828 process_pending_signals (env); 2829 } 2830 } 2831 #endif 2832 2833 #ifdef TARGET_CRIS 2834 void cpu_loop(CPUCRISState *env) 2835 { 2836 CPUState *cs = CPU(cris_env_get_cpu(env)); 2837 int trapnr, ret; 2838 target_siginfo_t info; 2839 2840 while (1) { 2841 cpu_exec_start(cs); 2842 trapnr = cpu_cris_exec(cs); 2843 cpu_exec_end(cs); 2844 switch (trapnr) { 2845 case 0xaa: 2846 { 2847 info.si_signo = TARGET_SIGSEGV; 2848 info.si_errno = 0; 2849 /* XXX: check env->error_code */ 2850 info.si_code = TARGET_SEGV_MAPERR; 2851 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2852 queue_signal(env, info.si_signo, &info); 2853 } 2854 break; 2855 case EXCP_INTERRUPT: 2856 /* just indicate that signals should be handled asap */ 2857 break; 2858 case EXCP_BREAK: 2859 ret = do_syscall(env, 2860 env->regs[9], 2861 env->regs[10], 2862 env->regs[11], 2863 env->regs[12], 2864 env->regs[13], 2865 env->pregs[7], 2866 env->pregs[11], 2867 0, 0); 2868 env->regs[10] = ret; 2869 break; 2870 case EXCP_DEBUG: 2871 { 2872 int sig; 2873 2874 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2875 if (sig) 2876 { 2877 info.si_signo = sig; 2878 info.si_errno = 0; 2879 info.si_code = TARGET_TRAP_BRKPT; 2880 queue_signal(env, info.si_signo, &info); 2881 } 2882 } 2883 break; 2884 default: 2885 printf ("Unhandled trap: 0x%x\n", trapnr); 2886 cpu_dump_state(cs, stderr, fprintf, 0); 2887 exit(EXIT_FAILURE); 2888 } 2889 process_pending_signals (env); 2890 } 2891 } 2892 #endif 2893 2894 #ifdef TARGET_MICROBLAZE 2895 void cpu_loop(CPUMBState *env) 2896 { 2897 CPUState *cs = CPU(mb_env_get_cpu(env)); 2898 int trapnr, ret; 2899 target_siginfo_t info; 2900 2901 while (1) { 2902 cpu_exec_start(cs); 2903 trapnr = cpu_mb_exec(cs); 2904 cpu_exec_end(cs); 2905 switch (trapnr) { 2906 case 0xaa: 2907 { 2908 info.si_signo = TARGET_SIGSEGV; 2909 info.si_errno = 0; 2910 /* XXX: check env->error_code */ 2911 info.si_code = TARGET_SEGV_MAPERR; 2912 info._sifields._sigfault._addr = 0; 2913 queue_signal(env, info.si_signo, &info); 2914 } 2915 break; 2916 case EXCP_INTERRUPT: 2917 /* just indicate that signals should be handled asap */ 2918 break; 2919 case EXCP_BREAK: 2920 /* Return address is 4 bytes after the call. */ 2921 env->regs[14] += 4; 2922 env->sregs[SR_PC] = env->regs[14]; 2923 ret = do_syscall(env, 2924 env->regs[12], 2925 env->regs[5], 2926 env->regs[6], 2927 env->regs[7], 2928 env->regs[8], 2929 env->regs[9], 2930 env->regs[10], 2931 0, 0); 2932 env->regs[3] = ret; 2933 break; 2934 case EXCP_HW_EXCP: 2935 env->regs[17] = env->sregs[SR_PC] + 4; 2936 if (env->iflags & D_FLAG) { 2937 env->sregs[SR_ESR] |= 1 << 12; 2938 env->sregs[SR_PC] -= 4; 2939 /* FIXME: if branch was immed, replay the imm as well. */ 2940 } 2941 2942 env->iflags &= ~(IMM_FLAG | D_FLAG); 2943 2944 switch (env->sregs[SR_ESR] & 31) { 2945 case ESR_EC_DIVZERO: 2946 info.si_signo = TARGET_SIGFPE; 2947 info.si_errno = 0; 2948 info.si_code = TARGET_FPE_FLTDIV; 2949 info._sifields._sigfault._addr = 0; 2950 queue_signal(env, info.si_signo, &info); 2951 break; 2952 case ESR_EC_FPU: 2953 info.si_signo = TARGET_SIGFPE; 2954 info.si_errno = 0; 2955 if (env->sregs[SR_FSR] & FSR_IO) { 2956 info.si_code = TARGET_FPE_FLTINV; 2957 } 2958 if (env->sregs[SR_FSR] & FSR_DZ) { 2959 info.si_code = TARGET_FPE_FLTDIV; 2960 } 2961 info._sifields._sigfault._addr = 0; 2962 queue_signal(env, info.si_signo, &info); 2963 break; 2964 default: 2965 printf ("Unhandled hw-exception: 0x%x\n", 2966 env->sregs[SR_ESR] & ESR_EC_MASK); 2967 cpu_dump_state(cs, stderr, fprintf, 0); 2968 exit(EXIT_FAILURE); 2969 break; 2970 } 2971 break; 2972 case EXCP_DEBUG: 2973 { 2974 int sig; 2975 2976 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2977 if (sig) 2978 { 2979 info.si_signo = sig; 2980 info.si_errno = 0; 2981 info.si_code = TARGET_TRAP_BRKPT; 2982 queue_signal(env, info.si_signo, &info); 2983 } 2984 } 2985 break; 2986 default: 2987 printf ("Unhandled trap: 0x%x\n", trapnr); 2988 cpu_dump_state(cs, stderr, fprintf, 0); 2989 exit(EXIT_FAILURE); 2990 } 2991 process_pending_signals (env); 2992 } 2993 } 2994 #endif 2995 2996 #ifdef TARGET_M68K 2997 2998 void cpu_loop(CPUM68KState *env) 2999 { 3000 CPUState *cs = CPU(m68k_env_get_cpu(env)); 3001 int trapnr; 3002 unsigned int n; 3003 target_siginfo_t info; 3004 TaskState *ts = cs->opaque; 3005 3006 for(;;) { 3007 cpu_exec_start(cs); 3008 trapnr = cpu_m68k_exec(cs); 3009 cpu_exec_end(cs); 3010 switch(trapnr) { 3011 case EXCP_ILLEGAL: 3012 { 3013 if (ts->sim_syscalls) { 3014 uint16_t nr; 3015 get_user_u16(nr, env->pc + 2); 3016 env->pc += 4; 3017 do_m68k_simcall(env, nr); 3018 } else { 3019 goto do_sigill; 3020 } 3021 } 3022 break; 3023 case EXCP_HALT_INSN: 3024 /* Semihosing syscall. */ 3025 env->pc += 4; 3026 do_m68k_semihosting(env, env->dregs[0]); 3027 break; 3028 case EXCP_LINEA: 3029 case EXCP_LINEF: 3030 case EXCP_UNSUPPORTED: 3031 do_sigill: 3032 info.si_signo = TARGET_SIGILL; 3033 info.si_errno = 0; 3034 info.si_code = TARGET_ILL_ILLOPN; 3035 info._sifields._sigfault._addr = env->pc; 3036 queue_signal(env, info.si_signo, &info); 3037 break; 3038 case EXCP_TRAP0: 3039 { 3040 ts->sim_syscalls = 0; 3041 n = env->dregs[0]; 3042 env->pc += 2; 3043 env->dregs[0] = do_syscall(env, 3044 n, 3045 env->dregs[1], 3046 env->dregs[2], 3047 env->dregs[3], 3048 env->dregs[4], 3049 env->dregs[5], 3050 env->aregs[0], 3051 0, 0); 3052 } 3053 break; 3054 case EXCP_INTERRUPT: 3055 /* just indicate that signals should be handled asap */ 3056 break; 3057 case EXCP_ACCESS: 3058 { 3059 info.si_signo = TARGET_SIGSEGV; 3060 info.si_errno = 0; 3061 /* XXX: check env->error_code */ 3062 info.si_code = TARGET_SEGV_MAPERR; 3063 info._sifields._sigfault._addr = env->mmu.ar; 3064 queue_signal(env, info.si_signo, &info); 3065 } 3066 break; 3067 case EXCP_DEBUG: 3068 { 3069 int sig; 3070 3071 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3072 if (sig) 3073 { 3074 info.si_signo = sig; 3075 info.si_errno = 0; 3076 info.si_code = TARGET_TRAP_BRKPT; 3077 queue_signal(env, info.si_signo, &info); 3078 } 3079 } 3080 break; 3081 default: 3082 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 3083 abort(); 3084 } 3085 process_pending_signals(env); 3086 } 3087 } 3088 #endif /* TARGET_M68K */ 3089 3090 #ifdef TARGET_ALPHA 3091 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 3092 { 3093 target_ulong addr, val, tmp; 3094 target_siginfo_t info; 3095 int ret = 0; 3096 3097 addr = env->lock_addr; 3098 tmp = env->lock_st_addr; 3099 env->lock_addr = -1; 3100 env->lock_st_addr = 0; 3101 3102 start_exclusive(); 3103 mmap_lock(); 3104 3105 if (addr == tmp) { 3106 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3107 goto do_sigsegv; 3108 } 3109 3110 if (val == env->lock_value) { 3111 tmp = env->ir[reg]; 3112 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 3113 goto do_sigsegv; 3114 } 3115 ret = 1; 3116 } 3117 } 3118 env->ir[reg] = ret; 3119 env->pc += 4; 3120 3121 mmap_unlock(); 3122 end_exclusive(); 3123 return; 3124 3125 do_sigsegv: 3126 mmap_unlock(); 3127 end_exclusive(); 3128 3129 info.si_signo = TARGET_SIGSEGV; 3130 info.si_errno = 0; 3131 info.si_code = TARGET_SEGV_MAPERR; 3132 info._sifields._sigfault._addr = addr; 3133 queue_signal(env, TARGET_SIGSEGV, &info); 3134 } 3135 3136 void cpu_loop(CPUAlphaState *env) 3137 { 3138 CPUState *cs = CPU(alpha_env_get_cpu(env)); 3139 int trapnr; 3140 target_siginfo_t info; 3141 abi_long sysret; 3142 3143 while (1) { 3144 cpu_exec_start(cs); 3145 trapnr = cpu_alpha_exec(cs); 3146 cpu_exec_end(cs); 3147 3148 /* All of the traps imply a transition through PALcode, which 3149 implies an REI instruction has been executed. Which means 3150 that the intr_flag should be cleared. */ 3151 env->intr_flag = 0; 3152 3153 switch (trapnr) { 3154 case EXCP_RESET: 3155 fprintf(stderr, "Reset requested. Exit\n"); 3156 exit(EXIT_FAILURE); 3157 break; 3158 case EXCP_MCHK: 3159 fprintf(stderr, "Machine check exception. Exit\n"); 3160 exit(EXIT_FAILURE); 3161 break; 3162 case EXCP_SMP_INTERRUPT: 3163 case EXCP_CLK_INTERRUPT: 3164 case EXCP_DEV_INTERRUPT: 3165 fprintf(stderr, "External interrupt. Exit\n"); 3166 exit(EXIT_FAILURE); 3167 break; 3168 case EXCP_MMFAULT: 3169 env->lock_addr = -1; 3170 info.si_signo = TARGET_SIGSEGV; 3171 info.si_errno = 0; 3172 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 3173 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 3174 info._sifields._sigfault._addr = env->trap_arg0; 3175 queue_signal(env, info.si_signo, &info); 3176 break; 3177 case EXCP_UNALIGN: 3178 env->lock_addr = -1; 3179 info.si_signo = TARGET_SIGBUS; 3180 info.si_errno = 0; 3181 info.si_code = TARGET_BUS_ADRALN; 3182 info._sifields._sigfault._addr = env->trap_arg0; 3183 queue_signal(env, info.si_signo, &info); 3184 break; 3185 case EXCP_OPCDEC: 3186 do_sigill: 3187 env->lock_addr = -1; 3188 info.si_signo = TARGET_SIGILL; 3189 info.si_errno = 0; 3190 info.si_code = TARGET_ILL_ILLOPC; 3191 info._sifields._sigfault._addr = env->pc; 3192 queue_signal(env, info.si_signo, &info); 3193 break; 3194 case EXCP_ARITH: 3195 env->lock_addr = -1; 3196 info.si_signo = TARGET_SIGFPE; 3197 info.si_errno = 0; 3198 info.si_code = TARGET_FPE_FLTINV; 3199 info._sifields._sigfault._addr = env->pc; 3200 queue_signal(env, info.si_signo, &info); 3201 break; 3202 case EXCP_FEN: 3203 /* No-op. Linux simply re-enables the FPU. */ 3204 break; 3205 case EXCP_CALL_PAL: 3206 env->lock_addr = -1; 3207 switch (env->error_code) { 3208 case 0x80: 3209 /* BPT */ 3210 info.si_signo = TARGET_SIGTRAP; 3211 info.si_errno = 0; 3212 info.si_code = TARGET_TRAP_BRKPT; 3213 info._sifields._sigfault._addr = env->pc; 3214 queue_signal(env, info.si_signo, &info); 3215 break; 3216 case 0x81: 3217 /* BUGCHK */ 3218 info.si_signo = TARGET_SIGTRAP; 3219 info.si_errno = 0; 3220 info.si_code = 0; 3221 info._sifields._sigfault._addr = env->pc; 3222 queue_signal(env, info.si_signo, &info); 3223 break; 3224 case 0x83: 3225 /* CALLSYS */ 3226 trapnr = env->ir[IR_V0]; 3227 sysret = do_syscall(env, trapnr, 3228 env->ir[IR_A0], env->ir[IR_A1], 3229 env->ir[IR_A2], env->ir[IR_A3], 3230 env->ir[IR_A4], env->ir[IR_A5], 3231 0, 0); 3232 if (trapnr == TARGET_NR_sigreturn 3233 || trapnr == TARGET_NR_rt_sigreturn) { 3234 break; 3235 } 3236 /* Syscall writes 0 to V0 to bypass error check, similar 3237 to how this is handled internal to Linux kernel. 3238 (Ab)use trapnr temporarily as boolean indicating error. */ 3239 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 3240 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 3241 env->ir[IR_A3] = trapnr; 3242 break; 3243 case 0x86: 3244 /* IMB */ 3245 /* ??? We can probably elide the code using page_unprotect 3246 that is checking for self-modifying code. Instead we 3247 could simply call tb_flush here. Until we work out the 3248 changes required to turn off the extra write protection, 3249 this can be a no-op. */ 3250 break; 3251 case 0x9E: 3252 /* RDUNIQUE */ 3253 /* Handled in the translator for usermode. */ 3254 abort(); 3255 case 0x9F: 3256 /* WRUNIQUE */ 3257 /* Handled in the translator for usermode. */ 3258 abort(); 3259 case 0xAA: 3260 /* GENTRAP */ 3261 info.si_signo = TARGET_SIGFPE; 3262 switch (env->ir[IR_A0]) { 3263 case TARGET_GEN_INTOVF: 3264 info.si_code = TARGET_FPE_INTOVF; 3265 break; 3266 case TARGET_GEN_INTDIV: 3267 info.si_code = TARGET_FPE_INTDIV; 3268 break; 3269 case TARGET_GEN_FLTOVF: 3270 info.si_code = TARGET_FPE_FLTOVF; 3271 break; 3272 case TARGET_GEN_FLTUND: 3273 info.si_code = TARGET_FPE_FLTUND; 3274 break; 3275 case TARGET_GEN_FLTINV: 3276 info.si_code = TARGET_FPE_FLTINV; 3277 break; 3278 case TARGET_GEN_FLTINE: 3279 info.si_code = TARGET_FPE_FLTRES; 3280 break; 3281 case TARGET_GEN_ROPRAND: 3282 info.si_code = 0; 3283 break; 3284 default: 3285 info.si_signo = TARGET_SIGTRAP; 3286 info.si_code = 0; 3287 break; 3288 } 3289 info.si_errno = 0; 3290 info._sifields._sigfault._addr = env->pc; 3291 queue_signal(env, info.si_signo, &info); 3292 break; 3293 default: 3294 goto do_sigill; 3295 } 3296 break; 3297 case EXCP_DEBUG: 3298 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); 3299 if (info.si_signo) { 3300 env->lock_addr = -1; 3301 info.si_errno = 0; 3302 info.si_code = TARGET_TRAP_BRKPT; 3303 queue_signal(env, info.si_signo, &info); 3304 } 3305 break; 3306 case EXCP_STL_C: 3307 case EXCP_STQ_C: 3308 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3309 break; 3310 case EXCP_INTERRUPT: 3311 /* Just indicate that signals should be handled asap. */ 3312 break; 3313 default: 3314 printf ("Unhandled trap: 0x%x\n", trapnr); 3315 cpu_dump_state(cs, stderr, fprintf, 0); 3316 exit(EXIT_FAILURE); 3317 } 3318 process_pending_signals (env); 3319 } 3320 } 3321 #endif /* TARGET_ALPHA */ 3322 3323 #ifdef TARGET_S390X 3324 void cpu_loop(CPUS390XState *env) 3325 { 3326 CPUState *cs = CPU(s390_env_get_cpu(env)); 3327 int trapnr, n, sig; 3328 target_siginfo_t info; 3329 target_ulong addr; 3330 3331 while (1) { 3332 cpu_exec_start(cs); 3333 trapnr = cpu_s390x_exec(cs); 3334 cpu_exec_end(cs); 3335 switch (trapnr) { 3336 case EXCP_INTERRUPT: 3337 /* Just indicate that signals should be handled asap. */ 3338 break; 3339 3340 case EXCP_SVC: 3341 n = env->int_svc_code; 3342 if (!n) { 3343 /* syscalls > 255 */ 3344 n = env->regs[1]; 3345 } 3346 env->psw.addr += env->int_svc_ilen; 3347 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], 3348 env->regs[4], env->regs[5], 3349 env->regs[6], env->regs[7], 0, 0); 3350 break; 3351 3352 case EXCP_DEBUG: 3353 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3354 if (sig) { 3355 n = TARGET_TRAP_BRKPT; 3356 goto do_signal_pc; 3357 } 3358 break; 3359 case EXCP_PGM: 3360 n = env->int_pgm_code; 3361 switch (n) { 3362 case PGM_OPERATION: 3363 case PGM_PRIVILEGED: 3364 sig = TARGET_SIGILL; 3365 n = TARGET_ILL_ILLOPC; 3366 goto do_signal_pc; 3367 case PGM_PROTECTION: 3368 case PGM_ADDRESSING: 3369 sig = TARGET_SIGSEGV; 3370 /* XXX: check env->error_code */ 3371 n = TARGET_SEGV_MAPERR; 3372 addr = env->__excp_addr; 3373 goto do_signal; 3374 case PGM_EXECUTE: 3375 case PGM_SPECIFICATION: 3376 case PGM_SPECIAL_OP: 3377 case PGM_OPERAND: 3378 do_sigill_opn: 3379 sig = TARGET_SIGILL; 3380 n = TARGET_ILL_ILLOPN; 3381 goto do_signal_pc; 3382 3383 case PGM_FIXPT_OVERFLOW: 3384 sig = TARGET_SIGFPE; 3385 n = TARGET_FPE_INTOVF; 3386 goto do_signal_pc; 3387 case PGM_FIXPT_DIVIDE: 3388 sig = TARGET_SIGFPE; 3389 n = TARGET_FPE_INTDIV; 3390 goto do_signal_pc; 3391 3392 case PGM_DATA: 3393 n = (env->fpc >> 8) & 0xff; 3394 if (n == 0xff) { 3395 /* compare-and-trap */ 3396 goto do_sigill_opn; 3397 } else { 3398 /* An IEEE exception, simulated or otherwise. */ 3399 if (n & 0x80) { 3400 n = TARGET_FPE_FLTINV; 3401 } else if (n & 0x40) { 3402 n = TARGET_FPE_FLTDIV; 3403 } else if (n & 0x20) { 3404 n = TARGET_FPE_FLTOVF; 3405 } else if (n & 0x10) { 3406 n = TARGET_FPE_FLTUND; 3407 } else if (n & 0x08) { 3408 n = TARGET_FPE_FLTRES; 3409 } else { 3410 /* ??? Quantum exception; BFP, DFP error. */ 3411 goto do_sigill_opn; 3412 } 3413 sig = TARGET_SIGFPE; 3414 goto do_signal_pc; 3415 } 3416 3417 default: 3418 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3419 cpu_dump_state(cs, stderr, fprintf, 0); 3420 exit(EXIT_FAILURE); 3421 } 3422 break; 3423 3424 do_signal_pc: 3425 addr = env->psw.addr; 3426 do_signal: 3427 info.si_signo = sig; 3428 info.si_errno = 0; 3429 info.si_code = n; 3430 info._sifields._sigfault._addr = addr; 3431 queue_signal(env, info.si_signo, &info); 3432 break; 3433 3434 default: 3435 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3436 cpu_dump_state(cs, stderr, fprintf, 0); 3437 exit(EXIT_FAILURE); 3438 } 3439 process_pending_signals (env); 3440 } 3441 } 3442 3443 #endif /* TARGET_S390X */ 3444 3445 #ifdef TARGET_TILEGX 3446 3447 static void gen_sigill_reg(CPUTLGState *env) 3448 { 3449 target_siginfo_t info; 3450 3451 info.si_signo = TARGET_SIGILL; 3452 info.si_errno = 0; 3453 info.si_code = TARGET_ILL_PRVREG; 3454 info._sifields._sigfault._addr = env->pc; 3455 queue_signal(env, info.si_signo, &info); 3456 } 3457 3458 static void do_signal(CPUTLGState *env, int signo, int sigcode) 3459 { 3460 target_siginfo_t info; 3461 3462 info.si_signo = signo; 3463 info.si_errno = 0; 3464 info._sifields._sigfault._addr = env->pc; 3465 3466 if (signo == TARGET_SIGSEGV) { 3467 /* The passed in sigcode is a dummy; check for a page mapping 3468 and pass either MAPERR or ACCERR. */ 3469 target_ulong addr = env->excaddr; 3470 info._sifields._sigfault._addr = addr; 3471 if (page_check_range(addr, 1, PAGE_VALID) < 0) { 3472 sigcode = TARGET_SEGV_MAPERR; 3473 } else { 3474 sigcode = TARGET_SEGV_ACCERR; 3475 } 3476 } 3477 info.si_code = sigcode; 3478 3479 queue_signal(env, info.si_signo, &info); 3480 } 3481 3482 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) 3483 { 3484 env->excaddr = addr; 3485 do_signal(env, TARGET_SIGSEGV, 0); 3486 } 3487 3488 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) 3489 { 3490 if (unlikely(reg >= TILEGX_R_COUNT)) { 3491 switch (reg) { 3492 case TILEGX_R_SN: 3493 case TILEGX_R_ZERO: 3494 return; 3495 case TILEGX_R_IDN0: 3496 case TILEGX_R_IDN1: 3497 case TILEGX_R_UDN0: 3498 case TILEGX_R_UDN1: 3499 case TILEGX_R_UDN2: 3500 case TILEGX_R_UDN3: 3501 gen_sigill_reg(env); 3502 return; 3503 default: 3504 g_assert_not_reached(); 3505 } 3506 } 3507 env->regs[reg] = val; 3508 } 3509 3510 /* 3511 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in 3512 * memory at the address held in the first source register. If the values are 3513 * not equal, then no memory operation is performed. If the values are equal, 3514 * the 8-byte quantity from the second source register is written into memory 3515 * at the address held in the first source register. In either case, the result 3516 * of the instruction is the value read from memory. The compare and write to 3517 * memory are atomic and thus can be used for synchronization purposes. This 3518 * instruction only operates for addresses aligned to a 8-byte boundary. 3519 * Unaligned memory access causes an Unaligned Data Reference interrupt. 3520 * 3521 * Functional Description (64-bit) 3522 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); 3523 * rf[Dest] = memVal; 3524 * if (memVal == SPR[CmpValueSPR]) 3525 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); 3526 * 3527 * Functional Description (32-bit) 3528 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); 3529 * rf[Dest] = memVal; 3530 * if (memVal == signExtend32 (SPR[CmpValueSPR])) 3531 * memoryWriteWord (rf[SrcA], rf[SrcB]); 3532 * 3533 * 3534 * This function also processes exch and exch4 which need not process SPR. 3535 */ 3536 static void do_exch(CPUTLGState *env, bool quad, bool cmp) 3537 { 3538 target_ulong addr; 3539 target_long val, sprval; 3540 3541 start_exclusive(); 3542 3543 addr = env->atomic_srca; 3544 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3545 goto sigsegv_maperr; 3546 } 3547 3548 if (cmp) { 3549 if (quad) { 3550 sprval = env->spregs[TILEGX_SPR_CMPEXCH]; 3551 } else { 3552 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); 3553 } 3554 } 3555 3556 if (!cmp || val == sprval) { 3557 target_long valb = env->atomic_srcb; 3558 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3559 goto sigsegv_maperr; 3560 } 3561 } 3562 3563 set_regval(env, env->atomic_dstr, val); 3564 end_exclusive(); 3565 return; 3566 3567 sigsegv_maperr: 3568 end_exclusive(); 3569 gen_sigsegv_maperr(env, addr); 3570 } 3571 3572 static void do_fetch(CPUTLGState *env, int trapnr, bool quad) 3573 { 3574 int8_t write = 1; 3575 target_ulong addr; 3576 target_long val, valb; 3577 3578 start_exclusive(); 3579 3580 addr = env->atomic_srca; 3581 valb = env->atomic_srcb; 3582 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3583 goto sigsegv_maperr; 3584 } 3585 3586 switch (trapnr) { 3587 case TILEGX_EXCP_OPCODE_FETCHADD: 3588 case TILEGX_EXCP_OPCODE_FETCHADD4: 3589 valb += val; 3590 break; 3591 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3592 valb += val; 3593 if (valb < 0) { 3594 write = 0; 3595 } 3596 break; 3597 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3598 valb += val; 3599 if ((int32_t)valb < 0) { 3600 write = 0; 3601 } 3602 break; 3603 case TILEGX_EXCP_OPCODE_FETCHAND: 3604 case TILEGX_EXCP_OPCODE_FETCHAND4: 3605 valb &= val; 3606 break; 3607 case TILEGX_EXCP_OPCODE_FETCHOR: 3608 case TILEGX_EXCP_OPCODE_FETCHOR4: 3609 valb |= val; 3610 break; 3611 default: 3612 g_assert_not_reached(); 3613 } 3614 3615 if (write) { 3616 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3617 goto sigsegv_maperr; 3618 } 3619 } 3620 3621 set_regval(env, env->atomic_dstr, val); 3622 end_exclusive(); 3623 return; 3624 3625 sigsegv_maperr: 3626 end_exclusive(); 3627 gen_sigsegv_maperr(env, addr); 3628 } 3629 3630 void cpu_loop(CPUTLGState *env) 3631 { 3632 CPUState *cs = CPU(tilegx_env_get_cpu(env)); 3633 int trapnr; 3634 3635 while (1) { 3636 cpu_exec_start(cs); 3637 trapnr = cpu_tilegx_exec(cs); 3638 cpu_exec_end(cs); 3639 switch (trapnr) { 3640 case TILEGX_EXCP_SYSCALL: 3641 env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR], 3642 env->regs[0], env->regs[1], 3643 env->regs[2], env->regs[3], 3644 env->regs[4], env->regs[5], 3645 env->regs[6], env->regs[7]); 3646 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE]) 3647 ? - env->regs[TILEGX_R_RE] 3648 : 0; 3649 break; 3650 case TILEGX_EXCP_OPCODE_EXCH: 3651 do_exch(env, true, false); 3652 break; 3653 case TILEGX_EXCP_OPCODE_EXCH4: 3654 do_exch(env, false, false); 3655 break; 3656 case TILEGX_EXCP_OPCODE_CMPEXCH: 3657 do_exch(env, true, true); 3658 break; 3659 case TILEGX_EXCP_OPCODE_CMPEXCH4: 3660 do_exch(env, false, true); 3661 break; 3662 case TILEGX_EXCP_OPCODE_FETCHADD: 3663 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3664 case TILEGX_EXCP_OPCODE_FETCHAND: 3665 case TILEGX_EXCP_OPCODE_FETCHOR: 3666 do_fetch(env, trapnr, true); 3667 break; 3668 case TILEGX_EXCP_OPCODE_FETCHADD4: 3669 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3670 case TILEGX_EXCP_OPCODE_FETCHAND4: 3671 case TILEGX_EXCP_OPCODE_FETCHOR4: 3672 do_fetch(env, trapnr, false); 3673 break; 3674 case TILEGX_EXCP_SIGNAL: 3675 do_signal(env, env->signo, env->sigcode); 3676 break; 3677 case TILEGX_EXCP_REG_IDN_ACCESS: 3678 case TILEGX_EXCP_REG_UDN_ACCESS: 3679 gen_sigill_reg(env); 3680 break; 3681 default: 3682 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); 3683 g_assert_not_reached(); 3684 } 3685 process_pending_signals(env); 3686 } 3687 } 3688 3689 #endif 3690 3691 THREAD CPUState *thread_cpu; 3692 3693 void task_settid(TaskState *ts) 3694 { 3695 if (ts->ts_tid == 0) { 3696 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3697 } 3698 } 3699 3700 void stop_all_tasks(void) 3701 { 3702 /* 3703 * We trust that when using NPTL, start_exclusive() 3704 * handles thread stopping correctly. 3705 */ 3706 start_exclusive(); 3707 } 3708 3709 /* Assumes contents are already zeroed. */ 3710 void init_task_state(TaskState *ts) 3711 { 3712 int i; 3713 3714 ts->used = 1; 3715 ts->first_free = ts->sigqueue_table; 3716 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 3717 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 3718 } 3719 ts->sigqueue_table[i].next = NULL; 3720 } 3721 3722 CPUArchState *cpu_copy(CPUArchState *env) 3723 { 3724 CPUState *cpu = ENV_GET_CPU(env); 3725 CPUState *new_cpu = cpu_init(cpu_model); 3726 CPUArchState *new_env = new_cpu->env_ptr; 3727 CPUBreakpoint *bp; 3728 CPUWatchpoint *wp; 3729 3730 /* Reset non arch specific state */ 3731 cpu_reset(new_cpu); 3732 3733 memcpy(new_env, env, sizeof(CPUArchState)); 3734 3735 /* Clone all break/watchpoints. 3736 Note: Once we support ptrace with hw-debug register access, make sure 3737 BP_CPU break/watchpoints are handled correctly on clone. */ 3738 QTAILQ_INIT(&new_cpu->breakpoints); 3739 QTAILQ_INIT(&new_cpu->watchpoints); 3740 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 3741 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); 3742 } 3743 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { 3744 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); 3745 } 3746 3747 return new_env; 3748 } 3749 3750 static void handle_arg_help(const char *arg) 3751 { 3752 usage(EXIT_SUCCESS); 3753 } 3754 3755 static void handle_arg_log(const char *arg) 3756 { 3757 int mask; 3758 3759 mask = qemu_str_to_log_mask(arg); 3760 if (!mask) { 3761 qemu_print_log_usage(stdout); 3762 exit(EXIT_FAILURE); 3763 } 3764 qemu_log_needs_buffers(); 3765 qemu_set_log(mask); 3766 } 3767 3768 static void handle_arg_log_filename(const char *arg) 3769 { 3770 qemu_set_log_filename(arg); 3771 } 3772 3773 static void handle_arg_set_env(const char *arg) 3774 { 3775 char *r, *p, *token; 3776 r = p = strdup(arg); 3777 while ((token = strsep(&p, ",")) != NULL) { 3778 if (envlist_setenv(envlist, token) != 0) { 3779 usage(EXIT_FAILURE); 3780 } 3781 } 3782 free(r); 3783 } 3784 3785 static void handle_arg_unset_env(const char *arg) 3786 { 3787 char *r, *p, *token; 3788 r = p = strdup(arg); 3789 while ((token = strsep(&p, ",")) != NULL) { 3790 if (envlist_unsetenv(envlist, token) != 0) { 3791 usage(EXIT_FAILURE); 3792 } 3793 } 3794 free(r); 3795 } 3796 3797 static void handle_arg_argv0(const char *arg) 3798 { 3799 argv0 = strdup(arg); 3800 } 3801 3802 static void handle_arg_stack_size(const char *arg) 3803 { 3804 char *p; 3805 guest_stack_size = strtoul(arg, &p, 0); 3806 if (guest_stack_size == 0) { 3807 usage(EXIT_FAILURE); 3808 } 3809 3810 if (*p == 'M') { 3811 guest_stack_size *= 1024 * 1024; 3812 } else if (*p == 'k' || *p == 'K') { 3813 guest_stack_size *= 1024; 3814 } 3815 } 3816 3817 static void handle_arg_ld_prefix(const char *arg) 3818 { 3819 interp_prefix = strdup(arg); 3820 } 3821 3822 static void handle_arg_pagesize(const char *arg) 3823 { 3824 qemu_host_page_size = atoi(arg); 3825 if (qemu_host_page_size == 0 || 3826 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3827 fprintf(stderr, "page size must be a power of two\n"); 3828 exit(EXIT_FAILURE); 3829 } 3830 } 3831 3832 static void handle_arg_randseed(const char *arg) 3833 { 3834 unsigned long long seed; 3835 3836 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) { 3837 fprintf(stderr, "Invalid seed number: %s\n", arg); 3838 exit(EXIT_FAILURE); 3839 } 3840 srand(seed); 3841 } 3842 3843 static void handle_arg_gdb(const char *arg) 3844 { 3845 gdbstub_port = atoi(arg); 3846 } 3847 3848 static void handle_arg_uname(const char *arg) 3849 { 3850 qemu_uname_release = strdup(arg); 3851 } 3852 3853 static void handle_arg_cpu(const char *arg) 3854 { 3855 cpu_model = strdup(arg); 3856 if (cpu_model == NULL || is_help_option(cpu_model)) { 3857 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3858 #if defined(cpu_list) 3859 cpu_list(stdout, &fprintf); 3860 #endif 3861 exit(EXIT_FAILURE); 3862 } 3863 } 3864 3865 static void handle_arg_guest_base(const char *arg) 3866 { 3867 guest_base = strtol(arg, NULL, 0); 3868 have_guest_base = 1; 3869 } 3870 3871 static void handle_arg_reserved_va(const char *arg) 3872 { 3873 char *p; 3874 int shift = 0; 3875 reserved_va = strtoul(arg, &p, 0); 3876 switch (*p) { 3877 case 'k': 3878 case 'K': 3879 shift = 10; 3880 break; 3881 case 'M': 3882 shift = 20; 3883 break; 3884 case 'G': 3885 shift = 30; 3886 break; 3887 } 3888 if (shift) { 3889 unsigned long unshifted = reserved_va; 3890 p++; 3891 reserved_va <<= shift; 3892 if (((reserved_va >> shift) != unshifted) 3893 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3894 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3895 #endif 3896 ) { 3897 fprintf(stderr, "Reserved virtual address too big\n"); 3898 exit(EXIT_FAILURE); 3899 } 3900 } 3901 if (*p) { 3902 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3903 exit(EXIT_FAILURE); 3904 } 3905 } 3906 3907 static void handle_arg_singlestep(const char *arg) 3908 { 3909 singlestep = 1; 3910 } 3911 3912 static void handle_arg_strace(const char *arg) 3913 { 3914 do_strace = 1; 3915 } 3916 3917 static void handle_arg_version(const char *arg) 3918 { 3919 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3920 ", Copyright (c) 2003-2008 Fabrice Bellard\n"); 3921 exit(EXIT_SUCCESS); 3922 } 3923 3924 struct qemu_argument { 3925 const char *argv; 3926 const char *env; 3927 bool has_arg; 3928 void (*handle_opt)(const char *arg); 3929 const char *example; 3930 const char *help; 3931 }; 3932 3933 static const struct qemu_argument arg_table[] = { 3934 {"h", "", false, handle_arg_help, 3935 "", "print this help"}, 3936 {"help", "", false, handle_arg_help, 3937 "", ""}, 3938 {"g", "QEMU_GDB", true, handle_arg_gdb, 3939 "port", "wait gdb connection to 'port'"}, 3940 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3941 "path", "set the elf interpreter prefix to 'path'"}, 3942 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3943 "size", "set the stack size to 'size' bytes"}, 3944 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3945 "model", "select CPU (-cpu help for list)"}, 3946 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3947 "var=value", "sets targets environment variable (see below)"}, 3948 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3949 "var", "unsets targets environment variable (see below)"}, 3950 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 3951 "argv0", "forces target process argv[0] to be 'argv0'"}, 3952 {"r", "QEMU_UNAME", true, handle_arg_uname, 3953 "uname", "set qemu uname release string to 'uname'"}, 3954 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 3955 "address", "set guest_base address to 'address'"}, 3956 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 3957 "size", "reserve 'size' bytes for guest virtual address space"}, 3958 {"d", "QEMU_LOG", true, handle_arg_log, 3959 "item[,...]", "enable logging of specified items " 3960 "(use '-d help' for a list of items)"}, 3961 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 3962 "logfile", "write logs to 'logfile' (default stderr)"}, 3963 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 3964 "pagesize", "set the host page size to 'pagesize'"}, 3965 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 3966 "", "run in singlestep mode"}, 3967 {"strace", "QEMU_STRACE", false, handle_arg_strace, 3968 "", "log system calls"}, 3969 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed, 3970 "", "Seed for pseudo-random number generator"}, 3971 {"version", "QEMU_VERSION", false, handle_arg_version, 3972 "", "display version information and exit"}, 3973 {NULL, NULL, false, NULL, NULL, NULL} 3974 }; 3975 3976 static void usage(int exitcode) 3977 { 3978 const struct qemu_argument *arginfo; 3979 int maxarglen; 3980 int maxenvlen; 3981 3982 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 3983 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 3984 "\n" 3985 "Options and associated environment variables:\n" 3986 "\n"); 3987 3988 /* Calculate column widths. We must always have at least enough space 3989 * for the column header. 3990 */ 3991 maxarglen = strlen("Argument"); 3992 maxenvlen = strlen("Env-variable"); 3993 3994 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3995 int arglen = strlen(arginfo->argv); 3996 if (arginfo->has_arg) { 3997 arglen += strlen(arginfo->example) + 1; 3998 } 3999 if (strlen(arginfo->env) > maxenvlen) { 4000 maxenvlen = strlen(arginfo->env); 4001 } 4002 if (arglen > maxarglen) { 4003 maxarglen = arglen; 4004 } 4005 } 4006 4007 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 4008 maxenvlen, "Env-variable"); 4009 4010 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4011 if (arginfo->has_arg) { 4012 printf("-%s %-*s %-*s %s\n", arginfo->argv, 4013 (int)(maxarglen - strlen(arginfo->argv) - 1), 4014 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 4015 } else { 4016 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 4017 maxenvlen, arginfo->env, 4018 arginfo->help); 4019 } 4020 } 4021 4022 printf("\n" 4023 "Defaults:\n" 4024 "QEMU_LD_PREFIX = %s\n" 4025 "QEMU_STACK_SIZE = %ld byte\n", 4026 interp_prefix, 4027 guest_stack_size); 4028 4029 printf("\n" 4030 "You can use -E and -U options or the QEMU_SET_ENV and\n" 4031 "QEMU_UNSET_ENV environment variables to set and unset\n" 4032 "environment variables for the target process.\n" 4033 "It is possible to provide several variables by separating them\n" 4034 "by commas in getsubopt(3) style. Additionally it is possible to\n" 4035 "provide the -E and -U options multiple times.\n" 4036 "The following lines are equivalent:\n" 4037 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 4038 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 4039 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 4040 "Note that if you provide several changes to a single variable\n" 4041 "the last change will stay in effect.\n"); 4042 4043 exit(exitcode); 4044 } 4045 4046 static int parse_args(int argc, char **argv) 4047 { 4048 const char *r; 4049 int optind; 4050 const struct qemu_argument *arginfo; 4051 4052 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4053 if (arginfo->env == NULL) { 4054 continue; 4055 } 4056 4057 r = getenv(arginfo->env); 4058 if (r != NULL) { 4059 arginfo->handle_opt(r); 4060 } 4061 } 4062 4063 optind = 1; 4064 for (;;) { 4065 if (optind >= argc) { 4066 break; 4067 } 4068 r = argv[optind]; 4069 if (r[0] != '-') { 4070 break; 4071 } 4072 optind++; 4073 r++; 4074 if (!strcmp(r, "-")) { 4075 break; 4076 } 4077 /* Treat --foo the same as -foo. */ 4078 if (r[0] == '-') { 4079 r++; 4080 } 4081 4082 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4083 if (!strcmp(r, arginfo->argv)) { 4084 if (arginfo->has_arg) { 4085 if (optind >= argc) { 4086 (void) fprintf(stderr, 4087 "qemu: missing argument for option '%s'\n", r); 4088 exit(EXIT_FAILURE); 4089 } 4090 arginfo->handle_opt(argv[optind]); 4091 optind++; 4092 } else { 4093 arginfo->handle_opt(NULL); 4094 } 4095 break; 4096 } 4097 } 4098 4099 /* no option matched the current argv */ 4100 if (arginfo->handle_opt == NULL) { 4101 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r); 4102 exit(EXIT_FAILURE); 4103 } 4104 } 4105 4106 if (optind >= argc) { 4107 (void) fprintf(stderr, "qemu: no user program specified\n"); 4108 exit(EXIT_FAILURE); 4109 } 4110 4111 filename = argv[optind]; 4112 exec_path = argv[optind]; 4113 4114 return optind; 4115 } 4116 4117 int main(int argc, char **argv, char **envp) 4118 { 4119 struct target_pt_regs regs1, *regs = ®s1; 4120 struct image_info info1, *info = &info1; 4121 struct linux_binprm bprm; 4122 TaskState *ts; 4123 CPUArchState *env; 4124 CPUState *cpu; 4125 int optind; 4126 char **target_environ, **wrk; 4127 char **target_argv; 4128 int target_argc; 4129 int i; 4130 int ret; 4131 int execfd; 4132 4133 module_call_init(MODULE_INIT_QOM); 4134 4135 if ((envlist = envlist_create()) == NULL) { 4136 (void) fprintf(stderr, "Unable to allocate envlist\n"); 4137 exit(EXIT_FAILURE); 4138 } 4139 4140 /* add current environment into the list */ 4141 for (wrk = environ; *wrk != NULL; wrk++) { 4142 (void) envlist_setenv(envlist, *wrk); 4143 } 4144 4145 /* Read the stack limit from the kernel. If it's "unlimited", 4146 then we can do little else besides use the default. */ 4147 { 4148 struct rlimit lim; 4149 if (getrlimit(RLIMIT_STACK, &lim) == 0 4150 && lim.rlim_cur != RLIM_INFINITY 4151 && lim.rlim_cur == (target_long)lim.rlim_cur) { 4152 guest_stack_size = lim.rlim_cur; 4153 } 4154 } 4155 4156 cpu_model = NULL; 4157 #if defined(cpudef_setup) 4158 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ 4159 #endif 4160 4161 srand(time(NULL)); 4162 4163 optind = parse_args(argc, argv); 4164 4165 /* Zero out regs */ 4166 memset(regs, 0, sizeof(struct target_pt_regs)); 4167 4168 /* Zero out image_info */ 4169 memset(info, 0, sizeof(struct image_info)); 4170 4171 memset(&bprm, 0, sizeof (bprm)); 4172 4173 /* Scan interp_prefix dir for replacement files. */ 4174 init_paths(interp_prefix); 4175 4176 init_qemu_uname_release(); 4177 4178 if (cpu_model == NULL) { 4179 #if defined(TARGET_I386) 4180 #ifdef TARGET_X86_64 4181 cpu_model = "qemu64"; 4182 #else 4183 cpu_model = "qemu32"; 4184 #endif 4185 #elif defined(TARGET_ARM) 4186 cpu_model = "any"; 4187 #elif defined(TARGET_UNICORE32) 4188 cpu_model = "any"; 4189 #elif defined(TARGET_M68K) 4190 cpu_model = "any"; 4191 #elif defined(TARGET_SPARC) 4192 #ifdef TARGET_SPARC64 4193 cpu_model = "TI UltraSparc II"; 4194 #else 4195 cpu_model = "Fujitsu MB86904"; 4196 #endif 4197 #elif defined(TARGET_MIPS) 4198 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 4199 cpu_model = "5KEf"; 4200 #else 4201 cpu_model = "24Kf"; 4202 #endif 4203 #elif defined TARGET_OPENRISC 4204 cpu_model = "or1200"; 4205 #elif defined(TARGET_PPC) 4206 # ifdef TARGET_PPC64 4207 cpu_model = "POWER8"; 4208 # else 4209 cpu_model = "750"; 4210 # endif 4211 #elif defined TARGET_SH4 4212 cpu_model = TYPE_SH7785_CPU; 4213 #else 4214 cpu_model = "any"; 4215 #endif 4216 } 4217 tcg_exec_init(0); 4218 /* NOTE: we need to init the CPU at this stage to get 4219 qemu_host_page_size */ 4220 cpu = cpu_init(cpu_model); 4221 if (!cpu) { 4222 fprintf(stderr, "Unable to find CPU definition\n"); 4223 exit(EXIT_FAILURE); 4224 } 4225 env = cpu->env_ptr; 4226 cpu_reset(cpu); 4227 4228 thread_cpu = cpu; 4229 4230 if (getenv("QEMU_STRACE")) { 4231 do_strace = 1; 4232 } 4233 4234 if (getenv("QEMU_RAND_SEED")) { 4235 handle_arg_randseed(getenv("QEMU_RAND_SEED")); 4236 } 4237 4238 target_environ = envlist_to_environ(envlist, NULL); 4239 envlist_free(envlist); 4240 4241 /* 4242 * Now that page sizes are configured in cpu_init() we can do 4243 * proper page alignment for guest_base. 4244 */ 4245 guest_base = HOST_PAGE_ALIGN(guest_base); 4246 4247 if (reserved_va || have_guest_base) { 4248 guest_base = init_guest_space(guest_base, reserved_va, 0, 4249 have_guest_base); 4250 if (guest_base == (unsigned long)-1) { 4251 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 4252 "space for use as guest address space (check your virtual " 4253 "memory ulimit setting or reserve less using -R option)\n", 4254 reserved_va); 4255 exit(EXIT_FAILURE); 4256 } 4257 4258 if (reserved_va) { 4259 mmap_next_start = reserved_va; 4260 } 4261 } 4262 4263 /* 4264 * Read in mmap_min_addr kernel parameter. This value is used 4265 * When loading the ELF image to determine whether guest_base 4266 * is needed. It is also used in mmap_find_vma. 4267 */ 4268 { 4269 FILE *fp; 4270 4271 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 4272 unsigned long tmp; 4273 if (fscanf(fp, "%lu", &tmp) == 1) { 4274 mmap_min_addr = tmp; 4275 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr); 4276 } 4277 fclose(fp); 4278 } 4279 } 4280 4281 /* 4282 * Prepare copy of argv vector for target. 4283 */ 4284 target_argc = argc - optind; 4285 target_argv = calloc(target_argc + 1, sizeof (char *)); 4286 if (target_argv == NULL) { 4287 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 4288 exit(EXIT_FAILURE); 4289 } 4290 4291 /* 4292 * If argv0 is specified (using '-0' switch) we replace 4293 * argv[0] pointer with the given one. 4294 */ 4295 i = 0; 4296 if (argv0 != NULL) { 4297 target_argv[i++] = strdup(argv0); 4298 } 4299 for (; i < target_argc; i++) { 4300 target_argv[i] = strdup(argv[optind + i]); 4301 } 4302 target_argv[target_argc] = NULL; 4303 4304 ts = g_new0(TaskState, 1); 4305 init_task_state(ts); 4306 /* build Task State */ 4307 ts->info = info; 4308 ts->bprm = &bprm; 4309 cpu->opaque = ts; 4310 task_settid(ts); 4311 4312 execfd = qemu_getauxval(AT_EXECFD); 4313 if (execfd == 0) { 4314 execfd = open(filename, O_RDONLY); 4315 if (execfd < 0) { 4316 printf("Error while loading %s: %s\n", filename, strerror(errno)); 4317 _exit(EXIT_FAILURE); 4318 } 4319 } 4320 4321 ret = loader_exec(execfd, filename, target_argv, target_environ, regs, 4322 info, &bprm); 4323 if (ret != 0) { 4324 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 4325 _exit(EXIT_FAILURE); 4326 } 4327 4328 for (wrk = target_environ; *wrk; wrk++) { 4329 free(*wrk); 4330 } 4331 4332 free(target_environ); 4333 4334 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { 4335 qemu_log("guest_base 0x%lx\n", guest_base); 4336 log_page_dump(); 4337 4338 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 4339 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 4340 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 4341 info->start_code); 4342 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 4343 info->start_data); 4344 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 4345 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 4346 info->start_stack); 4347 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 4348 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 4349 } 4350 4351 target_set_brk(info->brk); 4352 syscall_init(); 4353 signal_init(); 4354 4355 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 4356 generating the prologue until now so that the prologue can take 4357 the real value of GUEST_BASE into account. */ 4358 tcg_prologue_init(&tcg_ctx); 4359 4360 #if defined(TARGET_I386) 4361 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 4362 env->hflags |= HF_PE_MASK | HF_CPL_MASK; 4363 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4364 env->cr[4] |= CR4_OSFXSR_MASK; 4365 env->hflags |= HF_OSFXSR_MASK; 4366 } 4367 #ifndef TARGET_ABI32 4368 /* enable 64 bit mode if possible */ 4369 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 4370 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 4371 exit(EXIT_FAILURE); 4372 } 4373 env->cr[4] |= CR4_PAE_MASK; 4374 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 4375 env->hflags |= HF_LMA_MASK; 4376 #endif 4377 4378 /* flags setup : we activate the IRQs by default as in user mode */ 4379 env->eflags |= IF_MASK; 4380 4381 /* linux register setup */ 4382 #ifndef TARGET_ABI32 4383 env->regs[R_EAX] = regs->rax; 4384 env->regs[R_EBX] = regs->rbx; 4385 env->regs[R_ECX] = regs->rcx; 4386 env->regs[R_EDX] = regs->rdx; 4387 env->regs[R_ESI] = regs->rsi; 4388 env->regs[R_EDI] = regs->rdi; 4389 env->regs[R_EBP] = regs->rbp; 4390 env->regs[R_ESP] = regs->rsp; 4391 env->eip = regs->rip; 4392 #else 4393 env->regs[R_EAX] = regs->eax; 4394 env->regs[R_EBX] = regs->ebx; 4395 env->regs[R_ECX] = regs->ecx; 4396 env->regs[R_EDX] = regs->edx; 4397 env->regs[R_ESI] = regs->esi; 4398 env->regs[R_EDI] = regs->edi; 4399 env->regs[R_EBP] = regs->ebp; 4400 env->regs[R_ESP] = regs->esp; 4401 env->eip = regs->eip; 4402 #endif 4403 4404 /* linux interrupt setup */ 4405 #ifndef TARGET_ABI32 4406 env->idt.limit = 511; 4407 #else 4408 env->idt.limit = 255; 4409 #endif 4410 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 4411 PROT_READ|PROT_WRITE, 4412 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4413 idt_table = g2h(env->idt.base); 4414 set_idt(0, 0); 4415 set_idt(1, 0); 4416 set_idt(2, 0); 4417 set_idt(3, 3); 4418 set_idt(4, 3); 4419 set_idt(5, 0); 4420 set_idt(6, 0); 4421 set_idt(7, 0); 4422 set_idt(8, 0); 4423 set_idt(9, 0); 4424 set_idt(10, 0); 4425 set_idt(11, 0); 4426 set_idt(12, 0); 4427 set_idt(13, 0); 4428 set_idt(14, 0); 4429 set_idt(15, 0); 4430 set_idt(16, 0); 4431 set_idt(17, 0); 4432 set_idt(18, 0); 4433 set_idt(19, 0); 4434 set_idt(0x80, 3); 4435 4436 /* linux segment setup */ 4437 { 4438 uint64_t *gdt_table; 4439 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 4440 PROT_READ|PROT_WRITE, 4441 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4442 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 4443 gdt_table = g2h(env->gdt.base); 4444 #ifdef TARGET_ABI32 4445 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4446 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4447 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4448 #else 4449 /* 64 bit code segment */ 4450 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4451 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4452 DESC_L_MASK | 4453 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4454 #endif 4455 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 4456 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4457 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 4458 } 4459 cpu_x86_load_seg(env, R_CS, __USER_CS); 4460 cpu_x86_load_seg(env, R_SS, __USER_DS); 4461 #ifdef TARGET_ABI32 4462 cpu_x86_load_seg(env, R_DS, __USER_DS); 4463 cpu_x86_load_seg(env, R_ES, __USER_DS); 4464 cpu_x86_load_seg(env, R_FS, __USER_DS); 4465 cpu_x86_load_seg(env, R_GS, __USER_DS); 4466 /* This hack makes Wine work... */ 4467 env->segs[R_FS].selector = 0; 4468 #else 4469 cpu_x86_load_seg(env, R_DS, 0); 4470 cpu_x86_load_seg(env, R_ES, 0); 4471 cpu_x86_load_seg(env, R_FS, 0); 4472 cpu_x86_load_seg(env, R_GS, 0); 4473 #endif 4474 #elif defined(TARGET_AARCH64) 4475 { 4476 int i; 4477 4478 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 4479 fprintf(stderr, 4480 "The selected ARM CPU does not support 64 bit mode\n"); 4481 exit(EXIT_FAILURE); 4482 } 4483 4484 for (i = 0; i < 31; i++) { 4485 env->xregs[i] = regs->regs[i]; 4486 } 4487 env->pc = regs->pc; 4488 env->xregs[31] = regs->sp; 4489 } 4490 #elif defined(TARGET_ARM) 4491 { 4492 int i; 4493 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, 4494 CPSRWriteByInstr); 4495 for(i = 0; i < 16; i++) { 4496 env->regs[i] = regs->uregs[i]; 4497 } 4498 #ifdef TARGET_WORDS_BIGENDIAN 4499 /* Enable BE8. */ 4500 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 4501 && (info->elf_flags & EF_ARM_BE8)) { 4502 env->uncached_cpsr |= CPSR_E; 4503 env->cp15.sctlr_el[1] |= SCTLR_E0E; 4504 } else { 4505 env->cp15.sctlr_el[1] |= SCTLR_B; 4506 } 4507 #endif 4508 } 4509 #elif defined(TARGET_UNICORE32) 4510 { 4511 int i; 4512 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 4513 for (i = 0; i < 32; i++) { 4514 env->regs[i] = regs->uregs[i]; 4515 } 4516 } 4517 #elif defined(TARGET_SPARC) 4518 { 4519 int i; 4520 env->pc = regs->pc; 4521 env->npc = regs->npc; 4522 env->y = regs->y; 4523 for(i = 0; i < 8; i++) 4524 env->gregs[i] = regs->u_regs[i]; 4525 for(i = 0; i < 8; i++) 4526 env->regwptr[i] = regs->u_regs[i + 8]; 4527 } 4528 #elif defined(TARGET_PPC) 4529 { 4530 int i; 4531 4532 #if defined(TARGET_PPC64) 4533 #if defined(TARGET_ABI32) 4534 env->msr &= ~((target_ulong)1 << MSR_SF); 4535 #else 4536 env->msr |= (target_ulong)1 << MSR_SF; 4537 #endif 4538 #endif 4539 env->nip = regs->nip; 4540 for(i = 0; i < 32; i++) { 4541 env->gpr[i] = regs->gpr[i]; 4542 } 4543 } 4544 #elif defined(TARGET_M68K) 4545 { 4546 env->pc = regs->pc; 4547 env->dregs[0] = regs->d0; 4548 env->dregs[1] = regs->d1; 4549 env->dregs[2] = regs->d2; 4550 env->dregs[3] = regs->d3; 4551 env->dregs[4] = regs->d4; 4552 env->dregs[5] = regs->d5; 4553 env->dregs[6] = regs->d6; 4554 env->dregs[7] = regs->d7; 4555 env->aregs[0] = regs->a0; 4556 env->aregs[1] = regs->a1; 4557 env->aregs[2] = regs->a2; 4558 env->aregs[3] = regs->a3; 4559 env->aregs[4] = regs->a4; 4560 env->aregs[5] = regs->a5; 4561 env->aregs[6] = regs->a6; 4562 env->aregs[7] = regs->usp; 4563 env->sr = regs->sr; 4564 ts->sim_syscalls = 1; 4565 } 4566 #elif defined(TARGET_MICROBLAZE) 4567 { 4568 env->regs[0] = regs->r0; 4569 env->regs[1] = regs->r1; 4570 env->regs[2] = regs->r2; 4571 env->regs[3] = regs->r3; 4572 env->regs[4] = regs->r4; 4573 env->regs[5] = regs->r5; 4574 env->regs[6] = regs->r6; 4575 env->regs[7] = regs->r7; 4576 env->regs[8] = regs->r8; 4577 env->regs[9] = regs->r9; 4578 env->regs[10] = regs->r10; 4579 env->regs[11] = regs->r11; 4580 env->regs[12] = regs->r12; 4581 env->regs[13] = regs->r13; 4582 env->regs[14] = regs->r14; 4583 env->regs[15] = regs->r15; 4584 env->regs[16] = regs->r16; 4585 env->regs[17] = regs->r17; 4586 env->regs[18] = regs->r18; 4587 env->regs[19] = regs->r19; 4588 env->regs[20] = regs->r20; 4589 env->regs[21] = regs->r21; 4590 env->regs[22] = regs->r22; 4591 env->regs[23] = regs->r23; 4592 env->regs[24] = regs->r24; 4593 env->regs[25] = regs->r25; 4594 env->regs[26] = regs->r26; 4595 env->regs[27] = regs->r27; 4596 env->regs[28] = regs->r28; 4597 env->regs[29] = regs->r29; 4598 env->regs[30] = regs->r30; 4599 env->regs[31] = regs->r31; 4600 env->sregs[SR_PC] = regs->pc; 4601 } 4602 #elif defined(TARGET_MIPS) 4603 { 4604 int i; 4605 4606 for(i = 0; i < 32; i++) { 4607 env->active_tc.gpr[i] = regs->regs[i]; 4608 } 4609 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 4610 if (regs->cp0_epc & 1) { 4611 env->hflags |= MIPS_HFLAG_M16; 4612 } 4613 } 4614 #elif defined(TARGET_OPENRISC) 4615 { 4616 int i; 4617 4618 for (i = 0; i < 32; i++) { 4619 env->gpr[i] = regs->gpr[i]; 4620 } 4621 4622 env->sr = regs->sr; 4623 env->pc = regs->pc; 4624 } 4625 #elif defined(TARGET_SH4) 4626 { 4627 int i; 4628 4629 for(i = 0; i < 16; i++) { 4630 env->gregs[i] = regs->regs[i]; 4631 } 4632 env->pc = regs->pc; 4633 } 4634 #elif defined(TARGET_ALPHA) 4635 { 4636 int i; 4637 4638 for(i = 0; i < 28; i++) { 4639 env->ir[i] = ((abi_ulong *)regs)[i]; 4640 } 4641 env->ir[IR_SP] = regs->usp; 4642 env->pc = regs->pc; 4643 } 4644 #elif defined(TARGET_CRIS) 4645 { 4646 env->regs[0] = regs->r0; 4647 env->regs[1] = regs->r1; 4648 env->regs[2] = regs->r2; 4649 env->regs[3] = regs->r3; 4650 env->regs[4] = regs->r4; 4651 env->regs[5] = regs->r5; 4652 env->regs[6] = regs->r6; 4653 env->regs[7] = regs->r7; 4654 env->regs[8] = regs->r8; 4655 env->regs[9] = regs->r9; 4656 env->regs[10] = regs->r10; 4657 env->regs[11] = regs->r11; 4658 env->regs[12] = regs->r12; 4659 env->regs[13] = regs->r13; 4660 env->regs[14] = info->start_stack; 4661 env->regs[15] = regs->acr; 4662 env->pc = regs->erp; 4663 } 4664 #elif defined(TARGET_S390X) 4665 { 4666 int i; 4667 for (i = 0; i < 16; i++) { 4668 env->regs[i] = regs->gprs[i]; 4669 } 4670 env->psw.mask = regs->psw.mask; 4671 env->psw.addr = regs->psw.addr; 4672 } 4673 #elif defined(TARGET_TILEGX) 4674 { 4675 int i; 4676 for (i = 0; i < TILEGX_R_COUNT; i++) { 4677 env->regs[i] = regs->regs[i]; 4678 } 4679 for (i = 0; i < TILEGX_SPR_COUNT; i++) { 4680 env->spregs[i] = 0; 4681 } 4682 env->pc = regs->pc; 4683 } 4684 #else 4685 #error unsupported target CPU 4686 #endif 4687 4688 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4689 ts->stack_base = info->start_stack; 4690 ts->heap_base = info->brk; 4691 /* This will be filled in on the first SYS_HEAPINFO call. */ 4692 ts->heap_limit = 0; 4693 #endif 4694 4695 if (gdbstub_port) { 4696 if (gdbserver_start(gdbstub_port) < 0) { 4697 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4698 gdbstub_port); 4699 exit(EXIT_FAILURE); 4700 } 4701 gdb_handlesig(cpu, 0); 4702 } 4703 cpu_loop(env); 4704 /* never exits */ 4705 return 0; 4706 } 4707