1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 #include <stdlib.h> 21 #include <stdio.h> 22 #include <stdarg.h> 23 #include <string.h> 24 #include <errno.h> 25 #include <unistd.h> 26 #include <sys/mman.h> 27 28 #include "qemu.h" 29 #include "qemu-common.h" 30 /* For tb_lock */ 31 #include "exec-all.h" 32 33 #define DEBUG_LOGFILE "/tmp/qemu.log" 34 35 static const char *interp_prefix = CONFIG_QEMU_PREFIX; 36 const char *qemu_uname_release = CONFIG_UNAME_RELEASE; 37 38 #if defined(__i386__) && !defined(CONFIG_STATIC) 39 /* Force usage of an ELF interpreter even if it is an ELF shared 40 object ! */ 41 const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2"; 42 #endif 43 44 /* for recent libc, we add these dummy symbols which are not declared 45 when generating a linked object (bug in ld ?) */ 46 #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC) 47 asm(".globl __preinit_array_start\n" 48 ".globl __preinit_array_end\n" 49 ".globl __init_array_start\n" 50 ".globl __init_array_end\n" 51 ".globl __fini_array_start\n" 52 ".globl __fini_array_end\n" 53 ".section \".rodata\"\n" 54 "__preinit_array_start:\n" 55 "__preinit_array_end:\n" 56 "__init_array_start:\n" 57 "__init_array_end:\n" 58 "__fini_array_start:\n" 59 "__fini_array_end:\n" 60 ".long 0\n" 61 ".previous\n"); 62 #endif 63 64 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 65 we allocate a bigger stack. Need a better solution, for example 66 by remapping the process stack directly at the right place */ 67 unsigned long x86_stack_size = 512 * 1024; 68 69 void gemu_log(const char *fmt, ...) 70 { 71 va_list ap; 72 73 va_start(ap, fmt); 74 vfprintf(stderr, fmt, ap); 75 va_end(ap); 76 } 77 78 void cpu_outb(CPUState *env, int addr, int val) 79 { 80 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val); 81 } 82 83 void cpu_outw(CPUState *env, int addr, int val) 84 { 85 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val); 86 } 87 88 void cpu_outl(CPUState *env, int addr, int val) 89 { 90 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val); 91 } 92 93 int cpu_inb(CPUState *env, int addr) 94 { 95 fprintf(stderr, "inb: port=0x%04x\n", addr); 96 return 0; 97 } 98 99 int cpu_inw(CPUState *env, int addr) 100 { 101 fprintf(stderr, "inw: port=0x%04x\n", addr); 102 return 0; 103 } 104 105 int cpu_inl(CPUState *env, int addr) 106 { 107 fprintf(stderr, "inl: port=0x%04x\n", addr); 108 return 0; 109 } 110 111 #if defined(TARGET_I386) 112 int cpu_get_pic_interrupt(CPUState *env) 113 { 114 return -1; 115 } 116 #endif 117 118 /* timers for rdtsc */ 119 120 #if 0 121 122 static uint64_t emu_time; 123 124 int64_t cpu_get_real_ticks(void) 125 { 126 return emu_time++; 127 } 128 129 #endif 130 131 #if defined(USE_NPTL) 132 /***********************************************************/ 133 /* Helper routines for implementing atomic operations. */ 134 135 /* To implement exclusive operations we force all cpus to syncronise. 136 We don't require a full sync, only that no cpus are executing guest code. 137 The alternative is to map target atomic ops onto host equivalents, 138 which requires quite a lot of per host/target work. */ 139 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 140 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 141 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 142 static int pending_cpus; 143 144 /* Make sure everything is in a consistent state for calling fork(). */ 145 void fork_start(void) 146 { 147 mmap_fork_start(); 148 pthread_mutex_lock(&tb_lock); 149 pthread_mutex_lock(&exclusive_lock); 150 } 151 152 void fork_end(int child) 153 { 154 if (child) { 155 /* Child processes created by fork() only have a single thread. 156 Discard information about the parent threads. */ 157 first_cpu = thread_env; 158 thread_env->next_cpu = NULL; 159 pending_cpus = 0; 160 pthread_mutex_init(&exclusive_lock, NULL); 161 pthread_cond_init(&exclusive_cond, NULL); 162 pthread_cond_init(&exclusive_resume, NULL); 163 pthread_mutex_init(&tb_lock, NULL); 164 } else { 165 pthread_mutex_unlock(&exclusive_lock); 166 pthread_mutex_unlock(&tb_lock); 167 } 168 mmap_fork_end(child); 169 } 170 171 /* Wait for pending exclusive operations to complete. The exclusive lock 172 must be held. */ 173 static inline void exclusive_idle(void) 174 { 175 while (pending_cpus) { 176 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 177 } 178 } 179 180 /* Start an exclusive operation. 181 Must only be called from outside cpu_arm_exec. */ 182 static inline void start_exclusive(void) 183 { 184 CPUState *other; 185 pthread_mutex_lock(&exclusive_lock); 186 exclusive_idle(); 187 188 pending_cpus = 1; 189 /* Make all other cpus stop executing. */ 190 for (other = first_cpu; other; other = other->next_cpu) { 191 if (other->running) { 192 pending_cpus++; 193 cpu_interrupt(other, CPU_INTERRUPT_EXIT); 194 } 195 } 196 if (pending_cpus > 1) { 197 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 198 } 199 } 200 201 /* Finish an exclusive operation. */ 202 static inline void end_exclusive(void) 203 { 204 pending_cpus = 0; 205 pthread_cond_broadcast(&exclusive_resume); 206 pthread_mutex_unlock(&exclusive_lock); 207 } 208 209 /* Wait for exclusive ops to finish, and begin cpu execution. */ 210 static inline void cpu_exec_start(CPUState *env) 211 { 212 pthread_mutex_lock(&exclusive_lock); 213 exclusive_idle(); 214 env->running = 1; 215 pthread_mutex_unlock(&exclusive_lock); 216 } 217 218 /* Mark cpu as not executing, and release pending exclusive ops. */ 219 static inline void cpu_exec_end(CPUState *env) 220 { 221 pthread_mutex_lock(&exclusive_lock); 222 env->running = 0; 223 if (pending_cpus > 1) { 224 pending_cpus--; 225 if (pending_cpus == 1) { 226 pthread_cond_signal(&exclusive_cond); 227 } 228 } 229 exclusive_idle(); 230 pthread_mutex_unlock(&exclusive_lock); 231 } 232 #else /* if !USE_NPTL */ 233 /* These are no-ops because we are not threadsafe. */ 234 static inline void cpu_exec_start(CPUState *env) 235 { 236 } 237 238 static inline void cpu_exec_end(CPUState *env) 239 { 240 } 241 242 static inline void start_exclusive(void) 243 { 244 } 245 246 static inline void end_exclusive(void) 247 { 248 } 249 250 void fork_start(void) 251 { 252 } 253 254 void fork_end(int child) 255 { 256 } 257 #endif 258 259 260 #ifdef TARGET_I386 261 /***********************************************************/ 262 /* CPUX86 core interface */ 263 264 void cpu_smm_update(CPUState *env) 265 { 266 } 267 268 uint64_t cpu_get_tsc(CPUX86State *env) 269 { 270 return cpu_get_real_ticks(); 271 } 272 273 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 274 int flags) 275 { 276 unsigned int e1, e2; 277 uint32_t *p; 278 e1 = (addr << 16) | (limit & 0xffff); 279 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 280 e2 |= flags; 281 p = ptr; 282 p[0] = tswap32(e1); 283 p[1] = tswap32(e2); 284 } 285 286 static uint64_t *idt_table; 287 #ifdef TARGET_X86_64 288 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 289 uint64_t addr, unsigned int sel) 290 { 291 uint32_t *p, e1, e2; 292 e1 = (addr & 0xffff) | (sel << 16); 293 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 294 p = ptr; 295 p[0] = tswap32(e1); 296 p[1] = tswap32(e2); 297 p[2] = tswap32(addr >> 32); 298 p[3] = 0; 299 } 300 /* only dpl matters as we do only user space emulation */ 301 static void set_idt(int n, unsigned int dpl) 302 { 303 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 304 } 305 #else 306 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 307 uint32_t addr, unsigned int sel) 308 { 309 uint32_t *p, e1, e2; 310 e1 = (addr & 0xffff) | (sel << 16); 311 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 312 p = ptr; 313 p[0] = tswap32(e1); 314 p[1] = tswap32(e2); 315 } 316 317 /* only dpl matters as we do only user space emulation */ 318 static void set_idt(int n, unsigned int dpl) 319 { 320 set_gate(idt_table + n, 0, dpl, 0, 0); 321 } 322 #endif 323 324 void cpu_loop(CPUX86State *env) 325 { 326 int trapnr; 327 abi_ulong pc; 328 target_siginfo_t info; 329 330 for(;;) { 331 trapnr = cpu_x86_exec(env); 332 switch(trapnr) { 333 case 0x80: 334 /* linux syscall from int $0x80 */ 335 env->regs[R_EAX] = do_syscall(env, 336 env->regs[R_EAX], 337 env->regs[R_EBX], 338 env->regs[R_ECX], 339 env->regs[R_EDX], 340 env->regs[R_ESI], 341 env->regs[R_EDI], 342 env->regs[R_EBP]); 343 break; 344 #ifndef TARGET_ABI32 345 case EXCP_SYSCALL: 346 /* linux syscall from syscall intruction */ 347 env->regs[R_EAX] = do_syscall(env, 348 env->regs[R_EAX], 349 env->regs[R_EDI], 350 env->regs[R_ESI], 351 env->regs[R_EDX], 352 env->regs[10], 353 env->regs[8], 354 env->regs[9]); 355 env->eip = env->exception_next_eip; 356 break; 357 #endif 358 case EXCP0B_NOSEG: 359 case EXCP0C_STACK: 360 info.si_signo = SIGBUS; 361 info.si_errno = 0; 362 info.si_code = TARGET_SI_KERNEL; 363 info._sifields._sigfault._addr = 0; 364 queue_signal(env, info.si_signo, &info); 365 break; 366 case EXCP0D_GPF: 367 /* XXX: potential problem if ABI32 */ 368 #ifndef TARGET_X86_64 369 if (env->eflags & VM_MASK) { 370 handle_vm86_fault(env); 371 } else 372 #endif 373 { 374 info.si_signo = SIGSEGV; 375 info.si_errno = 0; 376 info.si_code = TARGET_SI_KERNEL; 377 info._sifields._sigfault._addr = 0; 378 queue_signal(env, info.si_signo, &info); 379 } 380 break; 381 case EXCP0E_PAGE: 382 info.si_signo = SIGSEGV; 383 info.si_errno = 0; 384 if (!(env->error_code & 1)) 385 info.si_code = TARGET_SEGV_MAPERR; 386 else 387 info.si_code = TARGET_SEGV_ACCERR; 388 info._sifields._sigfault._addr = env->cr[2]; 389 queue_signal(env, info.si_signo, &info); 390 break; 391 case EXCP00_DIVZ: 392 #ifndef TARGET_X86_64 393 if (env->eflags & VM_MASK) { 394 handle_vm86_trap(env, trapnr); 395 } else 396 #endif 397 { 398 /* division by zero */ 399 info.si_signo = SIGFPE; 400 info.si_errno = 0; 401 info.si_code = TARGET_FPE_INTDIV; 402 info._sifields._sigfault._addr = env->eip; 403 queue_signal(env, info.si_signo, &info); 404 } 405 break; 406 case EXCP01_DB: 407 case EXCP03_INT3: 408 #ifndef TARGET_X86_64 409 if (env->eflags & VM_MASK) { 410 handle_vm86_trap(env, trapnr); 411 } else 412 #endif 413 { 414 info.si_signo = SIGTRAP; 415 info.si_errno = 0; 416 if (trapnr == EXCP01_DB) { 417 info.si_code = TARGET_TRAP_BRKPT; 418 info._sifields._sigfault._addr = env->eip; 419 } else { 420 info.si_code = TARGET_SI_KERNEL; 421 info._sifields._sigfault._addr = 0; 422 } 423 queue_signal(env, info.si_signo, &info); 424 } 425 break; 426 case EXCP04_INTO: 427 case EXCP05_BOUND: 428 #ifndef TARGET_X86_64 429 if (env->eflags & VM_MASK) { 430 handle_vm86_trap(env, trapnr); 431 } else 432 #endif 433 { 434 info.si_signo = SIGSEGV; 435 info.si_errno = 0; 436 info.si_code = TARGET_SI_KERNEL; 437 info._sifields._sigfault._addr = 0; 438 queue_signal(env, info.si_signo, &info); 439 } 440 break; 441 case EXCP06_ILLOP: 442 info.si_signo = SIGILL; 443 info.si_errno = 0; 444 info.si_code = TARGET_ILL_ILLOPN; 445 info._sifields._sigfault._addr = env->eip; 446 queue_signal(env, info.si_signo, &info); 447 break; 448 case EXCP_INTERRUPT: 449 /* just indicate that signals should be handled asap */ 450 break; 451 case EXCP_DEBUG: 452 { 453 int sig; 454 455 sig = gdb_handlesig (env, TARGET_SIGTRAP); 456 if (sig) 457 { 458 info.si_signo = sig; 459 info.si_errno = 0; 460 info.si_code = TARGET_TRAP_BRKPT; 461 queue_signal(env, info.si_signo, &info); 462 } 463 } 464 break; 465 default: 466 pc = env->segs[R_CS].base + env->eip; 467 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 468 (long)pc, trapnr); 469 abort(); 470 } 471 process_pending_signals(env); 472 } 473 } 474 #endif 475 476 #ifdef TARGET_ARM 477 478 static void arm_cache_flush(abi_ulong start, abi_ulong last) 479 { 480 abi_ulong addr, last1; 481 482 if (last < start) 483 return; 484 addr = start; 485 for(;;) { 486 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1; 487 if (last1 > last) 488 last1 = last; 489 tb_invalidate_page_range(addr, last1 + 1); 490 if (last1 == last) 491 break; 492 addr = last1 + 1; 493 } 494 } 495 496 /* Handle a jump to the kernel code page. */ 497 static int 498 do_kernel_trap(CPUARMState *env) 499 { 500 uint32_t addr; 501 uint32_t cpsr; 502 uint32_t val; 503 504 switch (env->regs[15]) { 505 case 0xffff0fa0: /* __kernel_memory_barrier */ 506 /* ??? No-op. Will need to do better for SMP. */ 507 break; 508 case 0xffff0fc0: /* __kernel_cmpxchg */ 509 /* XXX: This only works between threads, not between processes. 510 It's probably possible to implement this with native host 511 operations. However things like ldrex/strex are much harder so 512 there's not much point trying. */ 513 start_exclusive(); 514 cpsr = cpsr_read(env); 515 addr = env->regs[2]; 516 /* FIXME: This should SEGV if the access fails. */ 517 if (get_user_u32(val, addr)) 518 val = ~env->regs[0]; 519 if (val == env->regs[0]) { 520 val = env->regs[1]; 521 /* FIXME: Check for segfaults. */ 522 put_user_u32(val, addr); 523 env->regs[0] = 0; 524 cpsr |= CPSR_C; 525 } else { 526 env->regs[0] = -1; 527 cpsr &= ~CPSR_C; 528 } 529 cpsr_write(env, cpsr, CPSR_C); 530 end_exclusive(); 531 break; 532 case 0xffff0fe0: /* __kernel_get_tls */ 533 env->regs[0] = env->cp15.c13_tls2; 534 break; 535 default: 536 return 1; 537 } 538 /* Jump back to the caller. */ 539 addr = env->regs[14]; 540 if (addr & 1) { 541 env->thumb = 1; 542 addr &= ~1; 543 } 544 env->regs[15] = addr; 545 546 return 0; 547 } 548 549 void cpu_loop(CPUARMState *env) 550 { 551 int trapnr; 552 unsigned int n, insn; 553 target_siginfo_t info; 554 uint32_t addr; 555 556 for(;;) { 557 cpu_exec_start(env); 558 trapnr = cpu_arm_exec(env); 559 cpu_exec_end(env); 560 switch(trapnr) { 561 case EXCP_UDEF: 562 { 563 TaskState *ts = env->opaque; 564 uint32_t opcode; 565 int rc; 566 567 /* we handle the FPU emulation here, as Linux */ 568 /* we get the opcode */ 569 /* FIXME - what to do if get_user() fails? */ 570 get_user_u32(opcode, env->regs[15]); 571 572 rc = EmulateAll(opcode, &ts->fpa, env); 573 if (rc == 0) { /* illegal instruction */ 574 info.si_signo = SIGILL; 575 info.si_errno = 0; 576 info.si_code = TARGET_ILL_ILLOPN; 577 info._sifields._sigfault._addr = env->regs[15]; 578 queue_signal(env, info.si_signo, &info); 579 } else if (rc < 0) { /* FP exception */ 580 int arm_fpe=0; 581 582 /* translate softfloat flags to FPSR flags */ 583 if (-rc & float_flag_invalid) 584 arm_fpe |= BIT_IOC; 585 if (-rc & float_flag_divbyzero) 586 arm_fpe |= BIT_DZC; 587 if (-rc & float_flag_overflow) 588 arm_fpe |= BIT_OFC; 589 if (-rc & float_flag_underflow) 590 arm_fpe |= BIT_UFC; 591 if (-rc & float_flag_inexact) 592 arm_fpe |= BIT_IXC; 593 594 FPSR fpsr = ts->fpa.fpsr; 595 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 596 597 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 598 info.si_signo = SIGFPE; 599 info.si_errno = 0; 600 601 /* ordered by priority, least first */ 602 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 603 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 604 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 605 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 606 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 607 608 info._sifields._sigfault._addr = env->regs[15]; 609 queue_signal(env, info.si_signo, &info); 610 } else { 611 env->regs[15] += 4; 612 } 613 614 /* accumulate unenabled exceptions */ 615 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 616 fpsr |= BIT_IXC; 617 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 618 fpsr |= BIT_UFC; 619 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 620 fpsr |= BIT_OFC; 621 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 622 fpsr |= BIT_DZC; 623 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 624 fpsr |= BIT_IOC; 625 ts->fpa.fpsr=fpsr; 626 } else { /* everything OK */ 627 /* increment PC */ 628 env->regs[15] += 4; 629 } 630 } 631 break; 632 case EXCP_SWI: 633 case EXCP_BKPT: 634 { 635 env->eabi = 1; 636 /* system call */ 637 if (trapnr == EXCP_BKPT) { 638 if (env->thumb) { 639 /* FIXME - what to do if get_user() fails? */ 640 get_user_u16(insn, env->regs[15]); 641 n = insn & 0xff; 642 env->regs[15] += 2; 643 } else { 644 /* FIXME - what to do if get_user() fails? */ 645 get_user_u32(insn, env->regs[15]); 646 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 647 env->regs[15] += 4; 648 } 649 } else { 650 if (env->thumb) { 651 /* FIXME - what to do if get_user() fails? */ 652 get_user_u16(insn, env->regs[15] - 2); 653 n = insn & 0xff; 654 } else { 655 /* FIXME - what to do if get_user() fails? */ 656 get_user_u32(insn, env->regs[15] - 4); 657 n = insn & 0xffffff; 658 } 659 } 660 661 if (n == ARM_NR_cacheflush) { 662 arm_cache_flush(env->regs[0], env->regs[1]); 663 } else if (n == ARM_NR_semihosting 664 || n == ARM_NR_thumb_semihosting) { 665 env->regs[0] = do_arm_semihosting (env); 666 } else if (n == 0 || n >= ARM_SYSCALL_BASE 667 || (env->thumb && n == ARM_THUMB_SYSCALL)) { 668 /* linux syscall */ 669 if (env->thumb || n == 0) { 670 n = env->regs[7]; 671 } else { 672 n -= ARM_SYSCALL_BASE; 673 env->eabi = 0; 674 } 675 if ( n > ARM_NR_BASE) { 676 switch (n) { 677 case ARM_NR_cacheflush: 678 arm_cache_flush(env->regs[0], env->regs[1]); 679 break; 680 case ARM_NR_set_tls: 681 cpu_set_tls(env, env->regs[0]); 682 env->regs[0] = 0; 683 break; 684 default: 685 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 686 n); 687 env->regs[0] = -TARGET_ENOSYS; 688 break; 689 } 690 } else { 691 env->regs[0] = do_syscall(env, 692 n, 693 env->regs[0], 694 env->regs[1], 695 env->regs[2], 696 env->regs[3], 697 env->regs[4], 698 env->regs[5]); 699 } 700 } else { 701 goto error; 702 } 703 } 704 break; 705 case EXCP_INTERRUPT: 706 /* just indicate that signals should be handled asap */ 707 break; 708 case EXCP_PREFETCH_ABORT: 709 addr = env->cp15.c6_insn; 710 goto do_segv; 711 case EXCP_DATA_ABORT: 712 addr = env->cp15.c6_data; 713 goto do_segv; 714 do_segv: 715 { 716 info.si_signo = SIGSEGV; 717 info.si_errno = 0; 718 /* XXX: check env->error_code */ 719 info.si_code = TARGET_SEGV_MAPERR; 720 info._sifields._sigfault._addr = addr; 721 queue_signal(env, info.si_signo, &info); 722 } 723 break; 724 case EXCP_DEBUG: 725 { 726 int sig; 727 728 sig = gdb_handlesig (env, TARGET_SIGTRAP); 729 if (sig) 730 { 731 info.si_signo = sig; 732 info.si_errno = 0; 733 info.si_code = TARGET_TRAP_BRKPT; 734 queue_signal(env, info.si_signo, &info); 735 } 736 } 737 break; 738 case EXCP_KERNEL_TRAP: 739 if (do_kernel_trap(env)) 740 goto error; 741 break; 742 default: 743 error: 744 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 745 trapnr); 746 cpu_dump_state(env, stderr, fprintf, 0); 747 abort(); 748 } 749 process_pending_signals(env); 750 } 751 } 752 753 #endif 754 755 #ifdef TARGET_SPARC 756 #define SPARC64_STACK_BIAS 2047 757 758 //#define DEBUG_WIN 759 760 /* WARNING: dealing with register windows _is_ complicated. More info 761 can be found at http://www.sics.se/~psm/sparcstack.html */ 762 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 763 { 764 index = (index + cwp * 16) % (16 * env->nwindows); 765 /* wrap handling : if cwp is on the last window, then we use the 766 registers 'after' the end */ 767 if (index < 8 && env->cwp == env->nwindows - 1) 768 index += 16 * env->nwindows; 769 return index; 770 } 771 772 /* save the register window 'cwp1' */ 773 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 774 { 775 unsigned int i; 776 abi_ulong sp_ptr; 777 778 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 779 #ifdef TARGET_SPARC64 780 if (sp_ptr & 3) 781 sp_ptr += SPARC64_STACK_BIAS; 782 #endif 783 #if defined(DEBUG_WIN) 784 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 785 sp_ptr, cwp1); 786 #endif 787 for(i = 0; i < 16; i++) { 788 /* FIXME - what to do if put_user() fails? */ 789 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 790 sp_ptr += sizeof(abi_ulong); 791 } 792 } 793 794 static void save_window(CPUSPARCState *env) 795 { 796 #ifndef TARGET_SPARC64 797 unsigned int new_wim; 798 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 799 ((1LL << env->nwindows) - 1); 800 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 801 env->wim = new_wim; 802 #else 803 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 804 env->cansave++; 805 env->canrestore--; 806 #endif 807 } 808 809 static void restore_window(CPUSPARCState *env) 810 { 811 #ifndef TARGET_SPARC64 812 unsigned int new_wim; 813 #endif 814 unsigned int i, cwp1; 815 abi_ulong sp_ptr; 816 817 #ifndef TARGET_SPARC64 818 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 819 ((1LL << env->nwindows) - 1); 820 #endif 821 822 /* restore the invalid window */ 823 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 824 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 825 #ifdef TARGET_SPARC64 826 if (sp_ptr & 3) 827 sp_ptr += SPARC64_STACK_BIAS; 828 #endif 829 #if defined(DEBUG_WIN) 830 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 831 sp_ptr, cwp1); 832 #endif 833 for(i = 0; i < 16; i++) { 834 /* FIXME - what to do if get_user() fails? */ 835 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 836 sp_ptr += sizeof(abi_ulong); 837 } 838 #ifdef TARGET_SPARC64 839 env->canrestore++; 840 if (env->cleanwin < env->nwindows - 1) 841 env->cleanwin++; 842 env->cansave--; 843 #else 844 env->wim = new_wim; 845 #endif 846 } 847 848 static void flush_windows(CPUSPARCState *env) 849 { 850 int offset, cwp1; 851 852 offset = 1; 853 for(;;) { 854 /* if restore would invoke restore_window(), then we can stop */ 855 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 856 #ifndef TARGET_SPARC64 857 if (env->wim & (1 << cwp1)) 858 break; 859 #else 860 if (env->canrestore == 0) 861 break; 862 env->cansave++; 863 env->canrestore--; 864 #endif 865 save_window_offset(env, cwp1); 866 offset++; 867 } 868 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 869 #ifndef TARGET_SPARC64 870 /* set wim so that restore will reload the registers */ 871 env->wim = 1 << cwp1; 872 #endif 873 #if defined(DEBUG_WIN) 874 printf("flush_windows: nb=%d\n", offset - 1); 875 #endif 876 } 877 878 void cpu_loop (CPUSPARCState *env) 879 { 880 int trapnr, ret; 881 target_siginfo_t info; 882 883 while (1) { 884 trapnr = cpu_sparc_exec (env); 885 886 switch (trapnr) { 887 #ifndef TARGET_SPARC64 888 case 0x88: 889 case 0x90: 890 #else 891 case 0x110: 892 case 0x16d: 893 #endif 894 ret = do_syscall (env, env->gregs[1], 895 env->regwptr[0], env->regwptr[1], 896 env->regwptr[2], env->regwptr[3], 897 env->regwptr[4], env->regwptr[5]); 898 if ((unsigned int)ret >= (unsigned int)(-515)) { 899 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 900 env->xcc |= PSR_CARRY; 901 #else 902 env->psr |= PSR_CARRY; 903 #endif 904 ret = -ret; 905 } else { 906 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 907 env->xcc &= ~PSR_CARRY; 908 #else 909 env->psr &= ~PSR_CARRY; 910 #endif 911 } 912 env->regwptr[0] = ret; 913 /* next instruction */ 914 env->pc = env->npc; 915 env->npc = env->npc + 4; 916 break; 917 case 0x83: /* flush windows */ 918 #ifdef TARGET_ABI32 919 case 0x103: 920 #endif 921 flush_windows(env); 922 /* next instruction */ 923 env->pc = env->npc; 924 env->npc = env->npc + 4; 925 break; 926 #ifndef TARGET_SPARC64 927 case TT_WIN_OVF: /* window overflow */ 928 save_window(env); 929 break; 930 case TT_WIN_UNF: /* window underflow */ 931 restore_window(env); 932 break; 933 case TT_TFAULT: 934 case TT_DFAULT: 935 { 936 info.si_signo = SIGSEGV; 937 info.si_errno = 0; 938 /* XXX: check env->error_code */ 939 info.si_code = TARGET_SEGV_MAPERR; 940 info._sifields._sigfault._addr = env->mmuregs[4]; 941 queue_signal(env, info.si_signo, &info); 942 } 943 break; 944 #else 945 case TT_SPILL: /* window overflow */ 946 save_window(env); 947 break; 948 case TT_FILL: /* window underflow */ 949 restore_window(env); 950 break; 951 case TT_TFAULT: 952 case TT_DFAULT: 953 { 954 info.si_signo = SIGSEGV; 955 info.si_errno = 0; 956 /* XXX: check env->error_code */ 957 info.si_code = TARGET_SEGV_MAPERR; 958 if (trapnr == TT_DFAULT) 959 info._sifields._sigfault._addr = env->dmmuregs[4]; 960 else 961 info._sifields._sigfault._addr = env->tsptr->tpc; 962 queue_signal(env, info.si_signo, &info); 963 } 964 break; 965 #ifndef TARGET_ABI32 966 case 0x16e: 967 flush_windows(env); 968 sparc64_get_context(env); 969 break; 970 case 0x16f: 971 flush_windows(env); 972 sparc64_set_context(env); 973 break; 974 #endif 975 #endif 976 case EXCP_INTERRUPT: 977 /* just indicate that signals should be handled asap */ 978 break; 979 case EXCP_DEBUG: 980 { 981 int sig; 982 983 sig = gdb_handlesig (env, TARGET_SIGTRAP); 984 if (sig) 985 { 986 info.si_signo = sig; 987 info.si_errno = 0; 988 info.si_code = TARGET_TRAP_BRKPT; 989 queue_signal(env, info.si_signo, &info); 990 } 991 } 992 break; 993 default: 994 printf ("Unhandled trap: 0x%x\n", trapnr); 995 cpu_dump_state(env, stderr, fprintf, 0); 996 exit (1); 997 } 998 process_pending_signals (env); 999 } 1000 } 1001 1002 #endif 1003 1004 #ifdef TARGET_PPC 1005 static inline uint64_t cpu_ppc_get_tb (CPUState *env) 1006 { 1007 /* TO FIX */ 1008 return 0; 1009 } 1010 1011 uint32_t cpu_ppc_load_tbl (CPUState *env) 1012 { 1013 return cpu_ppc_get_tb(env) & 0xFFFFFFFF; 1014 } 1015 1016 uint32_t cpu_ppc_load_tbu (CPUState *env) 1017 { 1018 return cpu_ppc_get_tb(env) >> 32; 1019 } 1020 1021 uint32_t cpu_ppc_load_atbl (CPUState *env) 1022 { 1023 return cpu_ppc_get_tb(env) & 0xFFFFFFFF; 1024 } 1025 1026 uint32_t cpu_ppc_load_atbu (CPUState *env) 1027 { 1028 return cpu_ppc_get_tb(env) >> 32; 1029 } 1030 1031 uint32_t cpu_ppc601_load_rtcu (CPUState *env) 1032 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1033 1034 uint32_t cpu_ppc601_load_rtcl (CPUState *env) 1035 { 1036 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1037 } 1038 1039 /* XXX: to be fixed */ 1040 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) 1041 { 1042 return -1; 1043 } 1044 1045 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) 1046 { 1047 return -1; 1048 } 1049 1050 #define EXCP_DUMP(env, fmt, args...) \ 1051 do { \ 1052 fprintf(stderr, fmt , ##args); \ 1053 cpu_dump_state(env, stderr, fprintf, 0); \ 1054 if (loglevel != 0) { \ 1055 fprintf(logfile, fmt , ##args); \ 1056 cpu_dump_state(env, logfile, fprintf, 0); \ 1057 } \ 1058 } while (0) 1059 1060 void cpu_loop(CPUPPCState *env) 1061 { 1062 target_siginfo_t info; 1063 int trapnr; 1064 uint32_t ret; 1065 1066 for(;;) { 1067 trapnr = cpu_ppc_exec(env); 1068 switch(trapnr) { 1069 case POWERPC_EXCP_NONE: 1070 /* Just go on */ 1071 break; 1072 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1073 cpu_abort(env, "Critical interrupt while in user mode. " 1074 "Aborting\n"); 1075 break; 1076 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1077 cpu_abort(env, "Machine check exception while in user mode. " 1078 "Aborting\n"); 1079 break; 1080 case POWERPC_EXCP_DSI: /* Data storage exception */ 1081 EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n", 1082 env->spr[SPR_DAR]); 1083 /* XXX: check this. Seems bugged */ 1084 switch (env->error_code & 0xFF000000) { 1085 case 0x40000000: 1086 info.si_signo = TARGET_SIGSEGV; 1087 info.si_errno = 0; 1088 info.si_code = TARGET_SEGV_MAPERR; 1089 break; 1090 case 0x04000000: 1091 info.si_signo = TARGET_SIGILL; 1092 info.si_errno = 0; 1093 info.si_code = TARGET_ILL_ILLADR; 1094 break; 1095 case 0x08000000: 1096 info.si_signo = TARGET_SIGSEGV; 1097 info.si_errno = 0; 1098 info.si_code = TARGET_SEGV_ACCERR; 1099 break; 1100 default: 1101 /* Let's send a regular segfault... */ 1102 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1103 env->error_code); 1104 info.si_signo = TARGET_SIGSEGV; 1105 info.si_errno = 0; 1106 info.si_code = TARGET_SEGV_MAPERR; 1107 break; 1108 } 1109 info._sifields._sigfault._addr = env->nip; 1110 queue_signal(env, info.si_signo, &info); 1111 break; 1112 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1113 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n", 1114 env->spr[SPR_SRR0]); 1115 /* XXX: check this */ 1116 switch (env->error_code & 0xFF000000) { 1117 case 0x40000000: 1118 info.si_signo = TARGET_SIGSEGV; 1119 info.si_errno = 0; 1120 info.si_code = TARGET_SEGV_MAPERR; 1121 break; 1122 case 0x10000000: 1123 case 0x08000000: 1124 info.si_signo = TARGET_SIGSEGV; 1125 info.si_errno = 0; 1126 info.si_code = TARGET_SEGV_ACCERR; 1127 break; 1128 default: 1129 /* Let's send a regular segfault... */ 1130 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1131 env->error_code); 1132 info.si_signo = TARGET_SIGSEGV; 1133 info.si_errno = 0; 1134 info.si_code = TARGET_SEGV_MAPERR; 1135 break; 1136 } 1137 info._sifields._sigfault._addr = env->nip - 4; 1138 queue_signal(env, info.si_signo, &info); 1139 break; 1140 case POWERPC_EXCP_EXTERNAL: /* External input */ 1141 cpu_abort(env, "External interrupt while in user mode. " 1142 "Aborting\n"); 1143 break; 1144 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1145 EXCP_DUMP(env, "Unaligned memory access\n"); 1146 /* XXX: check this */ 1147 info.si_signo = TARGET_SIGBUS; 1148 info.si_errno = 0; 1149 info.si_code = TARGET_BUS_ADRALN; 1150 info._sifields._sigfault._addr = env->nip - 4; 1151 queue_signal(env, info.si_signo, &info); 1152 break; 1153 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1154 /* XXX: check this */ 1155 switch (env->error_code & ~0xF) { 1156 case POWERPC_EXCP_FP: 1157 EXCP_DUMP(env, "Floating point program exception\n"); 1158 info.si_signo = TARGET_SIGFPE; 1159 info.si_errno = 0; 1160 switch (env->error_code & 0xF) { 1161 case POWERPC_EXCP_FP_OX: 1162 info.si_code = TARGET_FPE_FLTOVF; 1163 break; 1164 case POWERPC_EXCP_FP_UX: 1165 info.si_code = TARGET_FPE_FLTUND; 1166 break; 1167 case POWERPC_EXCP_FP_ZX: 1168 case POWERPC_EXCP_FP_VXZDZ: 1169 info.si_code = TARGET_FPE_FLTDIV; 1170 break; 1171 case POWERPC_EXCP_FP_XX: 1172 info.si_code = TARGET_FPE_FLTRES; 1173 break; 1174 case POWERPC_EXCP_FP_VXSOFT: 1175 info.si_code = TARGET_FPE_FLTINV; 1176 break; 1177 case POWERPC_EXCP_FP_VXSNAN: 1178 case POWERPC_EXCP_FP_VXISI: 1179 case POWERPC_EXCP_FP_VXIDI: 1180 case POWERPC_EXCP_FP_VXIMZ: 1181 case POWERPC_EXCP_FP_VXVC: 1182 case POWERPC_EXCP_FP_VXSQRT: 1183 case POWERPC_EXCP_FP_VXCVI: 1184 info.si_code = TARGET_FPE_FLTSUB; 1185 break; 1186 default: 1187 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1188 env->error_code); 1189 break; 1190 } 1191 break; 1192 case POWERPC_EXCP_INVAL: 1193 EXCP_DUMP(env, "Invalid instruction\n"); 1194 info.si_signo = TARGET_SIGILL; 1195 info.si_errno = 0; 1196 switch (env->error_code & 0xF) { 1197 case POWERPC_EXCP_INVAL_INVAL: 1198 info.si_code = TARGET_ILL_ILLOPC; 1199 break; 1200 case POWERPC_EXCP_INVAL_LSWX: 1201 info.si_code = TARGET_ILL_ILLOPN; 1202 break; 1203 case POWERPC_EXCP_INVAL_SPR: 1204 info.si_code = TARGET_ILL_PRVREG; 1205 break; 1206 case POWERPC_EXCP_INVAL_FP: 1207 info.si_code = TARGET_ILL_COPROC; 1208 break; 1209 default: 1210 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1211 env->error_code & 0xF); 1212 info.si_code = TARGET_ILL_ILLADR; 1213 break; 1214 } 1215 break; 1216 case POWERPC_EXCP_PRIV: 1217 EXCP_DUMP(env, "Privilege violation\n"); 1218 info.si_signo = TARGET_SIGILL; 1219 info.si_errno = 0; 1220 switch (env->error_code & 0xF) { 1221 case POWERPC_EXCP_PRIV_OPC: 1222 info.si_code = TARGET_ILL_PRVOPC; 1223 break; 1224 case POWERPC_EXCP_PRIV_REG: 1225 info.si_code = TARGET_ILL_PRVREG; 1226 break; 1227 default: 1228 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1229 env->error_code & 0xF); 1230 info.si_code = TARGET_ILL_PRVOPC; 1231 break; 1232 } 1233 break; 1234 case POWERPC_EXCP_TRAP: 1235 cpu_abort(env, "Tried to call a TRAP\n"); 1236 break; 1237 default: 1238 /* Should not happen ! */ 1239 cpu_abort(env, "Unknown program exception (%02x)\n", 1240 env->error_code); 1241 break; 1242 } 1243 info._sifields._sigfault._addr = env->nip - 4; 1244 queue_signal(env, info.si_signo, &info); 1245 break; 1246 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1247 EXCP_DUMP(env, "No floating point allowed\n"); 1248 info.si_signo = TARGET_SIGILL; 1249 info.si_errno = 0; 1250 info.si_code = TARGET_ILL_COPROC; 1251 info._sifields._sigfault._addr = env->nip - 4; 1252 queue_signal(env, info.si_signo, &info); 1253 break; 1254 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1255 cpu_abort(env, "Syscall exception while in user mode. " 1256 "Aborting\n"); 1257 break; 1258 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1259 EXCP_DUMP(env, "No APU instruction allowed\n"); 1260 info.si_signo = TARGET_SIGILL; 1261 info.si_errno = 0; 1262 info.si_code = TARGET_ILL_COPROC; 1263 info._sifields._sigfault._addr = env->nip - 4; 1264 queue_signal(env, info.si_signo, &info); 1265 break; 1266 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1267 cpu_abort(env, "Decrementer interrupt while in user mode. " 1268 "Aborting\n"); 1269 break; 1270 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1271 cpu_abort(env, "Fix interval timer interrupt while in user mode. " 1272 "Aborting\n"); 1273 break; 1274 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1275 cpu_abort(env, "Watchdog timer interrupt while in user mode. " 1276 "Aborting\n"); 1277 break; 1278 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1279 cpu_abort(env, "Data TLB exception while in user mode. " 1280 "Aborting\n"); 1281 break; 1282 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1283 cpu_abort(env, "Instruction TLB exception while in user mode. " 1284 "Aborting\n"); 1285 break; 1286 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1287 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1288 info.si_signo = TARGET_SIGILL; 1289 info.si_errno = 0; 1290 info.si_code = TARGET_ILL_COPROC; 1291 info._sifields._sigfault._addr = env->nip - 4; 1292 queue_signal(env, info.si_signo, &info); 1293 break; 1294 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1295 cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); 1296 break; 1297 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1298 cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); 1299 break; 1300 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1301 cpu_abort(env, "Performance monitor exception not handled\n"); 1302 break; 1303 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1304 cpu_abort(env, "Doorbell interrupt while in user mode. " 1305 "Aborting\n"); 1306 break; 1307 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1308 cpu_abort(env, "Doorbell critical interrupt while in user mode. " 1309 "Aborting\n"); 1310 break; 1311 case POWERPC_EXCP_RESET: /* System reset exception */ 1312 cpu_abort(env, "Reset interrupt while in user mode. " 1313 "Aborting\n"); 1314 break; 1315 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1316 cpu_abort(env, "Data segment exception while in user mode. " 1317 "Aborting\n"); 1318 break; 1319 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1320 cpu_abort(env, "Instruction segment exception " 1321 "while in user mode. Aborting\n"); 1322 break; 1323 /* PowerPC 64 with hypervisor mode support */ 1324 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1325 cpu_abort(env, "Hypervisor decrementer interrupt " 1326 "while in user mode. Aborting\n"); 1327 break; 1328 case POWERPC_EXCP_TRACE: /* Trace exception */ 1329 /* Nothing to do: 1330 * we use this exception to emulate step-by-step execution mode. 1331 */ 1332 break; 1333 /* PowerPC 64 with hypervisor mode support */ 1334 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1335 cpu_abort(env, "Hypervisor data storage exception " 1336 "while in user mode. Aborting\n"); 1337 break; 1338 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1339 cpu_abort(env, "Hypervisor instruction storage exception " 1340 "while in user mode. Aborting\n"); 1341 break; 1342 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1343 cpu_abort(env, "Hypervisor data segment exception " 1344 "while in user mode. Aborting\n"); 1345 break; 1346 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1347 cpu_abort(env, "Hypervisor instruction segment exception " 1348 "while in user mode. Aborting\n"); 1349 break; 1350 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1351 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1352 info.si_signo = TARGET_SIGILL; 1353 info.si_errno = 0; 1354 info.si_code = TARGET_ILL_COPROC; 1355 info._sifields._sigfault._addr = env->nip - 4; 1356 queue_signal(env, info.si_signo, &info); 1357 break; 1358 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1359 cpu_abort(env, "Programable interval timer interrupt " 1360 "while in user mode. Aborting\n"); 1361 break; 1362 case POWERPC_EXCP_IO: /* IO error exception */ 1363 cpu_abort(env, "IO error exception while in user mode. " 1364 "Aborting\n"); 1365 break; 1366 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1367 cpu_abort(env, "Run mode exception while in user mode. " 1368 "Aborting\n"); 1369 break; 1370 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1371 cpu_abort(env, "Emulation trap exception not handled\n"); 1372 break; 1373 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1374 cpu_abort(env, "Instruction fetch TLB exception " 1375 "while in user-mode. Aborting"); 1376 break; 1377 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1378 cpu_abort(env, "Data load TLB exception while in user-mode. " 1379 "Aborting"); 1380 break; 1381 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1382 cpu_abort(env, "Data store TLB exception while in user-mode. " 1383 "Aborting"); 1384 break; 1385 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1386 cpu_abort(env, "Floating-point assist exception not handled\n"); 1387 break; 1388 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1389 cpu_abort(env, "Instruction address breakpoint exception " 1390 "not handled\n"); 1391 break; 1392 case POWERPC_EXCP_SMI: /* System management interrupt */ 1393 cpu_abort(env, "System management interrupt while in user mode. " 1394 "Aborting\n"); 1395 break; 1396 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1397 cpu_abort(env, "Thermal interrupt interrupt while in user mode. " 1398 "Aborting\n"); 1399 break; 1400 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1401 cpu_abort(env, "Performance monitor exception not handled\n"); 1402 break; 1403 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1404 cpu_abort(env, "Vector assist exception not handled\n"); 1405 break; 1406 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1407 cpu_abort(env, "Soft patch exception not handled\n"); 1408 break; 1409 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1410 cpu_abort(env, "Maintenance exception while in user mode. " 1411 "Aborting\n"); 1412 break; 1413 case POWERPC_EXCP_STOP: /* stop translation */ 1414 /* We did invalidate the instruction cache. Go on */ 1415 break; 1416 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1417 /* We just stopped because of a branch. Go on */ 1418 break; 1419 case POWERPC_EXCP_SYSCALL_USER: 1420 /* system call in user-mode emulation */ 1421 /* WARNING: 1422 * PPC ABI uses overflow flag in cr0 to signal an error 1423 * in syscalls. 1424 */ 1425 #if 0 1426 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0], 1427 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]); 1428 #endif 1429 env->crf[0] &= ~0x1; 1430 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1431 env->gpr[5], env->gpr[6], env->gpr[7], 1432 env->gpr[8]); 1433 if (ret > (uint32_t)(-515)) { 1434 env->crf[0] |= 0x1; 1435 ret = -ret; 1436 } 1437 env->gpr[3] = ret; 1438 #if 0 1439 printf("syscall returned 0x%08x (%d)\n", ret, ret); 1440 #endif 1441 break; 1442 case EXCP_DEBUG: 1443 { 1444 int sig; 1445 1446 sig = gdb_handlesig(env, TARGET_SIGTRAP); 1447 if (sig) { 1448 info.si_signo = sig; 1449 info.si_errno = 0; 1450 info.si_code = TARGET_TRAP_BRKPT; 1451 queue_signal(env, info.si_signo, &info); 1452 } 1453 } 1454 break; 1455 case EXCP_INTERRUPT: 1456 /* just indicate that signals should be handled asap */ 1457 break; 1458 default: 1459 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); 1460 break; 1461 } 1462 process_pending_signals(env); 1463 } 1464 } 1465 #endif 1466 1467 #ifdef TARGET_MIPS 1468 1469 #define MIPS_SYS(name, args) args, 1470 1471 static const uint8_t mips_syscall_args[] = { 1472 MIPS_SYS(sys_syscall , 0) /* 4000 */ 1473 MIPS_SYS(sys_exit , 1) 1474 MIPS_SYS(sys_fork , 0) 1475 MIPS_SYS(sys_read , 3) 1476 MIPS_SYS(sys_write , 3) 1477 MIPS_SYS(sys_open , 3) /* 4005 */ 1478 MIPS_SYS(sys_close , 1) 1479 MIPS_SYS(sys_waitpid , 3) 1480 MIPS_SYS(sys_creat , 2) 1481 MIPS_SYS(sys_link , 2) 1482 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1483 MIPS_SYS(sys_execve , 0) 1484 MIPS_SYS(sys_chdir , 1) 1485 MIPS_SYS(sys_time , 1) 1486 MIPS_SYS(sys_mknod , 3) 1487 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1488 MIPS_SYS(sys_lchown , 3) 1489 MIPS_SYS(sys_ni_syscall , 0) 1490 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1491 MIPS_SYS(sys_lseek , 3) 1492 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1493 MIPS_SYS(sys_mount , 5) 1494 MIPS_SYS(sys_oldumount , 1) 1495 MIPS_SYS(sys_setuid , 1) 1496 MIPS_SYS(sys_getuid , 0) 1497 MIPS_SYS(sys_stime , 1) /* 4025 */ 1498 MIPS_SYS(sys_ptrace , 4) 1499 MIPS_SYS(sys_alarm , 1) 1500 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1501 MIPS_SYS(sys_pause , 0) 1502 MIPS_SYS(sys_utime , 2) /* 4030 */ 1503 MIPS_SYS(sys_ni_syscall , 0) 1504 MIPS_SYS(sys_ni_syscall , 0) 1505 MIPS_SYS(sys_access , 2) 1506 MIPS_SYS(sys_nice , 1) 1507 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 1508 MIPS_SYS(sys_sync , 0) 1509 MIPS_SYS(sys_kill , 2) 1510 MIPS_SYS(sys_rename , 2) 1511 MIPS_SYS(sys_mkdir , 2) 1512 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 1513 MIPS_SYS(sys_dup , 1) 1514 MIPS_SYS(sys_pipe , 0) 1515 MIPS_SYS(sys_times , 1) 1516 MIPS_SYS(sys_ni_syscall , 0) 1517 MIPS_SYS(sys_brk , 1) /* 4045 */ 1518 MIPS_SYS(sys_setgid , 1) 1519 MIPS_SYS(sys_getgid , 0) 1520 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 1521 MIPS_SYS(sys_geteuid , 0) 1522 MIPS_SYS(sys_getegid , 0) /* 4050 */ 1523 MIPS_SYS(sys_acct , 0) 1524 MIPS_SYS(sys_umount , 2) 1525 MIPS_SYS(sys_ni_syscall , 0) 1526 MIPS_SYS(sys_ioctl , 3) 1527 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 1528 MIPS_SYS(sys_ni_syscall , 2) 1529 MIPS_SYS(sys_setpgid , 2) 1530 MIPS_SYS(sys_ni_syscall , 0) 1531 MIPS_SYS(sys_olduname , 1) 1532 MIPS_SYS(sys_umask , 1) /* 4060 */ 1533 MIPS_SYS(sys_chroot , 1) 1534 MIPS_SYS(sys_ustat , 2) 1535 MIPS_SYS(sys_dup2 , 2) 1536 MIPS_SYS(sys_getppid , 0) 1537 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 1538 MIPS_SYS(sys_setsid , 0) 1539 MIPS_SYS(sys_sigaction , 3) 1540 MIPS_SYS(sys_sgetmask , 0) 1541 MIPS_SYS(sys_ssetmask , 1) 1542 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 1543 MIPS_SYS(sys_setregid , 2) 1544 MIPS_SYS(sys_sigsuspend , 0) 1545 MIPS_SYS(sys_sigpending , 1) 1546 MIPS_SYS(sys_sethostname , 2) 1547 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 1548 MIPS_SYS(sys_getrlimit , 2) 1549 MIPS_SYS(sys_getrusage , 2) 1550 MIPS_SYS(sys_gettimeofday, 2) 1551 MIPS_SYS(sys_settimeofday, 2) 1552 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 1553 MIPS_SYS(sys_setgroups , 2) 1554 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 1555 MIPS_SYS(sys_symlink , 2) 1556 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 1557 MIPS_SYS(sys_readlink , 3) /* 4085 */ 1558 MIPS_SYS(sys_uselib , 1) 1559 MIPS_SYS(sys_swapon , 2) 1560 MIPS_SYS(sys_reboot , 3) 1561 MIPS_SYS(old_readdir , 3) 1562 MIPS_SYS(old_mmap , 6) /* 4090 */ 1563 MIPS_SYS(sys_munmap , 2) 1564 MIPS_SYS(sys_truncate , 2) 1565 MIPS_SYS(sys_ftruncate , 2) 1566 MIPS_SYS(sys_fchmod , 2) 1567 MIPS_SYS(sys_fchown , 3) /* 4095 */ 1568 MIPS_SYS(sys_getpriority , 2) 1569 MIPS_SYS(sys_setpriority , 3) 1570 MIPS_SYS(sys_ni_syscall , 0) 1571 MIPS_SYS(sys_statfs , 2) 1572 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 1573 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 1574 MIPS_SYS(sys_socketcall , 2) 1575 MIPS_SYS(sys_syslog , 3) 1576 MIPS_SYS(sys_setitimer , 3) 1577 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 1578 MIPS_SYS(sys_newstat , 2) 1579 MIPS_SYS(sys_newlstat , 2) 1580 MIPS_SYS(sys_newfstat , 2) 1581 MIPS_SYS(sys_uname , 1) 1582 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 1583 MIPS_SYS(sys_vhangup , 0) 1584 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 1585 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 1586 MIPS_SYS(sys_wait4 , 4) 1587 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 1588 MIPS_SYS(sys_sysinfo , 1) 1589 MIPS_SYS(sys_ipc , 6) 1590 MIPS_SYS(sys_fsync , 1) 1591 MIPS_SYS(sys_sigreturn , 0) 1592 MIPS_SYS(sys_clone , 0) /* 4120 */ 1593 MIPS_SYS(sys_setdomainname, 2) 1594 MIPS_SYS(sys_newuname , 1) 1595 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 1596 MIPS_SYS(sys_adjtimex , 1) 1597 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 1598 MIPS_SYS(sys_sigprocmask , 3) 1599 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 1600 MIPS_SYS(sys_init_module , 5) 1601 MIPS_SYS(sys_delete_module, 1) 1602 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 1603 MIPS_SYS(sys_quotactl , 0) 1604 MIPS_SYS(sys_getpgid , 1) 1605 MIPS_SYS(sys_fchdir , 1) 1606 MIPS_SYS(sys_bdflush , 2) 1607 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 1608 MIPS_SYS(sys_personality , 1) 1609 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 1610 MIPS_SYS(sys_setfsuid , 1) 1611 MIPS_SYS(sys_setfsgid , 1) 1612 MIPS_SYS(sys_llseek , 5) /* 4140 */ 1613 MIPS_SYS(sys_getdents , 3) 1614 MIPS_SYS(sys_select , 5) 1615 MIPS_SYS(sys_flock , 2) 1616 MIPS_SYS(sys_msync , 3) 1617 MIPS_SYS(sys_readv , 3) /* 4145 */ 1618 MIPS_SYS(sys_writev , 3) 1619 MIPS_SYS(sys_cacheflush , 3) 1620 MIPS_SYS(sys_cachectl , 3) 1621 MIPS_SYS(sys_sysmips , 4) 1622 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 1623 MIPS_SYS(sys_getsid , 1) 1624 MIPS_SYS(sys_fdatasync , 0) 1625 MIPS_SYS(sys_sysctl , 1) 1626 MIPS_SYS(sys_mlock , 2) 1627 MIPS_SYS(sys_munlock , 2) /* 4155 */ 1628 MIPS_SYS(sys_mlockall , 1) 1629 MIPS_SYS(sys_munlockall , 0) 1630 MIPS_SYS(sys_sched_setparam, 2) 1631 MIPS_SYS(sys_sched_getparam, 2) 1632 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 1633 MIPS_SYS(sys_sched_getscheduler, 1) 1634 MIPS_SYS(sys_sched_yield , 0) 1635 MIPS_SYS(sys_sched_get_priority_max, 1) 1636 MIPS_SYS(sys_sched_get_priority_min, 1) 1637 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 1638 MIPS_SYS(sys_nanosleep, 2) 1639 MIPS_SYS(sys_mremap , 4) 1640 MIPS_SYS(sys_accept , 3) 1641 MIPS_SYS(sys_bind , 3) 1642 MIPS_SYS(sys_connect , 3) /* 4170 */ 1643 MIPS_SYS(sys_getpeername , 3) 1644 MIPS_SYS(sys_getsockname , 3) 1645 MIPS_SYS(sys_getsockopt , 5) 1646 MIPS_SYS(sys_listen , 2) 1647 MIPS_SYS(sys_recv , 4) /* 4175 */ 1648 MIPS_SYS(sys_recvfrom , 6) 1649 MIPS_SYS(sys_recvmsg , 3) 1650 MIPS_SYS(sys_send , 4) 1651 MIPS_SYS(sys_sendmsg , 3) 1652 MIPS_SYS(sys_sendto , 6) /* 4180 */ 1653 MIPS_SYS(sys_setsockopt , 5) 1654 MIPS_SYS(sys_shutdown , 2) 1655 MIPS_SYS(sys_socket , 3) 1656 MIPS_SYS(sys_socketpair , 4) 1657 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 1658 MIPS_SYS(sys_getresuid , 3) 1659 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 1660 MIPS_SYS(sys_poll , 3) 1661 MIPS_SYS(sys_nfsservctl , 3) 1662 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 1663 MIPS_SYS(sys_getresgid , 3) 1664 MIPS_SYS(sys_prctl , 5) 1665 MIPS_SYS(sys_rt_sigreturn, 0) 1666 MIPS_SYS(sys_rt_sigaction, 4) 1667 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 1668 MIPS_SYS(sys_rt_sigpending, 2) 1669 MIPS_SYS(sys_rt_sigtimedwait, 4) 1670 MIPS_SYS(sys_rt_sigqueueinfo, 3) 1671 MIPS_SYS(sys_rt_sigsuspend, 0) 1672 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 1673 MIPS_SYS(sys_pwrite64 , 6) 1674 MIPS_SYS(sys_chown , 3) 1675 MIPS_SYS(sys_getcwd , 2) 1676 MIPS_SYS(sys_capget , 2) 1677 MIPS_SYS(sys_capset , 2) /* 4205 */ 1678 MIPS_SYS(sys_sigaltstack , 0) 1679 MIPS_SYS(sys_sendfile , 4) 1680 MIPS_SYS(sys_ni_syscall , 0) 1681 MIPS_SYS(sys_ni_syscall , 0) 1682 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 1683 MIPS_SYS(sys_truncate64 , 4) 1684 MIPS_SYS(sys_ftruncate64 , 4) 1685 MIPS_SYS(sys_stat64 , 2) 1686 MIPS_SYS(sys_lstat64 , 2) 1687 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 1688 MIPS_SYS(sys_pivot_root , 2) 1689 MIPS_SYS(sys_mincore , 3) 1690 MIPS_SYS(sys_madvise , 3) 1691 MIPS_SYS(sys_getdents64 , 3) 1692 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 1693 MIPS_SYS(sys_ni_syscall , 0) 1694 MIPS_SYS(sys_gettid , 0) 1695 MIPS_SYS(sys_readahead , 5) 1696 MIPS_SYS(sys_setxattr , 5) 1697 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 1698 MIPS_SYS(sys_fsetxattr , 5) 1699 MIPS_SYS(sys_getxattr , 4) 1700 MIPS_SYS(sys_lgetxattr , 4) 1701 MIPS_SYS(sys_fgetxattr , 4) 1702 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 1703 MIPS_SYS(sys_llistxattr , 3) 1704 MIPS_SYS(sys_flistxattr , 3) 1705 MIPS_SYS(sys_removexattr , 2) 1706 MIPS_SYS(sys_lremovexattr, 2) 1707 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 1708 MIPS_SYS(sys_tkill , 2) 1709 MIPS_SYS(sys_sendfile64 , 5) 1710 MIPS_SYS(sys_futex , 2) 1711 MIPS_SYS(sys_sched_setaffinity, 3) 1712 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 1713 MIPS_SYS(sys_io_setup , 2) 1714 MIPS_SYS(sys_io_destroy , 1) 1715 MIPS_SYS(sys_io_getevents, 5) 1716 MIPS_SYS(sys_io_submit , 3) 1717 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 1718 MIPS_SYS(sys_exit_group , 1) 1719 MIPS_SYS(sys_lookup_dcookie, 3) 1720 MIPS_SYS(sys_epoll_create, 1) 1721 MIPS_SYS(sys_epoll_ctl , 4) 1722 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 1723 MIPS_SYS(sys_remap_file_pages, 5) 1724 MIPS_SYS(sys_set_tid_address, 1) 1725 MIPS_SYS(sys_restart_syscall, 0) 1726 MIPS_SYS(sys_fadvise64_64, 7) 1727 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 1728 MIPS_SYS(sys_fstatfs64 , 2) 1729 MIPS_SYS(sys_timer_create, 3) 1730 MIPS_SYS(sys_timer_settime, 4) 1731 MIPS_SYS(sys_timer_gettime, 2) 1732 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 1733 MIPS_SYS(sys_timer_delete, 1) 1734 MIPS_SYS(sys_clock_settime, 2) 1735 MIPS_SYS(sys_clock_gettime, 2) 1736 MIPS_SYS(sys_clock_getres, 2) 1737 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 1738 MIPS_SYS(sys_tgkill , 3) 1739 MIPS_SYS(sys_utimes , 2) 1740 MIPS_SYS(sys_mbind , 4) 1741 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 1742 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 1743 MIPS_SYS(sys_mq_open , 4) 1744 MIPS_SYS(sys_mq_unlink , 1) 1745 MIPS_SYS(sys_mq_timedsend, 5) 1746 MIPS_SYS(sys_mq_timedreceive, 5) 1747 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 1748 MIPS_SYS(sys_mq_getsetattr, 3) 1749 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 1750 MIPS_SYS(sys_waitid , 4) 1751 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 1752 MIPS_SYS(sys_add_key , 5) 1753 MIPS_SYS(sys_request_key, 4) 1754 MIPS_SYS(sys_keyctl , 5) 1755 MIPS_SYS(sys_set_thread_area, 1) 1756 MIPS_SYS(sys_inotify_init, 0) 1757 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 1758 MIPS_SYS(sys_inotify_rm_watch, 2) 1759 MIPS_SYS(sys_migrate_pages, 4) 1760 MIPS_SYS(sys_openat, 4) 1761 MIPS_SYS(sys_mkdirat, 3) 1762 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 1763 MIPS_SYS(sys_fchownat, 5) 1764 MIPS_SYS(sys_futimesat, 3) 1765 MIPS_SYS(sys_fstatat64, 4) 1766 MIPS_SYS(sys_unlinkat, 3) 1767 MIPS_SYS(sys_renameat, 4) /* 4295 */ 1768 MIPS_SYS(sys_linkat, 5) 1769 MIPS_SYS(sys_symlinkat, 3) 1770 MIPS_SYS(sys_readlinkat, 4) 1771 MIPS_SYS(sys_fchmodat, 3) 1772 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 1773 MIPS_SYS(sys_pselect6, 6) 1774 MIPS_SYS(sys_ppoll, 5) 1775 MIPS_SYS(sys_unshare, 1) 1776 MIPS_SYS(sys_splice, 4) 1777 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 1778 MIPS_SYS(sys_tee, 4) 1779 MIPS_SYS(sys_vmsplice, 4) 1780 MIPS_SYS(sys_move_pages, 6) 1781 MIPS_SYS(sys_set_robust_list, 2) 1782 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 1783 MIPS_SYS(sys_kexec_load, 4) 1784 MIPS_SYS(sys_getcpu, 3) 1785 MIPS_SYS(sys_epoll_pwait, 6) 1786 MIPS_SYS(sys_ioprio_set, 3) 1787 MIPS_SYS(sys_ioprio_get, 2) 1788 }; 1789 1790 #undef MIPS_SYS 1791 1792 void cpu_loop(CPUMIPSState *env) 1793 { 1794 target_siginfo_t info; 1795 int trapnr, ret; 1796 unsigned int syscall_num; 1797 1798 for(;;) { 1799 trapnr = cpu_mips_exec(env); 1800 switch(trapnr) { 1801 case EXCP_SYSCALL: 1802 syscall_num = env->active_tc.gpr[2] - 4000; 1803 env->active_tc.PC += 4; 1804 if (syscall_num >= sizeof(mips_syscall_args)) { 1805 ret = -ENOSYS; 1806 } else { 1807 int nb_args; 1808 abi_ulong sp_reg; 1809 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 1810 1811 nb_args = mips_syscall_args[syscall_num]; 1812 sp_reg = env->active_tc.gpr[29]; 1813 switch (nb_args) { 1814 /* these arguments are taken from the stack */ 1815 /* FIXME - what to do if get_user() fails? */ 1816 case 8: get_user_ual(arg8, sp_reg + 28); 1817 case 7: get_user_ual(arg7, sp_reg + 24); 1818 case 6: get_user_ual(arg6, sp_reg + 20); 1819 case 5: get_user_ual(arg5, sp_reg + 16); 1820 default: 1821 break; 1822 } 1823 ret = do_syscall(env, env->active_tc.gpr[2], 1824 env->active_tc.gpr[4], 1825 env->active_tc.gpr[5], 1826 env->active_tc.gpr[6], 1827 env->active_tc.gpr[7], 1828 arg5, arg6/*, arg7, arg8*/); 1829 } 1830 if ((unsigned int)ret >= (unsigned int)(-1133)) { 1831 env->active_tc.gpr[7] = 1; /* error flag */ 1832 ret = -ret; 1833 } else { 1834 env->active_tc.gpr[7] = 0; /* error flag */ 1835 } 1836 env->active_tc.gpr[2] = ret; 1837 break; 1838 case EXCP_TLBL: 1839 case EXCP_TLBS: 1840 case EXCP_CpU: 1841 case EXCP_RI: 1842 info.si_signo = TARGET_SIGILL; 1843 info.si_errno = 0; 1844 info.si_code = 0; 1845 queue_signal(env, info.si_signo, &info); 1846 break; 1847 case EXCP_INTERRUPT: 1848 /* just indicate that signals should be handled asap */ 1849 break; 1850 case EXCP_DEBUG: 1851 { 1852 int sig; 1853 1854 sig = gdb_handlesig (env, TARGET_SIGTRAP); 1855 if (sig) 1856 { 1857 info.si_signo = sig; 1858 info.si_errno = 0; 1859 info.si_code = TARGET_TRAP_BRKPT; 1860 queue_signal(env, info.si_signo, &info); 1861 } 1862 } 1863 break; 1864 default: 1865 // error: 1866 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 1867 trapnr); 1868 cpu_dump_state(env, stderr, fprintf, 0); 1869 abort(); 1870 } 1871 process_pending_signals(env); 1872 } 1873 } 1874 #endif 1875 1876 #ifdef TARGET_SH4 1877 void cpu_loop (CPUState *env) 1878 { 1879 int trapnr, ret; 1880 target_siginfo_t info; 1881 1882 while (1) { 1883 trapnr = cpu_sh4_exec (env); 1884 1885 switch (trapnr) { 1886 case 0x160: 1887 env->pc += 2; 1888 ret = do_syscall(env, 1889 env->gregs[3], 1890 env->gregs[4], 1891 env->gregs[5], 1892 env->gregs[6], 1893 env->gregs[7], 1894 env->gregs[0], 1895 env->gregs[1]); 1896 env->gregs[0] = ret; 1897 break; 1898 case EXCP_INTERRUPT: 1899 /* just indicate that signals should be handled asap */ 1900 break; 1901 case EXCP_DEBUG: 1902 { 1903 int sig; 1904 1905 sig = gdb_handlesig (env, TARGET_SIGTRAP); 1906 if (sig) 1907 { 1908 info.si_signo = sig; 1909 info.si_errno = 0; 1910 info.si_code = TARGET_TRAP_BRKPT; 1911 queue_signal(env, info.si_signo, &info); 1912 } 1913 } 1914 break; 1915 case 0xa0: 1916 case 0xc0: 1917 info.si_signo = SIGSEGV; 1918 info.si_errno = 0; 1919 info.si_code = TARGET_SEGV_MAPERR; 1920 info._sifields._sigfault._addr = env->tea; 1921 queue_signal(env, info.si_signo, &info); 1922 break; 1923 1924 default: 1925 printf ("Unhandled trap: 0x%x\n", trapnr); 1926 cpu_dump_state(env, stderr, fprintf, 0); 1927 exit (1); 1928 } 1929 process_pending_signals (env); 1930 } 1931 } 1932 #endif 1933 1934 #ifdef TARGET_CRIS 1935 void cpu_loop (CPUState *env) 1936 { 1937 int trapnr, ret; 1938 target_siginfo_t info; 1939 1940 while (1) { 1941 trapnr = cpu_cris_exec (env); 1942 switch (trapnr) { 1943 case 0xaa: 1944 { 1945 info.si_signo = SIGSEGV; 1946 info.si_errno = 0; 1947 /* XXX: check env->error_code */ 1948 info.si_code = TARGET_SEGV_MAPERR; 1949 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 1950 queue_signal(env, info.si_signo, &info); 1951 } 1952 break; 1953 case EXCP_INTERRUPT: 1954 /* just indicate that signals should be handled asap */ 1955 break; 1956 case EXCP_BREAK: 1957 ret = do_syscall(env, 1958 env->regs[9], 1959 env->regs[10], 1960 env->regs[11], 1961 env->regs[12], 1962 env->regs[13], 1963 env->pregs[7], 1964 env->pregs[11]); 1965 env->regs[10] = ret; 1966 break; 1967 case EXCP_DEBUG: 1968 { 1969 int sig; 1970 1971 sig = gdb_handlesig (env, TARGET_SIGTRAP); 1972 if (sig) 1973 { 1974 info.si_signo = sig; 1975 info.si_errno = 0; 1976 info.si_code = TARGET_TRAP_BRKPT; 1977 queue_signal(env, info.si_signo, &info); 1978 } 1979 } 1980 break; 1981 default: 1982 printf ("Unhandled trap: 0x%x\n", trapnr); 1983 cpu_dump_state(env, stderr, fprintf, 0); 1984 exit (1); 1985 } 1986 process_pending_signals (env); 1987 } 1988 } 1989 #endif 1990 1991 #ifdef TARGET_M68K 1992 1993 void cpu_loop(CPUM68KState *env) 1994 { 1995 int trapnr; 1996 unsigned int n; 1997 target_siginfo_t info; 1998 TaskState *ts = env->opaque; 1999 2000 for(;;) { 2001 trapnr = cpu_m68k_exec(env); 2002 switch(trapnr) { 2003 case EXCP_ILLEGAL: 2004 { 2005 if (ts->sim_syscalls) { 2006 uint16_t nr; 2007 nr = lduw(env->pc + 2); 2008 env->pc += 4; 2009 do_m68k_simcall(env, nr); 2010 } else { 2011 goto do_sigill; 2012 } 2013 } 2014 break; 2015 case EXCP_HALT_INSN: 2016 /* Semihosing syscall. */ 2017 env->pc += 4; 2018 do_m68k_semihosting(env, env->dregs[0]); 2019 break; 2020 case EXCP_LINEA: 2021 case EXCP_LINEF: 2022 case EXCP_UNSUPPORTED: 2023 do_sigill: 2024 info.si_signo = SIGILL; 2025 info.si_errno = 0; 2026 info.si_code = TARGET_ILL_ILLOPN; 2027 info._sifields._sigfault._addr = env->pc; 2028 queue_signal(env, info.si_signo, &info); 2029 break; 2030 case EXCP_TRAP0: 2031 { 2032 ts->sim_syscalls = 0; 2033 n = env->dregs[0]; 2034 env->pc += 2; 2035 env->dregs[0] = do_syscall(env, 2036 n, 2037 env->dregs[1], 2038 env->dregs[2], 2039 env->dregs[3], 2040 env->dregs[4], 2041 env->dregs[5], 2042 env->aregs[0]); 2043 } 2044 break; 2045 case EXCP_INTERRUPT: 2046 /* just indicate that signals should be handled asap */ 2047 break; 2048 case EXCP_ACCESS: 2049 { 2050 info.si_signo = SIGSEGV; 2051 info.si_errno = 0; 2052 /* XXX: check env->error_code */ 2053 info.si_code = TARGET_SEGV_MAPERR; 2054 info._sifields._sigfault._addr = env->mmu.ar; 2055 queue_signal(env, info.si_signo, &info); 2056 } 2057 break; 2058 case EXCP_DEBUG: 2059 { 2060 int sig; 2061 2062 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2063 if (sig) 2064 { 2065 info.si_signo = sig; 2066 info.si_errno = 0; 2067 info.si_code = TARGET_TRAP_BRKPT; 2068 queue_signal(env, info.si_signo, &info); 2069 } 2070 } 2071 break; 2072 default: 2073 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2074 trapnr); 2075 cpu_dump_state(env, stderr, fprintf, 0); 2076 abort(); 2077 } 2078 process_pending_signals(env); 2079 } 2080 } 2081 #endif /* TARGET_M68K */ 2082 2083 #ifdef TARGET_ALPHA 2084 void cpu_loop (CPUState *env) 2085 { 2086 int trapnr; 2087 target_siginfo_t info; 2088 2089 while (1) { 2090 trapnr = cpu_alpha_exec (env); 2091 2092 switch (trapnr) { 2093 case EXCP_RESET: 2094 fprintf(stderr, "Reset requested. Exit\n"); 2095 exit(1); 2096 break; 2097 case EXCP_MCHK: 2098 fprintf(stderr, "Machine check exception. Exit\n"); 2099 exit(1); 2100 break; 2101 case EXCP_ARITH: 2102 fprintf(stderr, "Arithmetic trap.\n"); 2103 exit(1); 2104 break; 2105 case EXCP_HW_INTERRUPT: 2106 fprintf(stderr, "External interrupt. Exit\n"); 2107 exit(1); 2108 break; 2109 case EXCP_DFAULT: 2110 fprintf(stderr, "MMU data fault\n"); 2111 exit(1); 2112 break; 2113 case EXCP_DTB_MISS_PAL: 2114 fprintf(stderr, "MMU data TLB miss in PALcode\n"); 2115 exit(1); 2116 break; 2117 case EXCP_ITB_MISS: 2118 fprintf(stderr, "MMU instruction TLB miss\n"); 2119 exit(1); 2120 break; 2121 case EXCP_ITB_ACV: 2122 fprintf(stderr, "MMU instruction access violation\n"); 2123 exit(1); 2124 break; 2125 case EXCP_DTB_MISS_NATIVE: 2126 fprintf(stderr, "MMU data TLB miss\n"); 2127 exit(1); 2128 break; 2129 case EXCP_UNALIGN: 2130 fprintf(stderr, "Unaligned access\n"); 2131 exit(1); 2132 break; 2133 case EXCP_OPCDEC: 2134 fprintf(stderr, "Invalid instruction\n"); 2135 exit(1); 2136 break; 2137 case EXCP_FEN: 2138 fprintf(stderr, "Floating-point not allowed\n"); 2139 exit(1); 2140 break; 2141 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1): 2142 call_pal(env, (trapnr >> 6) | 0x80); 2143 break; 2144 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1): 2145 fprintf(stderr, "Privileged call to PALcode\n"); 2146 exit(1); 2147 break; 2148 case EXCP_DEBUG: 2149 { 2150 int sig; 2151 2152 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2153 if (sig) 2154 { 2155 info.si_signo = sig; 2156 info.si_errno = 0; 2157 info.si_code = TARGET_TRAP_BRKPT; 2158 queue_signal(env, info.si_signo, &info); 2159 } 2160 } 2161 break; 2162 default: 2163 printf ("Unhandled trap: 0x%x\n", trapnr); 2164 cpu_dump_state(env, stderr, fprintf, 0); 2165 exit (1); 2166 } 2167 process_pending_signals (env); 2168 } 2169 } 2170 #endif /* TARGET_ALPHA */ 2171 2172 static void usage(void) 2173 { 2174 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n" 2175 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n" 2176 "Linux CPU emulator (compiled for %s emulation)\n" 2177 "\n" 2178 "Standard options:\n" 2179 "-h print this help\n" 2180 "-g port wait gdb connection to port\n" 2181 "-L path set the elf interpreter prefix (default=%s)\n" 2182 "-s size set the stack size in bytes (default=%ld)\n" 2183 "-cpu model select CPU (-cpu ? for list)\n" 2184 "-drop-ld-preload drop LD_PRELOAD for target process\n" 2185 "\n" 2186 "Debug options:\n" 2187 "-d options activate log (logfile=%s)\n" 2188 "-p pagesize set the host page size to 'pagesize'\n" 2189 "-strace log system calls\n" 2190 "\n" 2191 "Environment variables:\n" 2192 "QEMU_STRACE Print system calls and arguments similar to the\n" 2193 " 'strace' program. Enable by setting to any value.\n" 2194 , 2195 TARGET_ARCH, 2196 interp_prefix, 2197 x86_stack_size, 2198 DEBUG_LOGFILE); 2199 _exit(1); 2200 } 2201 2202 THREAD CPUState *thread_env; 2203 2204 /* Assumes contents are already zeroed. */ 2205 void init_task_state(TaskState *ts) 2206 { 2207 int i; 2208 2209 ts->used = 1; 2210 ts->first_free = ts->sigqueue_table; 2211 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 2212 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 2213 } 2214 ts->sigqueue_table[i].next = NULL; 2215 } 2216 2217 int main(int argc, char **argv) 2218 { 2219 const char *filename; 2220 const char *cpu_model; 2221 struct target_pt_regs regs1, *regs = ®s1; 2222 struct image_info info1, *info = &info1; 2223 TaskState ts1, *ts = &ts1; 2224 CPUState *env; 2225 int optind; 2226 const char *r; 2227 int gdbstub_port = 0; 2228 int drop_ld_preload = 0, environ_count = 0; 2229 char **target_environ, **wrk, **dst; 2230 2231 if (argc <= 1) 2232 usage(); 2233 2234 /* init debug */ 2235 cpu_set_log_filename(DEBUG_LOGFILE); 2236 2237 cpu_model = NULL; 2238 optind = 1; 2239 for(;;) { 2240 if (optind >= argc) 2241 break; 2242 r = argv[optind]; 2243 if (r[0] != '-') 2244 break; 2245 optind++; 2246 r++; 2247 if (!strcmp(r, "-")) { 2248 break; 2249 } else if (!strcmp(r, "d")) { 2250 int mask; 2251 const CPULogItem *item; 2252 2253 if (optind >= argc) 2254 break; 2255 2256 r = argv[optind++]; 2257 mask = cpu_str_to_log_mask(r); 2258 if (!mask) { 2259 printf("Log items (comma separated):\n"); 2260 for(item = cpu_log_items; item->mask != 0; item++) { 2261 printf("%-10s %s\n", item->name, item->help); 2262 } 2263 exit(1); 2264 } 2265 cpu_set_log(mask); 2266 } else if (!strcmp(r, "s")) { 2267 r = argv[optind++]; 2268 x86_stack_size = strtol(r, (char **)&r, 0); 2269 if (x86_stack_size <= 0) 2270 usage(); 2271 if (*r == 'M') 2272 x86_stack_size *= 1024 * 1024; 2273 else if (*r == 'k' || *r == 'K') 2274 x86_stack_size *= 1024; 2275 } else if (!strcmp(r, "L")) { 2276 interp_prefix = argv[optind++]; 2277 } else if (!strcmp(r, "p")) { 2278 qemu_host_page_size = atoi(argv[optind++]); 2279 if (qemu_host_page_size == 0 || 2280 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 2281 fprintf(stderr, "page size must be a power of two\n"); 2282 exit(1); 2283 } 2284 } else if (!strcmp(r, "g")) { 2285 gdbstub_port = atoi(argv[optind++]); 2286 } else if (!strcmp(r, "r")) { 2287 qemu_uname_release = argv[optind++]; 2288 } else if (!strcmp(r, "cpu")) { 2289 cpu_model = argv[optind++]; 2290 if (strcmp(cpu_model, "?") == 0) { 2291 /* XXX: implement xxx_cpu_list for targets that still miss it */ 2292 #if defined(cpu_list) 2293 cpu_list(stdout, &fprintf); 2294 #endif 2295 _exit(1); 2296 } 2297 } else if (!strcmp(r, "drop-ld-preload")) { 2298 drop_ld_preload = 1; 2299 } else if (!strcmp(r, "strace")) { 2300 do_strace = 1; 2301 } else 2302 { 2303 usage(); 2304 } 2305 } 2306 if (optind >= argc) 2307 usage(); 2308 filename = argv[optind]; 2309 2310 /* Zero out regs */ 2311 memset(regs, 0, sizeof(struct target_pt_regs)); 2312 2313 /* Zero out image_info */ 2314 memset(info, 0, sizeof(struct image_info)); 2315 2316 /* Scan interp_prefix dir for replacement files. */ 2317 init_paths(interp_prefix); 2318 2319 if (cpu_model == NULL) { 2320 #if defined(TARGET_I386) 2321 #ifdef TARGET_X86_64 2322 cpu_model = "qemu64"; 2323 #else 2324 cpu_model = "qemu32"; 2325 #endif 2326 #elif defined(TARGET_ARM) 2327 cpu_model = "arm926"; 2328 #elif defined(TARGET_M68K) 2329 cpu_model = "any"; 2330 #elif defined(TARGET_SPARC) 2331 #ifdef TARGET_SPARC64 2332 cpu_model = "TI UltraSparc II"; 2333 #else 2334 cpu_model = "Fujitsu MB86904"; 2335 #endif 2336 #elif defined(TARGET_MIPS) 2337 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 2338 cpu_model = "20Kc"; 2339 #else 2340 cpu_model = "24Kf"; 2341 #endif 2342 #elif defined(TARGET_PPC) 2343 #ifdef TARGET_PPC64 2344 cpu_model = "970"; 2345 #else 2346 cpu_model = "750"; 2347 #endif 2348 #else 2349 cpu_model = "any"; 2350 #endif 2351 } 2352 cpu_exec_init_all(0); 2353 /* NOTE: we need to init the CPU at this stage to get 2354 qemu_host_page_size */ 2355 env = cpu_init(cpu_model); 2356 if (!env) { 2357 fprintf(stderr, "Unable to find CPU definition\n"); 2358 exit(1); 2359 } 2360 thread_env = env; 2361 2362 if (getenv("QEMU_STRACE")) { 2363 do_strace = 1; 2364 } 2365 2366 wrk = environ; 2367 while (*(wrk++)) 2368 environ_count++; 2369 2370 target_environ = malloc((environ_count + 1) * sizeof(char *)); 2371 if (!target_environ) 2372 abort(); 2373 for (wrk = environ, dst = target_environ; *wrk; wrk++) { 2374 if (drop_ld_preload && !strncmp(*wrk, "LD_PRELOAD=", 11)) 2375 continue; 2376 *(dst++) = strdup(*wrk); 2377 } 2378 *dst = NULL; /* NULL terminate target_environ */ 2379 2380 if (loader_exec(filename, argv+optind, target_environ, regs, info) != 0) { 2381 printf("Error loading %s\n", filename); 2382 _exit(1); 2383 } 2384 2385 for (wrk = target_environ; *wrk; wrk++) { 2386 free(*wrk); 2387 } 2388 2389 free(target_environ); 2390 2391 if (loglevel) { 2392 page_dump(logfile); 2393 2394 fprintf(logfile, "start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 2395 fprintf(logfile, "end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 2396 fprintf(logfile, "start_code 0x" TARGET_ABI_FMT_lx "\n", 2397 info->start_code); 2398 fprintf(logfile, "start_data 0x" TARGET_ABI_FMT_lx "\n", 2399 info->start_data); 2400 fprintf(logfile, "end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 2401 fprintf(logfile, "start_stack 0x" TARGET_ABI_FMT_lx "\n", 2402 info->start_stack); 2403 fprintf(logfile, "brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 2404 fprintf(logfile, "entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 2405 } 2406 2407 target_set_brk(info->brk); 2408 syscall_init(); 2409 signal_init(); 2410 2411 /* build Task State */ 2412 memset(ts, 0, sizeof(TaskState)); 2413 init_task_state(ts); 2414 ts->info = info; 2415 env->opaque = ts; 2416 env->user_mode_only = 1; 2417 2418 #if defined(TARGET_I386) 2419 cpu_x86_set_cpl(env, 3); 2420 2421 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 2422 env->hflags |= HF_PE_MASK; 2423 if (env->cpuid_features & CPUID_SSE) { 2424 env->cr[4] |= CR4_OSFXSR_MASK; 2425 env->hflags |= HF_OSFXSR_MASK; 2426 } 2427 #ifndef TARGET_ABI32 2428 /* enable 64 bit mode if possible */ 2429 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) { 2430 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 2431 exit(1); 2432 } 2433 env->cr[4] |= CR4_PAE_MASK; 2434 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 2435 env->hflags |= HF_LMA_MASK; 2436 #endif 2437 2438 /* flags setup : we activate the IRQs by default as in user mode */ 2439 env->eflags |= IF_MASK; 2440 2441 /* linux register setup */ 2442 #ifndef TARGET_ABI32 2443 env->regs[R_EAX] = regs->rax; 2444 env->regs[R_EBX] = regs->rbx; 2445 env->regs[R_ECX] = regs->rcx; 2446 env->regs[R_EDX] = regs->rdx; 2447 env->regs[R_ESI] = regs->rsi; 2448 env->regs[R_EDI] = regs->rdi; 2449 env->regs[R_EBP] = regs->rbp; 2450 env->regs[R_ESP] = regs->rsp; 2451 env->eip = regs->rip; 2452 #else 2453 env->regs[R_EAX] = regs->eax; 2454 env->regs[R_EBX] = regs->ebx; 2455 env->regs[R_ECX] = regs->ecx; 2456 env->regs[R_EDX] = regs->edx; 2457 env->regs[R_ESI] = regs->esi; 2458 env->regs[R_EDI] = regs->edi; 2459 env->regs[R_EBP] = regs->ebp; 2460 env->regs[R_ESP] = regs->esp; 2461 env->eip = regs->eip; 2462 #endif 2463 2464 /* linux interrupt setup */ 2465 #ifndef TARGET_ABI32 2466 env->idt.limit = 511; 2467 #else 2468 env->idt.limit = 255; 2469 #endif 2470 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 2471 PROT_READ|PROT_WRITE, 2472 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 2473 idt_table = g2h(env->idt.base); 2474 set_idt(0, 0); 2475 set_idt(1, 0); 2476 set_idt(2, 0); 2477 set_idt(3, 3); 2478 set_idt(4, 3); 2479 set_idt(5, 0); 2480 set_idt(6, 0); 2481 set_idt(7, 0); 2482 set_idt(8, 0); 2483 set_idt(9, 0); 2484 set_idt(10, 0); 2485 set_idt(11, 0); 2486 set_idt(12, 0); 2487 set_idt(13, 0); 2488 set_idt(14, 0); 2489 set_idt(15, 0); 2490 set_idt(16, 0); 2491 set_idt(17, 0); 2492 set_idt(18, 0); 2493 set_idt(19, 0); 2494 set_idt(0x80, 3); 2495 2496 /* linux segment setup */ 2497 { 2498 uint64_t *gdt_table; 2499 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 2500 PROT_READ|PROT_WRITE, 2501 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 2502 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 2503 gdt_table = g2h(env->gdt.base); 2504 #ifdef TARGET_ABI32 2505 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 2506 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 2507 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 2508 #else 2509 /* 64 bit code segment */ 2510 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 2511 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 2512 DESC_L_MASK | 2513 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 2514 #endif 2515 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 2516 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 2517 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 2518 } 2519 cpu_x86_load_seg(env, R_CS, __USER_CS); 2520 cpu_x86_load_seg(env, R_SS, __USER_DS); 2521 #ifdef TARGET_ABI32 2522 cpu_x86_load_seg(env, R_DS, __USER_DS); 2523 cpu_x86_load_seg(env, R_ES, __USER_DS); 2524 cpu_x86_load_seg(env, R_FS, __USER_DS); 2525 cpu_x86_load_seg(env, R_GS, __USER_DS); 2526 /* This hack makes Wine work... */ 2527 env->segs[R_FS].selector = 0; 2528 #else 2529 cpu_x86_load_seg(env, R_DS, 0); 2530 cpu_x86_load_seg(env, R_ES, 0); 2531 cpu_x86_load_seg(env, R_FS, 0); 2532 cpu_x86_load_seg(env, R_GS, 0); 2533 #endif 2534 #elif defined(TARGET_ARM) 2535 { 2536 int i; 2537 cpsr_write(env, regs->uregs[16], 0xffffffff); 2538 for(i = 0; i < 16; i++) { 2539 env->regs[i] = regs->uregs[i]; 2540 } 2541 } 2542 #elif defined(TARGET_SPARC) 2543 { 2544 int i; 2545 env->pc = regs->pc; 2546 env->npc = regs->npc; 2547 env->y = regs->y; 2548 for(i = 0; i < 8; i++) 2549 env->gregs[i] = regs->u_regs[i]; 2550 for(i = 0; i < 8; i++) 2551 env->regwptr[i] = regs->u_regs[i + 8]; 2552 } 2553 #elif defined(TARGET_PPC) 2554 { 2555 int i; 2556 2557 #if defined(TARGET_PPC64) 2558 #if defined(TARGET_ABI32) 2559 env->msr &= ~((target_ulong)1 << MSR_SF); 2560 #else 2561 env->msr |= (target_ulong)1 << MSR_SF; 2562 #endif 2563 #endif 2564 env->nip = regs->nip; 2565 for(i = 0; i < 32; i++) { 2566 env->gpr[i] = regs->gpr[i]; 2567 } 2568 } 2569 #elif defined(TARGET_M68K) 2570 { 2571 env->pc = regs->pc; 2572 env->dregs[0] = regs->d0; 2573 env->dregs[1] = regs->d1; 2574 env->dregs[2] = regs->d2; 2575 env->dregs[3] = regs->d3; 2576 env->dregs[4] = regs->d4; 2577 env->dregs[5] = regs->d5; 2578 env->dregs[6] = regs->d6; 2579 env->dregs[7] = regs->d7; 2580 env->aregs[0] = regs->a0; 2581 env->aregs[1] = regs->a1; 2582 env->aregs[2] = regs->a2; 2583 env->aregs[3] = regs->a3; 2584 env->aregs[4] = regs->a4; 2585 env->aregs[5] = regs->a5; 2586 env->aregs[6] = regs->a6; 2587 env->aregs[7] = regs->usp; 2588 env->sr = regs->sr; 2589 ts->sim_syscalls = 1; 2590 } 2591 #elif defined(TARGET_MIPS) 2592 { 2593 int i; 2594 2595 for(i = 0; i < 32; i++) { 2596 env->active_tc.gpr[i] = regs->regs[i]; 2597 } 2598 env->active_tc.PC = regs->cp0_epc; 2599 } 2600 #elif defined(TARGET_SH4) 2601 { 2602 int i; 2603 2604 for(i = 0; i < 16; i++) { 2605 env->gregs[i] = regs->regs[i]; 2606 } 2607 env->pc = regs->pc; 2608 } 2609 #elif defined(TARGET_ALPHA) 2610 { 2611 int i; 2612 2613 for(i = 0; i < 28; i++) { 2614 env->ir[i] = ((abi_ulong *)regs)[i]; 2615 } 2616 env->ipr[IPR_USP] = regs->usp; 2617 env->ir[30] = regs->usp; 2618 env->pc = regs->pc; 2619 env->unique = regs->unique; 2620 } 2621 #elif defined(TARGET_CRIS) 2622 { 2623 env->regs[0] = regs->r0; 2624 env->regs[1] = regs->r1; 2625 env->regs[2] = regs->r2; 2626 env->regs[3] = regs->r3; 2627 env->regs[4] = regs->r4; 2628 env->regs[5] = regs->r5; 2629 env->regs[6] = regs->r6; 2630 env->regs[7] = regs->r7; 2631 env->regs[8] = regs->r8; 2632 env->regs[9] = regs->r9; 2633 env->regs[10] = regs->r10; 2634 env->regs[11] = regs->r11; 2635 env->regs[12] = regs->r12; 2636 env->regs[13] = regs->r13; 2637 env->regs[14] = info->start_stack; 2638 env->regs[15] = regs->acr; 2639 env->pc = regs->erp; 2640 } 2641 #else 2642 #error unsupported target CPU 2643 #endif 2644 2645 #if defined(TARGET_ARM) || defined(TARGET_M68K) 2646 ts->stack_base = info->start_stack; 2647 ts->heap_base = info->brk; 2648 /* This will be filled in on the first SYS_HEAPINFO call. */ 2649 ts->heap_limit = 0; 2650 #endif 2651 2652 if (gdbstub_port) { 2653 gdbserver_start (gdbstub_port); 2654 gdb_handlesig(env, 0); 2655 } 2656 cpu_loop(env); 2657 /* never exits */ 2658 return 0; 2659 } 2660