1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu-version.h" 21 #include <sys/syscall.h> 22 #include <sys/resource.h> 23 24 #include "qapi/error.h" 25 #include "qemu.h" 26 #include "qemu/path.h" 27 #include "qemu/config-file.h" 28 #include "qemu/cutils.h" 29 #include "qemu/help_option.h" 30 #include "cpu.h" 31 #include "exec/exec-all.h" 32 #include "tcg.h" 33 #include "qemu/timer.h" 34 #include "qemu/envlist.h" 35 #include "elf.h" 36 #include "exec/log.h" 37 #include "trace/control.h" 38 #include "glib-compat.h" 39 40 char *exec_path; 41 42 int singlestep; 43 static const char *filename; 44 static const char *argv0; 45 static int gdbstub_port; 46 static envlist_t *envlist; 47 static const char *cpu_model; 48 unsigned long mmap_min_addr; 49 unsigned long guest_base; 50 int have_guest_base; 51 52 #define EXCP_DUMP(env, fmt, ...) \ 53 do { \ 54 CPUState *cs = ENV_GET_CPU(env); \ 55 fprintf(stderr, fmt , ## __VA_ARGS__); \ 56 cpu_dump_state(cs, stderr, fprintf, 0); \ 57 if (qemu_log_separate()) { \ 58 qemu_log(fmt, ## __VA_ARGS__); \ 59 log_cpu_state(cs, 0); \ 60 } \ 61 } while (0) 62 63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 64 /* 65 * When running 32-on-64 we should make sure we can fit all of the possible 66 * guest address space into a contiguous chunk of virtual host memory. 67 * 68 * This way we will never overlap with our own libraries or binaries or stack 69 * or anything else that QEMU maps. 70 */ 71 # ifdef TARGET_MIPS 72 /* MIPS only supports 31 bits of virtual address space for user space */ 73 unsigned long reserved_va = 0x77000000; 74 # else 75 unsigned long reserved_va = 0xf7000000; 76 # endif 77 #else 78 unsigned long reserved_va; 79 #endif 80 81 static void usage(int exitcode); 82 83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 84 const char *qemu_uname_release; 85 86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 87 we allocate a bigger stack. Need a better solution, for example 88 by remapping the process stack directly at the right place */ 89 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 90 91 void gemu_log(const char *fmt, ...) 92 { 93 va_list ap; 94 95 va_start(ap, fmt); 96 vfprintf(stderr, fmt, ap); 97 va_end(ap); 98 } 99 100 #if defined(TARGET_I386) 101 int cpu_get_pic_interrupt(CPUX86State *env) 102 { 103 return -1; 104 } 105 #endif 106 107 /***********************************************************/ 108 /* Helper routines for implementing atomic operations. */ 109 110 /* Make sure everything is in a consistent state for calling fork(). */ 111 void fork_start(void) 112 { 113 cpu_list_lock(); 114 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 115 mmap_fork_start(); 116 } 117 118 void fork_end(int child) 119 { 120 mmap_fork_end(child); 121 if (child) { 122 CPUState *cpu, *next_cpu; 123 /* Child processes created by fork() only have a single thread. 124 Discard information about the parent threads. */ 125 CPU_FOREACH_SAFE(cpu, next_cpu) { 126 if (cpu != thread_cpu) { 127 QTAILQ_REMOVE(&cpus, cpu, node); 128 } 129 } 130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); 131 qemu_init_cpu_list(); 132 gdbserver_fork(thread_cpu); 133 } else { 134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 135 cpu_list_unlock(); 136 } 137 } 138 139 #ifdef TARGET_I386 140 /***********************************************************/ 141 /* CPUX86 core interface */ 142 143 uint64_t cpu_get_tsc(CPUX86State *env) 144 { 145 return cpu_get_host_ticks(); 146 } 147 148 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 149 int flags) 150 { 151 unsigned int e1, e2; 152 uint32_t *p; 153 e1 = (addr << 16) | (limit & 0xffff); 154 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 155 e2 |= flags; 156 p = ptr; 157 p[0] = tswap32(e1); 158 p[1] = tswap32(e2); 159 } 160 161 static uint64_t *idt_table; 162 #ifdef TARGET_X86_64 163 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 164 uint64_t addr, unsigned int sel) 165 { 166 uint32_t *p, e1, e2; 167 e1 = (addr & 0xffff) | (sel << 16); 168 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 169 p = ptr; 170 p[0] = tswap32(e1); 171 p[1] = tswap32(e2); 172 p[2] = tswap32(addr >> 32); 173 p[3] = 0; 174 } 175 /* only dpl matters as we do only user space emulation */ 176 static void set_idt(int n, unsigned int dpl) 177 { 178 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 179 } 180 #else 181 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 182 uint32_t addr, unsigned int sel) 183 { 184 uint32_t *p, e1, e2; 185 e1 = (addr & 0xffff) | (sel << 16); 186 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 187 p = ptr; 188 p[0] = tswap32(e1); 189 p[1] = tswap32(e2); 190 } 191 192 /* only dpl matters as we do only user space emulation */ 193 static void set_idt(int n, unsigned int dpl) 194 { 195 set_gate(idt_table + n, 0, dpl, 0, 0); 196 } 197 #endif 198 199 void cpu_loop(CPUX86State *env) 200 { 201 CPUState *cs = CPU(x86_env_get_cpu(env)); 202 int trapnr; 203 abi_ulong pc; 204 abi_ulong ret; 205 target_siginfo_t info; 206 207 for(;;) { 208 cpu_exec_start(cs); 209 trapnr = cpu_exec(cs); 210 cpu_exec_end(cs); 211 process_queued_cpu_work(cs); 212 213 switch(trapnr) { 214 case 0x80: 215 /* linux syscall from int $0x80 */ 216 ret = do_syscall(env, 217 env->regs[R_EAX], 218 env->regs[R_EBX], 219 env->regs[R_ECX], 220 env->regs[R_EDX], 221 env->regs[R_ESI], 222 env->regs[R_EDI], 223 env->regs[R_EBP], 224 0, 0); 225 if (ret == -TARGET_ERESTARTSYS) { 226 env->eip -= 2; 227 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 228 env->regs[R_EAX] = ret; 229 } 230 break; 231 #ifndef TARGET_ABI32 232 case EXCP_SYSCALL: 233 /* linux syscall from syscall instruction */ 234 ret = do_syscall(env, 235 env->regs[R_EAX], 236 env->regs[R_EDI], 237 env->regs[R_ESI], 238 env->regs[R_EDX], 239 env->regs[10], 240 env->regs[8], 241 env->regs[9], 242 0, 0); 243 if (ret == -TARGET_ERESTARTSYS) { 244 env->eip -= 2; 245 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 246 env->regs[R_EAX] = ret; 247 } 248 break; 249 #endif 250 case EXCP0B_NOSEG: 251 case EXCP0C_STACK: 252 info.si_signo = TARGET_SIGBUS; 253 info.si_errno = 0; 254 info.si_code = TARGET_SI_KERNEL; 255 info._sifields._sigfault._addr = 0; 256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 257 break; 258 case EXCP0D_GPF: 259 /* XXX: potential problem if ABI32 */ 260 #ifndef TARGET_X86_64 261 if (env->eflags & VM_MASK) { 262 handle_vm86_fault(env); 263 } else 264 #endif 265 { 266 info.si_signo = TARGET_SIGSEGV; 267 info.si_errno = 0; 268 info.si_code = TARGET_SI_KERNEL; 269 info._sifields._sigfault._addr = 0; 270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 271 } 272 break; 273 case EXCP0E_PAGE: 274 info.si_signo = TARGET_SIGSEGV; 275 info.si_errno = 0; 276 if (!(env->error_code & 1)) 277 info.si_code = TARGET_SEGV_MAPERR; 278 else 279 info.si_code = TARGET_SEGV_ACCERR; 280 info._sifields._sigfault._addr = env->cr[2]; 281 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 282 break; 283 case EXCP00_DIVZ: 284 #ifndef TARGET_X86_64 285 if (env->eflags & VM_MASK) { 286 handle_vm86_trap(env, trapnr); 287 } else 288 #endif 289 { 290 /* division by zero */ 291 info.si_signo = TARGET_SIGFPE; 292 info.si_errno = 0; 293 info.si_code = TARGET_FPE_INTDIV; 294 info._sifields._sigfault._addr = env->eip; 295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 296 } 297 break; 298 case EXCP01_DB: 299 case EXCP03_INT3: 300 #ifndef TARGET_X86_64 301 if (env->eflags & VM_MASK) { 302 handle_vm86_trap(env, trapnr); 303 } else 304 #endif 305 { 306 info.si_signo = TARGET_SIGTRAP; 307 info.si_errno = 0; 308 if (trapnr == EXCP01_DB) { 309 info.si_code = TARGET_TRAP_BRKPT; 310 info._sifields._sigfault._addr = env->eip; 311 } else { 312 info.si_code = TARGET_SI_KERNEL; 313 info._sifields._sigfault._addr = 0; 314 } 315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 316 } 317 break; 318 case EXCP04_INTO: 319 case EXCP05_BOUND: 320 #ifndef TARGET_X86_64 321 if (env->eflags & VM_MASK) { 322 handle_vm86_trap(env, trapnr); 323 } else 324 #endif 325 { 326 info.si_signo = TARGET_SIGSEGV; 327 info.si_errno = 0; 328 info.si_code = TARGET_SI_KERNEL; 329 info._sifields._sigfault._addr = 0; 330 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 331 } 332 break; 333 case EXCP06_ILLOP: 334 info.si_signo = TARGET_SIGILL; 335 info.si_errno = 0; 336 info.si_code = TARGET_ILL_ILLOPN; 337 info._sifields._sigfault._addr = env->eip; 338 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 339 break; 340 case EXCP_INTERRUPT: 341 /* just indicate that signals should be handled asap */ 342 break; 343 case EXCP_DEBUG: 344 { 345 int sig; 346 347 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 348 if (sig) 349 { 350 info.si_signo = sig; 351 info.si_errno = 0; 352 info.si_code = TARGET_TRAP_BRKPT; 353 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 354 } 355 } 356 break; 357 default: 358 pc = env->segs[R_CS].base + env->eip; 359 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 360 (long)pc, trapnr); 361 abort(); 362 } 363 process_pending_signals(env); 364 } 365 } 366 #endif 367 368 #ifdef TARGET_ARM 369 370 #define get_user_code_u32(x, gaddr, env) \ 371 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 372 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 373 (x) = bswap32(x); \ 374 } \ 375 __r; \ 376 }) 377 378 #define get_user_code_u16(x, gaddr, env) \ 379 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 380 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 381 (x) = bswap16(x); \ 382 } \ 383 __r; \ 384 }) 385 386 #define get_user_data_u32(x, gaddr, env) \ 387 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 388 if (!__r && arm_cpu_bswap_data(env)) { \ 389 (x) = bswap32(x); \ 390 } \ 391 __r; \ 392 }) 393 394 #define get_user_data_u16(x, gaddr, env) \ 395 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 396 if (!__r && arm_cpu_bswap_data(env)) { \ 397 (x) = bswap16(x); \ 398 } \ 399 __r; \ 400 }) 401 402 #define put_user_data_u32(x, gaddr, env) \ 403 ({ typeof(x) __x = (x); \ 404 if (arm_cpu_bswap_data(env)) { \ 405 __x = bswap32(__x); \ 406 } \ 407 put_user_u32(__x, (gaddr)); \ 408 }) 409 410 #define put_user_data_u16(x, gaddr, env) \ 411 ({ typeof(x) __x = (x); \ 412 if (arm_cpu_bswap_data(env)) { \ 413 __x = bswap16(__x); \ 414 } \ 415 put_user_u16(__x, (gaddr)); \ 416 }) 417 418 #ifdef TARGET_ABI32 419 /* Commpage handling -- there is no commpage for AArch64 */ 420 421 /* 422 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 423 * Input: 424 * r0 = pointer to oldval 425 * r1 = pointer to newval 426 * r2 = pointer to target value 427 * 428 * Output: 429 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 430 * C set if *ptr was changed, clear if no exchange happened 431 * 432 * Note segv's in kernel helpers are a bit tricky, we can set the 433 * data address sensibly but the PC address is just the entry point. 434 */ 435 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 436 { 437 uint64_t oldval, newval, val; 438 uint32_t addr, cpsr; 439 target_siginfo_t info; 440 441 /* Based on the 32 bit code in do_kernel_trap */ 442 443 /* XXX: This only works between threads, not between processes. 444 It's probably possible to implement this with native host 445 operations. However things like ldrex/strex are much harder so 446 there's not much point trying. */ 447 start_exclusive(); 448 cpsr = cpsr_read(env); 449 addr = env->regs[2]; 450 451 if (get_user_u64(oldval, env->regs[0])) { 452 env->exception.vaddress = env->regs[0]; 453 goto segv; 454 }; 455 456 if (get_user_u64(newval, env->regs[1])) { 457 env->exception.vaddress = env->regs[1]; 458 goto segv; 459 }; 460 461 if (get_user_u64(val, addr)) { 462 env->exception.vaddress = addr; 463 goto segv; 464 } 465 466 if (val == oldval) { 467 val = newval; 468 469 if (put_user_u64(val, addr)) { 470 env->exception.vaddress = addr; 471 goto segv; 472 }; 473 474 env->regs[0] = 0; 475 cpsr |= CPSR_C; 476 } else { 477 env->regs[0] = -1; 478 cpsr &= ~CPSR_C; 479 } 480 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 481 end_exclusive(); 482 return; 483 484 segv: 485 end_exclusive(); 486 /* We get the PC of the entry address - which is as good as anything, 487 on a real kernel what you get depends on which mode it uses. */ 488 info.si_signo = TARGET_SIGSEGV; 489 info.si_errno = 0; 490 /* XXX: check env->error_code */ 491 info.si_code = TARGET_SEGV_MAPERR; 492 info._sifields._sigfault._addr = env->exception.vaddress; 493 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 494 } 495 496 /* Handle a jump to the kernel code page. */ 497 static int 498 do_kernel_trap(CPUARMState *env) 499 { 500 uint32_t addr; 501 uint32_t cpsr; 502 uint32_t val; 503 504 switch (env->regs[15]) { 505 case 0xffff0fa0: /* __kernel_memory_barrier */ 506 /* ??? No-op. Will need to do better for SMP. */ 507 break; 508 case 0xffff0fc0: /* __kernel_cmpxchg */ 509 /* XXX: This only works between threads, not between processes. 510 It's probably possible to implement this with native host 511 operations. However things like ldrex/strex are much harder so 512 there's not much point trying. */ 513 start_exclusive(); 514 cpsr = cpsr_read(env); 515 addr = env->regs[2]; 516 /* FIXME: This should SEGV if the access fails. */ 517 if (get_user_u32(val, addr)) 518 val = ~env->regs[0]; 519 if (val == env->regs[0]) { 520 val = env->regs[1]; 521 /* FIXME: Check for segfaults. */ 522 put_user_u32(val, addr); 523 env->regs[0] = 0; 524 cpsr |= CPSR_C; 525 } else { 526 env->regs[0] = -1; 527 cpsr &= ~CPSR_C; 528 } 529 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 530 end_exclusive(); 531 break; 532 case 0xffff0fe0: /* __kernel_get_tls */ 533 env->regs[0] = cpu_get_tls(env); 534 break; 535 case 0xffff0f60: /* __kernel_cmpxchg64 */ 536 arm_kernel_cmpxchg64_helper(env); 537 break; 538 539 default: 540 return 1; 541 } 542 /* Jump back to the caller. */ 543 addr = env->regs[14]; 544 if (addr & 1) { 545 env->thumb = 1; 546 addr &= ~1; 547 } 548 env->regs[15] = addr; 549 550 return 0; 551 } 552 553 /* Store exclusive handling for AArch32 */ 554 static int do_strex(CPUARMState *env) 555 { 556 uint64_t val; 557 int size; 558 int rc = 1; 559 int segv = 0; 560 uint32_t addr; 561 start_exclusive(); 562 if (env->exclusive_addr != env->exclusive_test) { 563 goto fail; 564 } 565 /* We know we're always AArch32 so the address is in uint32_t range 566 * unless it was the -1 exclusive-monitor-lost value (which won't 567 * match exclusive_test above). 568 */ 569 assert(extract64(env->exclusive_addr, 32, 32) == 0); 570 addr = env->exclusive_addr; 571 size = env->exclusive_info & 0xf; 572 switch (size) { 573 case 0: 574 segv = get_user_u8(val, addr); 575 break; 576 case 1: 577 segv = get_user_data_u16(val, addr, env); 578 break; 579 case 2: 580 case 3: 581 segv = get_user_data_u32(val, addr, env); 582 break; 583 default: 584 abort(); 585 } 586 if (segv) { 587 env->exception.vaddress = addr; 588 goto done; 589 } 590 if (size == 3) { 591 uint32_t valhi; 592 segv = get_user_data_u32(valhi, addr + 4, env); 593 if (segv) { 594 env->exception.vaddress = addr + 4; 595 goto done; 596 } 597 if (arm_cpu_bswap_data(env)) { 598 val = deposit64((uint64_t)valhi, 32, 32, val); 599 } else { 600 val = deposit64(val, 32, 32, valhi); 601 } 602 } 603 if (val != env->exclusive_val) { 604 goto fail; 605 } 606 607 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 608 switch (size) { 609 case 0: 610 segv = put_user_u8(val, addr); 611 break; 612 case 1: 613 segv = put_user_data_u16(val, addr, env); 614 break; 615 case 2: 616 case 3: 617 segv = put_user_data_u32(val, addr, env); 618 break; 619 } 620 if (segv) { 621 env->exception.vaddress = addr; 622 goto done; 623 } 624 if (size == 3) { 625 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 626 segv = put_user_data_u32(val, addr + 4, env); 627 if (segv) { 628 env->exception.vaddress = addr + 4; 629 goto done; 630 } 631 } 632 rc = 0; 633 fail: 634 env->regs[15] += 4; 635 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 636 done: 637 end_exclusive(); 638 return segv; 639 } 640 641 void cpu_loop(CPUARMState *env) 642 { 643 CPUState *cs = CPU(arm_env_get_cpu(env)); 644 int trapnr; 645 unsigned int n, insn; 646 target_siginfo_t info; 647 uint32_t addr; 648 abi_ulong ret; 649 650 for(;;) { 651 cpu_exec_start(cs); 652 trapnr = cpu_exec(cs); 653 cpu_exec_end(cs); 654 process_queued_cpu_work(cs); 655 656 switch(trapnr) { 657 case EXCP_UDEF: 658 { 659 TaskState *ts = cs->opaque; 660 uint32_t opcode; 661 int rc; 662 663 /* we handle the FPU emulation here, as Linux */ 664 /* we get the opcode */ 665 /* FIXME - what to do if get_user() fails? */ 666 get_user_code_u32(opcode, env->regs[15], env); 667 668 rc = EmulateAll(opcode, &ts->fpa, env); 669 if (rc == 0) { /* illegal instruction */ 670 info.si_signo = TARGET_SIGILL; 671 info.si_errno = 0; 672 info.si_code = TARGET_ILL_ILLOPN; 673 info._sifields._sigfault._addr = env->regs[15]; 674 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 675 } else if (rc < 0) { /* FP exception */ 676 int arm_fpe=0; 677 678 /* translate softfloat flags to FPSR flags */ 679 if (-rc & float_flag_invalid) 680 arm_fpe |= BIT_IOC; 681 if (-rc & float_flag_divbyzero) 682 arm_fpe |= BIT_DZC; 683 if (-rc & float_flag_overflow) 684 arm_fpe |= BIT_OFC; 685 if (-rc & float_flag_underflow) 686 arm_fpe |= BIT_UFC; 687 if (-rc & float_flag_inexact) 688 arm_fpe |= BIT_IXC; 689 690 FPSR fpsr = ts->fpa.fpsr; 691 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 692 693 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 694 info.si_signo = TARGET_SIGFPE; 695 info.si_errno = 0; 696 697 /* ordered by priority, least first */ 698 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 699 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 700 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 701 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 702 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 703 704 info._sifields._sigfault._addr = env->regs[15]; 705 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 706 } else { 707 env->regs[15] += 4; 708 } 709 710 /* accumulate unenabled exceptions */ 711 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 712 fpsr |= BIT_IXC; 713 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 714 fpsr |= BIT_UFC; 715 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 716 fpsr |= BIT_OFC; 717 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 718 fpsr |= BIT_DZC; 719 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 720 fpsr |= BIT_IOC; 721 ts->fpa.fpsr=fpsr; 722 } else { /* everything OK */ 723 /* increment PC */ 724 env->regs[15] += 4; 725 } 726 } 727 break; 728 case EXCP_SWI: 729 case EXCP_BKPT: 730 { 731 env->eabi = 1; 732 /* system call */ 733 if (trapnr == EXCP_BKPT) { 734 if (env->thumb) { 735 /* FIXME - what to do if get_user() fails? */ 736 get_user_code_u16(insn, env->regs[15], env); 737 n = insn & 0xff; 738 env->regs[15] += 2; 739 } else { 740 /* FIXME - what to do if get_user() fails? */ 741 get_user_code_u32(insn, env->regs[15], env); 742 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 743 env->regs[15] += 4; 744 } 745 } else { 746 if (env->thumb) { 747 /* FIXME - what to do if get_user() fails? */ 748 get_user_code_u16(insn, env->regs[15] - 2, env); 749 n = insn & 0xff; 750 } else { 751 /* FIXME - what to do if get_user() fails? */ 752 get_user_code_u32(insn, env->regs[15] - 4, env); 753 n = insn & 0xffffff; 754 } 755 } 756 757 if (n == ARM_NR_cacheflush) { 758 /* nop */ 759 } else if (n == ARM_NR_semihosting 760 || n == ARM_NR_thumb_semihosting) { 761 env->regs[0] = do_arm_semihosting (env); 762 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 763 /* linux syscall */ 764 if (env->thumb || n == 0) { 765 n = env->regs[7]; 766 } else { 767 n -= ARM_SYSCALL_BASE; 768 env->eabi = 0; 769 } 770 if ( n > ARM_NR_BASE) { 771 switch (n) { 772 case ARM_NR_cacheflush: 773 /* nop */ 774 break; 775 case ARM_NR_set_tls: 776 cpu_set_tls(env, env->regs[0]); 777 env->regs[0] = 0; 778 break; 779 case ARM_NR_breakpoint: 780 env->regs[15] -= env->thumb ? 2 : 4; 781 goto excp_debug; 782 default: 783 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 784 n); 785 env->regs[0] = -TARGET_ENOSYS; 786 break; 787 } 788 } else { 789 ret = do_syscall(env, 790 n, 791 env->regs[0], 792 env->regs[1], 793 env->regs[2], 794 env->regs[3], 795 env->regs[4], 796 env->regs[5], 797 0, 0); 798 if (ret == -TARGET_ERESTARTSYS) { 799 env->regs[15] -= env->thumb ? 2 : 4; 800 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 801 env->regs[0] = ret; 802 } 803 } 804 } else { 805 goto error; 806 } 807 } 808 break; 809 case EXCP_SEMIHOST: 810 env->regs[0] = do_arm_semihosting(env); 811 break; 812 case EXCP_INTERRUPT: 813 /* just indicate that signals should be handled asap */ 814 break; 815 case EXCP_STREX: 816 if (!do_strex(env)) { 817 break; 818 } 819 /* fall through for segv */ 820 case EXCP_PREFETCH_ABORT: 821 case EXCP_DATA_ABORT: 822 addr = env->exception.vaddress; 823 { 824 info.si_signo = TARGET_SIGSEGV; 825 info.si_errno = 0; 826 /* XXX: check env->error_code */ 827 info.si_code = TARGET_SEGV_MAPERR; 828 info._sifields._sigfault._addr = addr; 829 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 830 } 831 break; 832 case EXCP_DEBUG: 833 excp_debug: 834 { 835 int sig; 836 837 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 838 if (sig) 839 { 840 info.si_signo = sig; 841 info.si_errno = 0; 842 info.si_code = TARGET_TRAP_BRKPT; 843 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 844 } 845 } 846 break; 847 case EXCP_KERNEL_TRAP: 848 if (do_kernel_trap(env)) 849 goto error; 850 break; 851 case EXCP_YIELD: 852 /* nothing to do here for user-mode, just resume guest code */ 853 break; 854 default: 855 error: 856 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 857 abort(); 858 } 859 process_pending_signals(env); 860 } 861 } 862 863 #else 864 865 /* 866 * Handle AArch64 store-release exclusive 867 * 868 * rs = gets the status result of store exclusive 869 * rt = is the register that is stored 870 * rt2 = is the second register store (in STP) 871 * 872 */ 873 static int do_strex_a64(CPUARMState *env) 874 { 875 uint64_t val; 876 int size; 877 bool is_pair; 878 int rc = 1; 879 int segv = 0; 880 uint64_t addr; 881 int rs, rt, rt2; 882 883 start_exclusive(); 884 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ 885 size = extract32(env->exclusive_info, 0, 2); 886 is_pair = extract32(env->exclusive_info, 2, 1); 887 rs = extract32(env->exclusive_info, 4, 5); 888 rt = extract32(env->exclusive_info, 9, 5); 889 rt2 = extract32(env->exclusive_info, 14, 5); 890 891 addr = env->exclusive_addr; 892 893 if (addr != env->exclusive_test) { 894 goto finish; 895 } 896 897 switch (size) { 898 case 0: 899 segv = get_user_u8(val, addr); 900 break; 901 case 1: 902 segv = get_user_u16(val, addr); 903 break; 904 case 2: 905 segv = get_user_u32(val, addr); 906 break; 907 case 3: 908 segv = get_user_u64(val, addr); 909 break; 910 default: 911 abort(); 912 } 913 if (segv) { 914 env->exception.vaddress = addr; 915 goto error; 916 } 917 if (val != env->exclusive_val) { 918 goto finish; 919 } 920 if (is_pair) { 921 if (size == 2) { 922 segv = get_user_u32(val, addr + 4); 923 } else { 924 segv = get_user_u64(val, addr + 8); 925 } 926 if (segv) { 927 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 928 goto error; 929 } 930 if (val != env->exclusive_high) { 931 goto finish; 932 } 933 } 934 /* handle the zero register */ 935 val = rt == 31 ? 0 : env->xregs[rt]; 936 switch (size) { 937 case 0: 938 segv = put_user_u8(val, addr); 939 break; 940 case 1: 941 segv = put_user_u16(val, addr); 942 break; 943 case 2: 944 segv = put_user_u32(val, addr); 945 break; 946 case 3: 947 segv = put_user_u64(val, addr); 948 break; 949 } 950 if (segv) { 951 goto error; 952 } 953 if (is_pair) { 954 /* handle the zero register */ 955 val = rt2 == 31 ? 0 : env->xregs[rt2]; 956 if (size == 2) { 957 segv = put_user_u32(val, addr + 4); 958 } else { 959 segv = put_user_u64(val, addr + 8); 960 } 961 if (segv) { 962 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 963 goto error; 964 } 965 } 966 rc = 0; 967 finish: 968 env->pc += 4; 969 /* rs == 31 encodes a write to the ZR, thus throwing away 970 * the status return. This is rather silly but valid. 971 */ 972 if (rs < 31) { 973 env->xregs[rs] = rc; 974 } 975 error: 976 /* instruction faulted, PC does not advance */ 977 /* either way a strex releases any exclusive lock we have */ 978 env->exclusive_addr = -1; 979 end_exclusive(); 980 return segv; 981 } 982 983 /* AArch64 main loop */ 984 void cpu_loop(CPUARMState *env) 985 { 986 CPUState *cs = CPU(arm_env_get_cpu(env)); 987 int trapnr, sig; 988 abi_long ret; 989 target_siginfo_t info; 990 991 for (;;) { 992 cpu_exec_start(cs); 993 trapnr = cpu_exec(cs); 994 cpu_exec_end(cs); 995 process_queued_cpu_work(cs); 996 997 switch (trapnr) { 998 case EXCP_SWI: 999 ret = do_syscall(env, 1000 env->xregs[8], 1001 env->xregs[0], 1002 env->xregs[1], 1003 env->xregs[2], 1004 env->xregs[3], 1005 env->xregs[4], 1006 env->xregs[5], 1007 0, 0); 1008 if (ret == -TARGET_ERESTARTSYS) { 1009 env->pc -= 4; 1010 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 1011 env->xregs[0] = ret; 1012 } 1013 break; 1014 case EXCP_INTERRUPT: 1015 /* just indicate that signals should be handled asap */ 1016 break; 1017 case EXCP_UDEF: 1018 info.si_signo = TARGET_SIGILL; 1019 info.si_errno = 0; 1020 info.si_code = TARGET_ILL_ILLOPN; 1021 info._sifields._sigfault._addr = env->pc; 1022 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1023 break; 1024 case EXCP_STREX: 1025 if (!do_strex_a64(env)) { 1026 break; 1027 } 1028 /* fall through for segv */ 1029 case EXCP_PREFETCH_ABORT: 1030 case EXCP_DATA_ABORT: 1031 info.si_signo = TARGET_SIGSEGV; 1032 info.si_errno = 0; 1033 /* XXX: check env->error_code */ 1034 info.si_code = TARGET_SEGV_MAPERR; 1035 info._sifields._sigfault._addr = env->exception.vaddress; 1036 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1037 break; 1038 case EXCP_DEBUG: 1039 case EXCP_BKPT: 1040 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1041 if (sig) { 1042 info.si_signo = sig; 1043 info.si_errno = 0; 1044 info.si_code = TARGET_TRAP_BRKPT; 1045 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1046 } 1047 break; 1048 case EXCP_SEMIHOST: 1049 env->xregs[0] = do_arm_semihosting(env); 1050 break; 1051 case EXCP_YIELD: 1052 /* nothing to do here for user-mode, just resume guest code */ 1053 break; 1054 default: 1055 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1056 abort(); 1057 } 1058 process_pending_signals(env); 1059 /* Exception return on AArch64 always clears the exclusive monitor, 1060 * so any return to running guest code implies this. 1061 * A strex (successful or otherwise) also clears the monitor, so 1062 * we don't need to specialcase EXCP_STREX. 1063 */ 1064 env->exclusive_addr = -1; 1065 } 1066 } 1067 #endif /* ndef TARGET_ABI32 */ 1068 1069 #endif 1070 1071 #ifdef TARGET_UNICORE32 1072 1073 void cpu_loop(CPUUniCore32State *env) 1074 { 1075 CPUState *cs = CPU(uc32_env_get_cpu(env)); 1076 int trapnr; 1077 unsigned int n, insn; 1078 target_siginfo_t info; 1079 1080 for (;;) { 1081 cpu_exec_start(cs); 1082 trapnr = cpu_exec(cs); 1083 cpu_exec_end(cs); 1084 process_queued_cpu_work(cs); 1085 1086 switch (trapnr) { 1087 case UC32_EXCP_PRIV: 1088 { 1089 /* system call */ 1090 get_user_u32(insn, env->regs[31] - 4); 1091 n = insn & 0xffffff; 1092 1093 if (n >= UC32_SYSCALL_BASE) { 1094 /* linux syscall */ 1095 n -= UC32_SYSCALL_BASE; 1096 if (n == UC32_SYSCALL_NR_set_tls) { 1097 cpu_set_tls(env, env->regs[0]); 1098 env->regs[0] = 0; 1099 } else { 1100 abi_long ret = do_syscall(env, 1101 n, 1102 env->regs[0], 1103 env->regs[1], 1104 env->regs[2], 1105 env->regs[3], 1106 env->regs[4], 1107 env->regs[5], 1108 0, 0); 1109 if (ret == -TARGET_ERESTARTSYS) { 1110 env->regs[31] -= 4; 1111 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 1112 env->regs[0] = ret; 1113 } 1114 } 1115 } else { 1116 goto error; 1117 } 1118 } 1119 break; 1120 case UC32_EXCP_DTRAP: 1121 case UC32_EXCP_ITRAP: 1122 info.si_signo = TARGET_SIGSEGV; 1123 info.si_errno = 0; 1124 /* XXX: check env->error_code */ 1125 info.si_code = TARGET_SEGV_MAPERR; 1126 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 1127 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1128 break; 1129 case EXCP_INTERRUPT: 1130 /* just indicate that signals should be handled asap */ 1131 break; 1132 case EXCP_DEBUG: 1133 { 1134 int sig; 1135 1136 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1137 if (sig) { 1138 info.si_signo = sig; 1139 info.si_errno = 0; 1140 info.si_code = TARGET_TRAP_BRKPT; 1141 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1142 } 1143 } 1144 break; 1145 default: 1146 goto error; 1147 } 1148 process_pending_signals(env); 1149 } 1150 1151 error: 1152 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1153 abort(); 1154 } 1155 #endif 1156 1157 #ifdef TARGET_SPARC 1158 #define SPARC64_STACK_BIAS 2047 1159 1160 //#define DEBUG_WIN 1161 1162 /* WARNING: dealing with register windows _is_ complicated. More info 1163 can be found at http://www.sics.se/~psm/sparcstack.html */ 1164 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 1165 { 1166 index = (index + cwp * 16) % (16 * env->nwindows); 1167 /* wrap handling : if cwp is on the last window, then we use the 1168 registers 'after' the end */ 1169 if (index < 8 && env->cwp == env->nwindows - 1) 1170 index += 16 * env->nwindows; 1171 return index; 1172 } 1173 1174 /* save the register window 'cwp1' */ 1175 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1176 { 1177 unsigned int i; 1178 abi_ulong sp_ptr; 1179 1180 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1181 #ifdef TARGET_SPARC64 1182 if (sp_ptr & 3) 1183 sp_ptr += SPARC64_STACK_BIAS; 1184 #endif 1185 #if defined(DEBUG_WIN) 1186 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1187 sp_ptr, cwp1); 1188 #endif 1189 for(i = 0; i < 16; i++) { 1190 /* FIXME - what to do if put_user() fails? */ 1191 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1192 sp_ptr += sizeof(abi_ulong); 1193 } 1194 } 1195 1196 static void save_window(CPUSPARCState *env) 1197 { 1198 #ifndef TARGET_SPARC64 1199 unsigned int new_wim; 1200 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1201 ((1LL << env->nwindows) - 1); 1202 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1203 env->wim = new_wim; 1204 #else 1205 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1206 env->cansave++; 1207 env->canrestore--; 1208 #endif 1209 } 1210 1211 static void restore_window(CPUSPARCState *env) 1212 { 1213 #ifndef TARGET_SPARC64 1214 unsigned int new_wim; 1215 #endif 1216 unsigned int i, cwp1; 1217 abi_ulong sp_ptr; 1218 1219 #ifndef TARGET_SPARC64 1220 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1221 ((1LL << env->nwindows) - 1); 1222 #endif 1223 1224 /* restore the invalid window */ 1225 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1226 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1227 #ifdef TARGET_SPARC64 1228 if (sp_ptr & 3) 1229 sp_ptr += SPARC64_STACK_BIAS; 1230 #endif 1231 #if defined(DEBUG_WIN) 1232 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1233 sp_ptr, cwp1); 1234 #endif 1235 for(i = 0; i < 16; i++) { 1236 /* FIXME - what to do if get_user() fails? */ 1237 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1238 sp_ptr += sizeof(abi_ulong); 1239 } 1240 #ifdef TARGET_SPARC64 1241 env->canrestore++; 1242 if (env->cleanwin < env->nwindows - 1) 1243 env->cleanwin++; 1244 env->cansave--; 1245 #else 1246 env->wim = new_wim; 1247 #endif 1248 } 1249 1250 static void flush_windows(CPUSPARCState *env) 1251 { 1252 int offset, cwp1; 1253 1254 offset = 1; 1255 for(;;) { 1256 /* if restore would invoke restore_window(), then we can stop */ 1257 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1258 #ifndef TARGET_SPARC64 1259 if (env->wim & (1 << cwp1)) 1260 break; 1261 #else 1262 if (env->canrestore == 0) 1263 break; 1264 env->cansave++; 1265 env->canrestore--; 1266 #endif 1267 save_window_offset(env, cwp1); 1268 offset++; 1269 } 1270 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1271 #ifndef TARGET_SPARC64 1272 /* set wim so that restore will reload the registers */ 1273 env->wim = 1 << cwp1; 1274 #endif 1275 #if defined(DEBUG_WIN) 1276 printf("flush_windows: nb=%d\n", offset - 1); 1277 #endif 1278 } 1279 1280 void cpu_loop (CPUSPARCState *env) 1281 { 1282 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1283 int trapnr; 1284 abi_long ret; 1285 target_siginfo_t info; 1286 1287 while (1) { 1288 cpu_exec_start(cs); 1289 trapnr = cpu_exec(cs); 1290 cpu_exec_end(cs); 1291 process_queued_cpu_work(cs); 1292 1293 /* Compute PSR before exposing state. */ 1294 if (env->cc_op != CC_OP_FLAGS) { 1295 cpu_get_psr(env); 1296 } 1297 1298 switch (trapnr) { 1299 #ifndef TARGET_SPARC64 1300 case 0x88: 1301 case 0x90: 1302 #else 1303 case 0x110: 1304 case 0x16d: 1305 #endif 1306 ret = do_syscall (env, env->gregs[1], 1307 env->regwptr[0], env->regwptr[1], 1308 env->regwptr[2], env->regwptr[3], 1309 env->regwptr[4], env->regwptr[5], 1310 0, 0); 1311 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { 1312 break; 1313 } 1314 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1315 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1316 env->xcc |= PSR_CARRY; 1317 #else 1318 env->psr |= PSR_CARRY; 1319 #endif 1320 ret = -ret; 1321 } else { 1322 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1323 env->xcc &= ~PSR_CARRY; 1324 #else 1325 env->psr &= ~PSR_CARRY; 1326 #endif 1327 } 1328 env->regwptr[0] = ret; 1329 /* next instruction */ 1330 env->pc = env->npc; 1331 env->npc = env->npc + 4; 1332 break; 1333 case 0x83: /* flush windows */ 1334 #ifdef TARGET_ABI32 1335 case 0x103: 1336 #endif 1337 flush_windows(env); 1338 /* next instruction */ 1339 env->pc = env->npc; 1340 env->npc = env->npc + 4; 1341 break; 1342 #ifndef TARGET_SPARC64 1343 case TT_WIN_OVF: /* window overflow */ 1344 save_window(env); 1345 break; 1346 case TT_WIN_UNF: /* window underflow */ 1347 restore_window(env); 1348 break; 1349 case TT_TFAULT: 1350 case TT_DFAULT: 1351 { 1352 info.si_signo = TARGET_SIGSEGV; 1353 info.si_errno = 0; 1354 /* XXX: check env->error_code */ 1355 info.si_code = TARGET_SEGV_MAPERR; 1356 info._sifields._sigfault._addr = env->mmuregs[4]; 1357 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1358 } 1359 break; 1360 #else 1361 case TT_SPILL: /* window overflow */ 1362 save_window(env); 1363 break; 1364 case TT_FILL: /* window underflow */ 1365 restore_window(env); 1366 break; 1367 case TT_TFAULT: 1368 case TT_DFAULT: 1369 { 1370 info.si_signo = TARGET_SIGSEGV; 1371 info.si_errno = 0; 1372 /* XXX: check env->error_code */ 1373 info.si_code = TARGET_SEGV_MAPERR; 1374 if (trapnr == TT_DFAULT) 1375 info._sifields._sigfault._addr = env->dmmuregs[4]; 1376 else 1377 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1378 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1379 } 1380 break; 1381 #ifndef TARGET_ABI32 1382 case 0x16e: 1383 flush_windows(env); 1384 sparc64_get_context(env); 1385 break; 1386 case 0x16f: 1387 flush_windows(env); 1388 sparc64_set_context(env); 1389 break; 1390 #endif 1391 #endif 1392 case EXCP_INTERRUPT: 1393 /* just indicate that signals should be handled asap */ 1394 break; 1395 case TT_ILL_INSN: 1396 { 1397 info.si_signo = TARGET_SIGILL; 1398 info.si_errno = 0; 1399 info.si_code = TARGET_ILL_ILLOPC; 1400 info._sifields._sigfault._addr = env->pc; 1401 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1402 } 1403 break; 1404 case EXCP_DEBUG: 1405 { 1406 int sig; 1407 1408 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1409 if (sig) 1410 { 1411 info.si_signo = sig; 1412 info.si_errno = 0; 1413 info.si_code = TARGET_TRAP_BRKPT; 1414 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1415 } 1416 } 1417 break; 1418 default: 1419 printf ("Unhandled trap: 0x%x\n", trapnr); 1420 cpu_dump_state(cs, stderr, fprintf, 0); 1421 exit(EXIT_FAILURE); 1422 } 1423 process_pending_signals (env); 1424 } 1425 } 1426 1427 #endif 1428 1429 #ifdef TARGET_PPC 1430 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1431 { 1432 return cpu_get_host_ticks(); 1433 } 1434 1435 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1436 { 1437 return cpu_ppc_get_tb(env); 1438 } 1439 1440 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1441 { 1442 return cpu_ppc_get_tb(env) >> 32; 1443 } 1444 1445 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1446 { 1447 return cpu_ppc_get_tb(env); 1448 } 1449 1450 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1451 { 1452 return cpu_ppc_get_tb(env) >> 32; 1453 } 1454 1455 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1456 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1457 1458 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1459 { 1460 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1461 } 1462 1463 /* XXX: to be fixed */ 1464 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1465 { 1466 return -1; 1467 } 1468 1469 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1470 { 1471 return -1; 1472 } 1473 1474 static int do_store_exclusive(CPUPPCState *env) 1475 { 1476 target_ulong addr; 1477 target_ulong page_addr; 1478 target_ulong val, val2 __attribute__((unused)) = 0; 1479 int flags; 1480 int segv = 0; 1481 1482 addr = env->reserve_ea; 1483 page_addr = addr & TARGET_PAGE_MASK; 1484 start_exclusive(); 1485 mmap_lock(); 1486 flags = page_get_flags(page_addr); 1487 if ((flags & PAGE_READ) == 0) { 1488 segv = 1; 1489 } else { 1490 int reg = env->reserve_info & 0x1f; 1491 int size = env->reserve_info >> 5; 1492 int stored = 0; 1493 1494 if (addr == env->reserve_addr) { 1495 switch (size) { 1496 case 1: segv = get_user_u8(val, addr); break; 1497 case 2: segv = get_user_u16(val, addr); break; 1498 case 4: segv = get_user_u32(val, addr); break; 1499 #if defined(TARGET_PPC64) 1500 case 8: segv = get_user_u64(val, addr); break; 1501 case 16: { 1502 segv = get_user_u64(val, addr); 1503 if (!segv) { 1504 segv = get_user_u64(val2, addr + 8); 1505 } 1506 break; 1507 } 1508 #endif 1509 default: abort(); 1510 } 1511 if (!segv && val == env->reserve_val) { 1512 val = env->gpr[reg]; 1513 switch (size) { 1514 case 1: segv = put_user_u8(val, addr); break; 1515 case 2: segv = put_user_u16(val, addr); break; 1516 case 4: segv = put_user_u32(val, addr); break; 1517 #if defined(TARGET_PPC64) 1518 case 8: segv = put_user_u64(val, addr); break; 1519 case 16: { 1520 if (val2 == env->reserve_val2) { 1521 if (msr_le) { 1522 val2 = val; 1523 val = env->gpr[reg+1]; 1524 } else { 1525 val2 = env->gpr[reg+1]; 1526 } 1527 segv = put_user_u64(val, addr); 1528 if (!segv) { 1529 segv = put_user_u64(val2, addr + 8); 1530 } 1531 } 1532 break; 1533 } 1534 #endif 1535 default: abort(); 1536 } 1537 if (!segv) { 1538 stored = 1; 1539 } 1540 } 1541 } 1542 env->crf[0] = (stored << 1) | xer_so; 1543 env->reserve_addr = (target_ulong)-1; 1544 } 1545 if (!segv) { 1546 env->nip += 4; 1547 } 1548 mmap_unlock(); 1549 end_exclusive(); 1550 return segv; 1551 } 1552 1553 void cpu_loop(CPUPPCState *env) 1554 { 1555 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1556 target_siginfo_t info; 1557 int trapnr; 1558 target_ulong ret; 1559 1560 for(;;) { 1561 cpu_exec_start(cs); 1562 trapnr = cpu_exec(cs); 1563 cpu_exec_end(cs); 1564 process_queued_cpu_work(cs); 1565 1566 switch(trapnr) { 1567 case POWERPC_EXCP_NONE: 1568 /* Just go on */ 1569 break; 1570 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1571 cpu_abort(cs, "Critical interrupt while in user mode. " 1572 "Aborting\n"); 1573 break; 1574 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1575 cpu_abort(cs, "Machine check exception while in user mode. " 1576 "Aborting\n"); 1577 break; 1578 case POWERPC_EXCP_DSI: /* Data storage exception */ 1579 /* XXX: check this. Seems bugged */ 1580 switch (env->error_code & 0xFF000000) { 1581 case 0x40000000: 1582 case 0x42000000: 1583 info.si_signo = TARGET_SIGSEGV; 1584 info.si_errno = 0; 1585 info.si_code = TARGET_SEGV_MAPERR; 1586 break; 1587 case 0x04000000: 1588 info.si_signo = TARGET_SIGILL; 1589 info.si_errno = 0; 1590 info.si_code = TARGET_ILL_ILLADR; 1591 break; 1592 case 0x08000000: 1593 info.si_signo = TARGET_SIGSEGV; 1594 info.si_errno = 0; 1595 info.si_code = TARGET_SEGV_ACCERR; 1596 break; 1597 default: 1598 /* Let's send a regular segfault... */ 1599 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1600 env->error_code); 1601 info.si_signo = TARGET_SIGSEGV; 1602 info.si_errno = 0; 1603 info.si_code = TARGET_SEGV_MAPERR; 1604 break; 1605 } 1606 info._sifields._sigfault._addr = env->nip; 1607 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1608 break; 1609 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1610 /* XXX: check this */ 1611 switch (env->error_code & 0xFF000000) { 1612 case 0x40000000: 1613 info.si_signo = TARGET_SIGSEGV; 1614 info.si_errno = 0; 1615 info.si_code = TARGET_SEGV_MAPERR; 1616 break; 1617 case 0x10000000: 1618 case 0x08000000: 1619 info.si_signo = TARGET_SIGSEGV; 1620 info.si_errno = 0; 1621 info.si_code = TARGET_SEGV_ACCERR; 1622 break; 1623 default: 1624 /* Let's send a regular segfault... */ 1625 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1626 env->error_code); 1627 info.si_signo = TARGET_SIGSEGV; 1628 info.si_errno = 0; 1629 info.si_code = TARGET_SEGV_MAPERR; 1630 break; 1631 } 1632 info._sifields._sigfault._addr = env->nip - 4; 1633 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1634 break; 1635 case POWERPC_EXCP_EXTERNAL: /* External input */ 1636 cpu_abort(cs, "External interrupt while in user mode. " 1637 "Aborting\n"); 1638 break; 1639 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1640 /* XXX: check this */ 1641 info.si_signo = TARGET_SIGBUS; 1642 info.si_errno = 0; 1643 info.si_code = TARGET_BUS_ADRALN; 1644 info._sifields._sigfault._addr = env->nip; 1645 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1646 break; 1647 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1648 case POWERPC_EXCP_HV_EMU: /* HV emulation */ 1649 /* XXX: check this */ 1650 switch (env->error_code & ~0xF) { 1651 case POWERPC_EXCP_FP: 1652 info.si_signo = TARGET_SIGFPE; 1653 info.si_errno = 0; 1654 switch (env->error_code & 0xF) { 1655 case POWERPC_EXCP_FP_OX: 1656 info.si_code = TARGET_FPE_FLTOVF; 1657 break; 1658 case POWERPC_EXCP_FP_UX: 1659 info.si_code = TARGET_FPE_FLTUND; 1660 break; 1661 case POWERPC_EXCP_FP_ZX: 1662 case POWERPC_EXCP_FP_VXZDZ: 1663 info.si_code = TARGET_FPE_FLTDIV; 1664 break; 1665 case POWERPC_EXCP_FP_XX: 1666 info.si_code = TARGET_FPE_FLTRES; 1667 break; 1668 case POWERPC_EXCP_FP_VXSOFT: 1669 info.si_code = TARGET_FPE_FLTINV; 1670 break; 1671 case POWERPC_EXCP_FP_VXSNAN: 1672 case POWERPC_EXCP_FP_VXISI: 1673 case POWERPC_EXCP_FP_VXIDI: 1674 case POWERPC_EXCP_FP_VXIMZ: 1675 case POWERPC_EXCP_FP_VXVC: 1676 case POWERPC_EXCP_FP_VXSQRT: 1677 case POWERPC_EXCP_FP_VXCVI: 1678 info.si_code = TARGET_FPE_FLTSUB; 1679 break; 1680 default: 1681 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1682 env->error_code); 1683 break; 1684 } 1685 break; 1686 case POWERPC_EXCP_INVAL: 1687 info.si_signo = TARGET_SIGILL; 1688 info.si_errno = 0; 1689 switch (env->error_code & 0xF) { 1690 case POWERPC_EXCP_INVAL_INVAL: 1691 info.si_code = TARGET_ILL_ILLOPC; 1692 break; 1693 case POWERPC_EXCP_INVAL_LSWX: 1694 info.si_code = TARGET_ILL_ILLOPN; 1695 break; 1696 case POWERPC_EXCP_INVAL_SPR: 1697 info.si_code = TARGET_ILL_PRVREG; 1698 break; 1699 case POWERPC_EXCP_INVAL_FP: 1700 info.si_code = TARGET_ILL_COPROC; 1701 break; 1702 default: 1703 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1704 env->error_code & 0xF); 1705 info.si_code = TARGET_ILL_ILLADR; 1706 break; 1707 } 1708 break; 1709 case POWERPC_EXCP_PRIV: 1710 info.si_signo = TARGET_SIGILL; 1711 info.si_errno = 0; 1712 switch (env->error_code & 0xF) { 1713 case POWERPC_EXCP_PRIV_OPC: 1714 info.si_code = TARGET_ILL_PRVOPC; 1715 break; 1716 case POWERPC_EXCP_PRIV_REG: 1717 info.si_code = TARGET_ILL_PRVREG; 1718 break; 1719 default: 1720 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1721 env->error_code & 0xF); 1722 info.si_code = TARGET_ILL_PRVOPC; 1723 break; 1724 } 1725 break; 1726 case POWERPC_EXCP_TRAP: 1727 cpu_abort(cs, "Tried to call a TRAP\n"); 1728 break; 1729 default: 1730 /* Should not happen ! */ 1731 cpu_abort(cs, "Unknown program exception (%02x)\n", 1732 env->error_code); 1733 break; 1734 } 1735 info._sifields._sigfault._addr = env->nip; 1736 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1737 break; 1738 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1739 info.si_signo = TARGET_SIGILL; 1740 info.si_errno = 0; 1741 info.si_code = TARGET_ILL_COPROC; 1742 info._sifields._sigfault._addr = env->nip; 1743 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1744 break; 1745 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1746 cpu_abort(cs, "Syscall exception while in user mode. " 1747 "Aborting\n"); 1748 break; 1749 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1750 info.si_signo = TARGET_SIGILL; 1751 info.si_errno = 0; 1752 info.si_code = TARGET_ILL_COPROC; 1753 info._sifields._sigfault._addr = env->nip; 1754 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1755 break; 1756 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1757 cpu_abort(cs, "Decrementer interrupt while in user mode. " 1758 "Aborting\n"); 1759 break; 1760 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1761 cpu_abort(cs, "Fix interval timer interrupt while in user mode. " 1762 "Aborting\n"); 1763 break; 1764 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1765 cpu_abort(cs, "Watchdog timer interrupt while in user mode. " 1766 "Aborting\n"); 1767 break; 1768 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1769 cpu_abort(cs, "Data TLB exception while in user mode. " 1770 "Aborting\n"); 1771 break; 1772 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1773 cpu_abort(cs, "Instruction TLB exception while in user mode. " 1774 "Aborting\n"); 1775 break; 1776 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1777 info.si_signo = TARGET_SIGILL; 1778 info.si_errno = 0; 1779 info.si_code = TARGET_ILL_COPROC; 1780 info._sifields._sigfault._addr = env->nip; 1781 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1782 break; 1783 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1784 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); 1785 break; 1786 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1787 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); 1788 break; 1789 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1790 cpu_abort(cs, "Performance monitor exception not handled\n"); 1791 break; 1792 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1793 cpu_abort(cs, "Doorbell interrupt while in user mode. " 1794 "Aborting\n"); 1795 break; 1796 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1797 cpu_abort(cs, "Doorbell critical interrupt while in user mode. " 1798 "Aborting\n"); 1799 break; 1800 case POWERPC_EXCP_RESET: /* System reset exception */ 1801 cpu_abort(cs, "Reset interrupt while in user mode. " 1802 "Aborting\n"); 1803 break; 1804 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1805 cpu_abort(cs, "Data segment exception while in user mode. " 1806 "Aborting\n"); 1807 break; 1808 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1809 cpu_abort(cs, "Instruction segment exception " 1810 "while in user mode. Aborting\n"); 1811 break; 1812 /* PowerPC 64 with hypervisor mode support */ 1813 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1814 cpu_abort(cs, "Hypervisor decrementer interrupt " 1815 "while in user mode. Aborting\n"); 1816 break; 1817 case POWERPC_EXCP_TRACE: /* Trace exception */ 1818 /* Nothing to do: 1819 * we use this exception to emulate step-by-step execution mode. 1820 */ 1821 break; 1822 /* PowerPC 64 with hypervisor mode support */ 1823 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1824 cpu_abort(cs, "Hypervisor data storage exception " 1825 "while in user mode. Aborting\n"); 1826 break; 1827 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1828 cpu_abort(cs, "Hypervisor instruction storage exception " 1829 "while in user mode. Aborting\n"); 1830 break; 1831 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1832 cpu_abort(cs, "Hypervisor data segment exception " 1833 "while in user mode. Aborting\n"); 1834 break; 1835 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1836 cpu_abort(cs, "Hypervisor instruction segment exception " 1837 "while in user mode. Aborting\n"); 1838 break; 1839 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1840 info.si_signo = TARGET_SIGILL; 1841 info.si_errno = 0; 1842 info.si_code = TARGET_ILL_COPROC; 1843 info._sifields._sigfault._addr = env->nip; 1844 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1845 break; 1846 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1847 cpu_abort(cs, "Programmable interval timer interrupt " 1848 "while in user mode. Aborting\n"); 1849 break; 1850 case POWERPC_EXCP_IO: /* IO error exception */ 1851 cpu_abort(cs, "IO error exception while in user mode. " 1852 "Aborting\n"); 1853 break; 1854 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1855 cpu_abort(cs, "Run mode exception while in user mode. " 1856 "Aborting\n"); 1857 break; 1858 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1859 cpu_abort(cs, "Emulation trap exception not handled\n"); 1860 break; 1861 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1862 cpu_abort(cs, "Instruction fetch TLB exception " 1863 "while in user-mode. Aborting"); 1864 break; 1865 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1866 cpu_abort(cs, "Data load TLB exception while in user-mode. " 1867 "Aborting"); 1868 break; 1869 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1870 cpu_abort(cs, "Data store TLB exception while in user-mode. " 1871 "Aborting"); 1872 break; 1873 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1874 cpu_abort(cs, "Floating-point assist exception not handled\n"); 1875 break; 1876 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1877 cpu_abort(cs, "Instruction address breakpoint exception " 1878 "not handled\n"); 1879 break; 1880 case POWERPC_EXCP_SMI: /* System management interrupt */ 1881 cpu_abort(cs, "System management interrupt while in user mode. " 1882 "Aborting\n"); 1883 break; 1884 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1885 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " 1886 "Aborting\n"); 1887 break; 1888 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1889 cpu_abort(cs, "Performance monitor exception not handled\n"); 1890 break; 1891 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1892 cpu_abort(cs, "Vector assist exception not handled\n"); 1893 break; 1894 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1895 cpu_abort(cs, "Soft patch exception not handled\n"); 1896 break; 1897 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1898 cpu_abort(cs, "Maintenance exception while in user mode. " 1899 "Aborting\n"); 1900 break; 1901 case POWERPC_EXCP_STOP: /* stop translation */ 1902 /* We did invalidate the instruction cache. Go on */ 1903 break; 1904 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1905 /* We just stopped because of a branch. Go on */ 1906 break; 1907 case POWERPC_EXCP_SYSCALL_USER: 1908 /* system call in user-mode emulation */ 1909 /* WARNING: 1910 * PPC ABI uses overflow flag in cr0 to signal an error 1911 * in syscalls. 1912 */ 1913 env->crf[0] &= ~0x1; 1914 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1915 env->gpr[5], env->gpr[6], env->gpr[7], 1916 env->gpr[8], 0, 0); 1917 if (ret == -TARGET_ERESTARTSYS) { 1918 break; 1919 } 1920 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1921 /* Returning from a successful sigreturn syscall. 1922 Avoid corrupting register state. */ 1923 break; 1924 } 1925 env->nip += 4; 1926 if (ret > (target_ulong)(-515)) { 1927 env->crf[0] |= 0x1; 1928 ret = -ret; 1929 } 1930 env->gpr[3] = ret; 1931 break; 1932 case POWERPC_EXCP_STCX: 1933 if (do_store_exclusive(env)) { 1934 info.si_signo = TARGET_SIGSEGV; 1935 info.si_errno = 0; 1936 info.si_code = TARGET_SEGV_MAPERR; 1937 info._sifields._sigfault._addr = env->nip; 1938 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1939 } 1940 break; 1941 case EXCP_DEBUG: 1942 { 1943 int sig; 1944 1945 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1946 if (sig) { 1947 info.si_signo = sig; 1948 info.si_errno = 0; 1949 info.si_code = TARGET_TRAP_BRKPT; 1950 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1951 } 1952 } 1953 break; 1954 case EXCP_INTERRUPT: 1955 /* just indicate that signals should be handled asap */ 1956 break; 1957 default: 1958 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); 1959 break; 1960 } 1961 process_pending_signals(env); 1962 } 1963 } 1964 #endif 1965 1966 #ifdef TARGET_MIPS 1967 1968 # ifdef TARGET_ABI_MIPSO32 1969 # define MIPS_SYS(name, args) args, 1970 static const uint8_t mips_syscall_args[] = { 1971 MIPS_SYS(sys_syscall , 8) /* 4000 */ 1972 MIPS_SYS(sys_exit , 1) 1973 MIPS_SYS(sys_fork , 0) 1974 MIPS_SYS(sys_read , 3) 1975 MIPS_SYS(sys_write , 3) 1976 MIPS_SYS(sys_open , 3) /* 4005 */ 1977 MIPS_SYS(sys_close , 1) 1978 MIPS_SYS(sys_waitpid , 3) 1979 MIPS_SYS(sys_creat , 2) 1980 MIPS_SYS(sys_link , 2) 1981 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1982 MIPS_SYS(sys_execve , 0) 1983 MIPS_SYS(sys_chdir , 1) 1984 MIPS_SYS(sys_time , 1) 1985 MIPS_SYS(sys_mknod , 3) 1986 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1987 MIPS_SYS(sys_lchown , 3) 1988 MIPS_SYS(sys_ni_syscall , 0) 1989 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1990 MIPS_SYS(sys_lseek , 3) 1991 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1992 MIPS_SYS(sys_mount , 5) 1993 MIPS_SYS(sys_umount , 1) 1994 MIPS_SYS(sys_setuid , 1) 1995 MIPS_SYS(sys_getuid , 0) 1996 MIPS_SYS(sys_stime , 1) /* 4025 */ 1997 MIPS_SYS(sys_ptrace , 4) 1998 MIPS_SYS(sys_alarm , 1) 1999 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 2000 MIPS_SYS(sys_pause , 0) 2001 MIPS_SYS(sys_utime , 2) /* 4030 */ 2002 MIPS_SYS(sys_ni_syscall , 0) 2003 MIPS_SYS(sys_ni_syscall , 0) 2004 MIPS_SYS(sys_access , 2) 2005 MIPS_SYS(sys_nice , 1) 2006 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 2007 MIPS_SYS(sys_sync , 0) 2008 MIPS_SYS(sys_kill , 2) 2009 MIPS_SYS(sys_rename , 2) 2010 MIPS_SYS(sys_mkdir , 2) 2011 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 2012 MIPS_SYS(sys_dup , 1) 2013 MIPS_SYS(sys_pipe , 0) 2014 MIPS_SYS(sys_times , 1) 2015 MIPS_SYS(sys_ni_syscall , 0) 2016 MIPS_SYS(sys_brk , 1) /* 4045 */ 2017 MIPS_SYS(sys_setgid , 1) 2018 MIPS_SYS(sys_getgid , 0) 2019 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 2020 MIPS_SYS(sys_geteuid , 0) 2021 MIPS_SYS(sys_getegid , 0) /* 4050 */ 2022 MIPS_SYS(sys_acct , 0) 2023 MIPS_SYS(sys_umount2 , 2) 2024 MIPS_SYS(sys_ni_syscall , 0) 2025 MIPS_SYS(sys_ioctl , 3) 2026 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 2027 MIPS_SYS(sys_ni_syscall , 2) 2028 MIPS_SYS(sys_setpgid , 2) 2029 MIPS_SYS(sys_ni_syscall , 0) 2030 MIPS_SYS(sys_olduname , 1) 2031 MIPS_SYS(sys_umask , 1) /* 4060 */ 2032 MIPS_SYS(sys_chroot , 1) 2033 MIPS_SYS(sys_ustat , 2) 2034 MIPS_SYS(sys_dup2 , 2) 2035 MIPS_SYS(sys_getppid , 0) 2036 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 2037 MIPS_SYS(sys_setsid , 0) 2038 MIPS_SYS(sys_sigaction , 3) 2039 MIPS_SYS(sys_sgetmask , 0) 2040 MIPS_SYS(sys_ssetmask , 1) 2041 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 2042 MIPS_SYS(sys_setregid , 2) 2043 MIPS_SYS(sys_sigsuspend , 0) 2044 MIPS_SYS(sys_sigpending , 1) 2045 MIPS_SYS(sys_sethostname , 2) 2046 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 2047 MIPS_SYS(sys_getrlimit , 2) 2048 MIPS_SYS(sys_getrusage , 2) 2049 MIPS_SYS(sys_gettimeofday, 2) 2050 MIPS_SYS(sys_settimeofday, 2) 2051 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 2052 MIPS_SYS(sys_setgroups , 2) 2053 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 2054 MIPS_SYS(sys_symlink , 2) 2055 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 2056 MIPS_SYS(sys_readlink , 3) /* 4085 */ 2057 MIPS_SYS(sys_uselib , 1) 2058 MIPS_SYS(sys_swapon , 2) 2059 MIPS_SYS(sys_reboot , 3) 2060 MIPS_SYS(old_readdir , 3) 2061 MIPS_SYS(old_mmap , 6) /* 4090 */ 2062 MIPS_SYS(sys_munmap , 2) 2063 MIPS_SYS(sys_truncate , 2) 2064 MIPS_SYS(sys_ftruncate , 2) 2065 MIPS_SYS(sys_fchmod , 2) 2066 MIPS_SYS(sys_fchown , 3) /* 4095 */ 2067 MIPS_SYS(sys_getpriority , 2) 2068 MIPS_SYS(sys_setpriority , 3) 2069 MIPS_SYS(sys_ni_syscall , 0) 2070 MIPS_SYS(sys_statfs , 2) 2071 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 2072 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 2073 MIPS_SYS(sys_socketcall , 2) 2074 MIPS_SYS(sys_syslog , 3) 2075 MIPS_SYS(sys_setitimer , 3) 2076 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 2077 MIPS_SYS(sys_newstat , 2) 2078 MIPS_SYS(sys_newlstat , 2) 2079 MIPS_SYS(sys_newfstat , 2) 2080 MIPS_SYS(sys_uname , 1) 2081 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 2082 MIPS_SYS(sys_vhangup , 0) 2083 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 2084 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 2085 MIPS_SYS(sys_wait4 , 4) 2086 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 2087 MIPS_SYS(sys_sysinfo , 1) 2088 MIPS_SYS(sys_ipc , 6) 2089 MIPS_SYS(sys_fsync , 1) 2090 MIPS_SYS(sys_sigreturn , 0) 2091 MIPS_SYS(sys_clone , 6) /* 4120 */ 2092 MIPS_SYS(sys_setdomainname, 2) 2093 MIPS_SYS(sys_newuname , 1) 2094 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 2095 MIPS_SYS(sys_adjtimex , 1) 2096 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 2097 MIPS_SYS(sys_sigprocmask , 3) 2098 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 2099 MIPS_SYS(sys_init_module , 5) 2100 MIPS_SYS(sys_delete_module, 1) 2101 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 2102 MIPS_SYS(sys_quotactl , 0) 2103 MIPS_SYS(sys_getpgid , 1) 2104 MIPS_SYS(sys_fchdir , 1) 2105 MIPS_SYS(sys_bdflush , 2) 2106 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 2107 MIPS_SYS(sys_personality , 1) 2108 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 2109 MIPS_SYS(sys_setfsuid , 1) 2110 MIPS_SYS(sys_setfsgid , 1) 2111 MIPS_SYS(sys_llseek , 5) /* 4140 */ 2112 MIPS_SYS(sys_getdents , 3) 2113 MIPS_SYS(sys_select , 5) 2114 MIPS_SYS(sys_flock , 2) 2115 MIPS_SYS(sys_msync , 3) 2116 MIPS_SYS(sys_readv , 3) /* 4145 */ 2117 MIPS_SYS(sys_writev , 3) 2118 MIPS_SYS(sys_cacheflush , 3) 2119 MIPS_SYS(sys_cachectl , 3) 2120 MIPS_SYS(sys_sysmips , 4) 2121 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 2122 MIPS_SYS(sys_getsid , 1) 2123 MIPS_SYS(sys_fdatasync , 0) 2124 MIPS_SYS(sys_sysctl , 1) 2125 MIPS_SYS(sys_mlock , 2) 2126 MIPS_SYS(sys_munlock , 2) /* 4155 */ 2127 MIPS_SYS(sys_mlockall , 1) 2128 MIPS_SYS(sys_munlockall , 0) 2129 MIPS_SYS(sys_sched_setparam, 2) 2130 MIPS_SYS(sys_sched_getparam, 2) 2131 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 2132 MIPS_SYS(sys_sched_getscheduler, 1) 2133 MIPS_SYS(sys_sched_yield , 0) 2134 MIPS_SYS(sys_sched_get_priority_max, 1) 2135 MIPS_SYS(sys_sched_get_priority_min, 1) 2136 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 2137 MIPS_SYS(sys_nanosleep, 2) 2138 MIPS_SYS(sys_mremap , 5) 2139 MIPS_SYS(sys_accept , 3) 2140 MIPS_SYS(sys_bind , 3) 2141 MIPS_SYS(sys_connect , 3) /* 4170 */ 2142 MIPS_SYS(sys_getpeername , 3) 2143 MIPS_SYS(sys_getsockname , 3) 2144 MIPS_SYS(sys_getsockopt , 5) 2145 MIPS_SYS(sys_listen , 2) 2146 MIPS_SYS(sys_recv , 4) /* 4175 */ 2147 MIPS_SYS(sys_recvfrom , 6) 2148 MIPS_SYS(sys_recvmsg , 3) 2149 MIPS_SYS(sys_send , 4) 2150 MIPS_SYS(sys_sendmsg , 3) 2151 MIPS_SYS(sys_sendto , 6) /* 4180 */ 2152 MIPS_SYS(sys_setsockopt , 5) 2153 MIPS_SYS(sys_shutdown , 2) 2154 MIPS_SYS(sys_socket , 3) 2155 MIPS_SYS(sys_socketpair , 4) 2156 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 2157 MIPS_SYS(sys_getresuid , 3) 2158 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 2159 MIPS_SYS(sys_poll , 3) 2160 MIPS_SYS(sys_nfsservctl , 3) 2161 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 2162 MIPS_SYS(sys_getresgid , 3) 2163 MIPS_SYS(sys_prctl , 5) 2164 MIPS_SYS(sys_rt_sigreturn, 0) 2165 MIPS_SYS(sys_rt_sigaction, 4) 2166 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 2167 MIPS_SYS(sys_rt_sigpending, 2) 2168 MIPS_SYS(sys_rt_sigtimedwait, 4) 2169 MIPS_SYS(sys_rt_sigqueueinfo, 3) 2170 MIPS_SYS(sys_rt_sigsuspend, 0) 2171 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 2172 MIPS_SYS(sys_pwrite64 , 6) 2173 MIPS_SYS(sys_chown , 3) 2174 MIPS_SYS(sys_getcwd , 2) 2175 MIPS_SYS(sys_capget , 2) 2176 MIPS_SYS(sys_capset , 2) /* 4205 */ 2177 MIPS_SYS(sys_sigaltstack , 2) 2178 MIPS_SYS(sys_sendfile , 4) 2179 MIPS_SYS(sys_ni_syscall , 0) 2180 MIPS_SYS(sys_ni_syscall , 0) 2181 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2182 MIPS_SYS(sys_truncate64 , 4) 2183 MIPS_SYS(sys_ftruncate64 , 4) 2184 MIPS_SYS(sys_stat64 , 2) 2185 MIPS_SYS(sys_lstat64 , 2) 2186 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2187 MIPS_SYS(sys_pivot_root , 2) 2188 MIPS_SYS(sys_mincore , 3) 2189 MIPS_SYS(sys_madvise , 3) 2190 MIPS_SYS(sys_getdents64 , 3) 2191 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2192 MIPS_SYS(sys_ni_syscall , 0) 2193 MIPS_SYS(sys_gettid , 0) 2194 MIPS_SYS(sys_readahead , 5) 2195 MIPS_SYS(sys_setxattr , 5) 2196 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2197 MIPS_SYS(sys_fsetxattr , 5) 2198 MIPS_SYS(sys_getxattr , 4) 2199 MIPS_SYS(sys_lgetxattr , 4) 2200 MIPS_SYS(sys_fgetxattr , 4) 2201 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2202 MIPS_SYS(sys_llistxattr , 3) 2203 MIPS_SYS(sys_flistxattr , 3) 2204 MIPS_SYS(sys_removexattr , 2) 2205 MIPS_SYS(sys_lremovexattr, 2) 2206 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2207 MIPS_SYS(sys_tkill , 2) 2208 MIPS_SYS(sys_sendfile64 , 5) 2209 MIPS_SYS(sys_futex , 6) 2210 MIPS_SYS(sys_sched_setaffinity, 3) 2211 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2212 MIPS_SYS(sys_io_setup , 2) 2213 MIPS_SYS(sys_io_destroy , 1) 2214 MIPS_SYS(sys_io_getevents, 5) 2215 MIPS_SYS(sys_io_submit , 3) 2216 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2217 MIPS_SYS(sys_exit_group , 1) 2218 MIPS_SYS(sys_lookup_dcookie, 3) 2219 MIPS_SYS(sys_epoll_create, 1) 2220 MIPS_SYS(sys_epoll_ctl , 4) 2221 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2222 MIPS_SYS(sys_remap_file_pages, 5) 2223 MIPS_SYS(sys_set_tid_address, 1) 2224 MIPS_SYS(sys_restart_syscall, 0) 2225 MIPS_SYS(sys_fadvise64_64, 7) 2226 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2227 MIPS_SYS(sys_fstatfs64 , 2) 2228 MIPS_SYS(sys_timer_create, 3) 2229 MIPS_SYS(sys_timer_settime, 4) 2230 MIPS_SYS(sys_timer_gettime, 2) 2231 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2232 MIPS_SYS(sys_timer_delete, 1) 2233 MIPS_SYS(sys_clock_settime, 2) 2234 MIPS_SYS(sys_clock_gettime, 2) 2235 MIPS_SYS(sys_clock_getres, 2) 2236 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2237 MIPS_SYS(sys_tgkill , 3) 2238 MIPS_SYS(sys_utimes , 2) 2239 MIPS_SYS(sys_mbind , 4) 2240 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2241 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2242 MIPS_SYS(sys_mq_open , 4) 2243 MIPS_SYS(sys_mq_unlink , 1) 2244 MIPS_SYS(sys_mq_timedsend, 5) 2245 MIPS_SYS(sys_mq_timedreceive, 5) 2246 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2247 MIPS_SYS(sys_mq_getsetattr, 3) 2248 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2249 MIPS_SYS(sys_waitid , 4) 2250 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2251 MIPS_SYS(sys_add_key , 5) 2252 MIPS_SYS(sys_request_key, 4) 2253 MIPS_SYS(sys_keyctl , 5) 2254 MIPS_SYS(sys_set_thread_area, 1) 2255 MIPS_SYS(sys_inotify_init, 0) 2256 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2257 MIPS_SYS(sys_inotify_rm_watch, 2) 2258 MIPS_SYS(sys_migrate_pages, 4) 2259 MIPS_SYS(sys_openat, 4) 2260 MIPS_SYS(sys_mkdirat, 3) 2261 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2262 MIPS_SYS(sys_fchownat, 5) 2263 MIPS_SYS(sys_futimesat, 3) 2264 MIPS_SYS(sys_fstatat64, 4) 2265 MIPS_SYS(sys_unlinkat, 3) 2266 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2267 MIPS_SYS(sys_linkat, 5) 2268 MIPS_SYS(sys_symlinkat, 3) 2269 MIPS_SYS(sys_readlinkat, 4) 2270 MIPS_SYS(sys_fchmodat, 3) 2271 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2272 MIPS_SYS(sys_pselect6, 6) 2273 MIPS_SYS(sys_ppoll, 5) 2274 MIPS_SYS(sys_unshare, 1) 2275 MIPS_SYS(sys_splice, 6) 2276 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2277 MIPS_SYS(sys_tee, 4) 2278 MIPS_SYS(sys_vmsplice, 4) 2279 MIPS_SYS(sys_move_pages, 6) 2280 MIPS_SYS(sys_set_robust_list, 2) 2281 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2282 MIPS_SYS(sys_kexec_load, 4) 2283 MIPS_SYS(sys_getcpu, 3) 2284 MIPS_SYS(sys_epoll_pwait, 6) 2285 MIPS_SYS(sys_ioprio_set, 3) 2286 MIPS_SYS(sys_ioprio_get, 2) 2287 MIPS_SYS(sys_utimensat, 4) 2288 MIPS_SYS(sys_signalfd, 3) 2289 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2290 MIPS_SYS(sys_eventfd, 1) 2291 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2292 MIPS_SYS(sys_timerfd_create, 2) 2293 MIPS_SYS(sys_timerfd_gettime, 2) 2294 MIPS_SYS(sys_timerfd_settime, 4) 2295 MIPS_SYS(sys_signalfd4, 4) 2296 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2297 MIPS_SYS(sys_epoll_create1, 1) 2298 MIPS_SYS(sys_dup3, 3) 2299 MIPS_SYS(sys_pipe2, 2) 2300 MIPS_SYS(sys_inotify_init1, 1) 2301 MIPS_SYS(sys_preadv, 5) /* 4330 */ 2302 MIPS_SYS(sys_pwritev, 5) 2303 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2304 MIPS_SYS(sys_perf_event_open, 5) 2305 MIPS_SYS(sys_accept4, 4) 2306 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2307 MIPS_SYS(sys_fanotify_init, 2) 2308 MIPS_SYS(sys_fanotify_mark, 6) 2309 MIPS_SYS(sys_prlimit64, 4) 2310 MIPS_SYS(sys_name_to_handle_at, 5) 2311 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2312 MIPS_SYS(sys_clock_adjtime, 2) 2313 MIPS_SYS(sys_syncfs, 1) 2314 MIPS_SYS(sys_sendmmsg, 4) 2315 MIPS_SYS(sys_setns, 2) 2316 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */ 2317 MIPS_SYS(sys_process_vm_writev, 6) 2318 MIPS_SYS(sys_kcmp, 5) 2319 MIPS_SYS(sys_finit_module, 3) 2320 MIPS_SYS(sys_sched_setattr, 2) 2321 MIPS_SYS(sys_sched_getattr, 3) /* 350 */ 2322 MIPS_SYS(sys_renameat2, 5) 2323 MIPS_SYS(sys_seccomp, 3) 2324 MIPS_SYS(sys_getrandom, 3) 2325 MIPS_SYS(sys_memfd_create, 2) 2326 MIPS_SYS(sys_bpf, 3) /* 355 */ 2327 MIPS_SYS(sys_execveat, 5) 2328 MIPS_SYS(sys_userfaultfd, 1) 2329 MIPS_SYS(sys_membarrier, 2) 2330 MIPS_SYS(sys_mlock2, 3) 2331 MIPS_SYS(sys_copy_file_range, 6) /* 360 */ 2332 MIPS_SYS(sys_preadv2, 6) 2333 MIPS_SYS(sys_pwritev2, 6) 2334 }; 2335 # undef MIPS_SYS 2336 # endif /* O32 */ 2337 2338 static int do_store_exclusive(CPUMIPSState *env) 2339 { 2340 target_ulong addr; 2341 target_ulong page_addr; 2342 target_ulong val; 2343 int flags; 2344 int segv = 0; 2345 int reg; 2346 int d; 2347 2348 addr = env->lladdr; 2349 page_addr = addr & TARGET_PAGE_MASK; 2350 start_exclusive(); 2351 mmap_lock(); 2352 flags = page_get_flags(page_addr); 2353 if ((flags & PAGE_READ) == 0) { 2354 segv = 1; 2355 } else { 2356 reg = env->llreg & 0x1f; 2357 d = (env->llreg & 0x20) != 0; 2358 if (d) { 2359 segv = get_user_s64(val, addr); 2360 } else { 2361 segv = get_user_s32(val, addr); 2362 } 2363 if (!segv) { 2364 if (val != env->llval) { 2365 env->active_tc.gpr[reg] = 0; 2366 } else { 2367 if (d) { 2368 segv = put_user_u64(env->llnewval, addr); 2369 } else { 2370 segv = put_user_u32(env->llnewval, addr); 2371 } 2372 if (!segv) { 2373 env->active_tc.gpr[reg] = 1; 2374 } 2375 } 2376 } 2377 } 2378 env->lladdr = -1; 2379 if (!segv) { 2380 env->active_tc.PC += 4; 2381 } 2382 mmap_unlock(); 2383 end_exclusive(); 2384 return segv; 2385 } 2386 2387 /* Break codes */ 2388 enum { 2389 BRK_OVERFLOW = 6, 2390 BRK_DIVZERO = 7 2391 }; 2392 2393 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2394 unsigned int code) 2395 { 2396 int ret = -1; 2397 2398 switch (code) { 2399 case BRK_OVERFLOW: 2400 case BRK_DIVZERO: 2401 info->si_signo = TARGET_SIGFPE; 2402 info->si_errno = 0; 2403 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2404 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 2405 ret = 0; 2406 break; 2407 default: 2408 info->si_signo = TARGET_SIGTRAP; 2409 info->si_errno = 0; 2410 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 2411 ret = 0; 2412 break; 2413 } 2414 2415 return ret; 2416 } 2417 2418 void cpu_loop(CPUMIPSState *env) 2419 { 2420 CPUState *cs = CPU(mips_env_get_cpu(env)); 2421 target_siginfo_t info; 2422 int trapnr; 2423 abi_long ret; 2424 # ifdef TARGET_ABI_MIPSO32 2425 unsigned int syscall_num; 2426 # endif 2427 2428 for(;;) { 2429 cpu_exec_start(cs); 2430 trapnr = cpu_exec(cs); 2431 cpu_exec_end(cs); 2432 process_queued_cpu_work(cs); 2433 2434 switch(trapnr) { 2435 case EXCP_SYSCALL: 2436 env->active_tc.PC += 4; 2437 # ifdef TARGET_ABI_MIPSO32 2438 syscall_num = env->active_tc.gpr[2] - 4000; 2439 if (syscall_num >= sizeof(mips_syscall_args)) { 2440 ret = -TARGET_ENOSYS; 2441 } else { 2442 int nb_args; 2443 abi_ulong sp_reg; 2444 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2445 2446 nb_args = mips_syscall_args[syscall_num]; 2447 sp_reg = env->active_tc.gpr[29]; 2448 switch (nb_args) { 2449 /* these arguments are taken from the stack */ 2450 case 8: 2451 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2452 goto done_syscall; 2453 } 2454 case 7: 2455 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2456 goto done_syscall; 2457 } 2458 case 6: 2459 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2460 goto done_syscall; 2461 } 2462 case 5: 2463 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2464 goto done_syscall; 2465 } 2466 default: 2467 break; 2468 } 2469 ret = do_syscall(env, env->active_tc.gpr[2], 2470 env->active_tc.gpr[4], 2471 env->active_tc.gpr[5], 2472 env->active_tc.gpr[6], 2473 env->active_tc.gpr[7], 2474 arg5, arg6, arg7, arg8); 2475 } 2476 done_syscall: 2477 # else 2478 ret = do_syscall(env, env->active_tc.gpr[2], 2479 env->active_tc.gpr[4], env->active_tc.gpr[5], 2480 env->active_tc.gpr[6], env->active_tc.gpr[7], 2481 env->active_tc.gpr[8], env->active_tc.gpr[9], 2482 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2483 # endif /* O32 */ 2484 if (ret == -TARGET_ERESTARTSYS) { 2485 env->active_tc.PC -= 4; 2486 break; 2487 } 2488 if (ret == -TARGET_QEMU_ESIGRETURN) { 2489 /* Returning from a successful sigreturn syscall. 2490 Avoid clobbering register state. */ 2491 break; 2492 } 2493 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2494 env->active_tc.gpr[7] = 1; /* error flag */ 2495 ret = -ret; 2496 } else { 2497 env->active_tc.gpr[7] = 0; /* error flag */ 2498 } 2499 env->active_tc.gpr[2] = ret; 2500 break; 2501 case EXCP_TLBL: 2502 case EXCP_TLBS: 2503 case EXCP_AdEL: 2504 case EXCP_AdES: 2505 info.si_signo = TARGET_SIGSEGV; 2506 info.si_errno = 0; 2507 /* XXX: check env->error_code */ 2508 info.si_code = TARGET_SEGV_MAPERR; 2509 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2510 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2511 break; 2512 case EXCP_CpU: 2513 case EXCP_RI: 2514 info.si_signo = TARGET_SIGILL; 2515 info.si_errno = 0; 2516 info.si_code = 0; 2517 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2518 break; 2519 case EXCP_INTERRUPT: 2520 /* just indicate that signals should be handled asap */ 2521 break; 2522 case EXCP_DEBUG: 2523 { 2524 int sig; 2525 2526 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2527 if (sig) 2528 { 2529 info.si_signo = sig; 2530 info.si_errno = 0; 2531 info.si_code = TARGET_TRAP_BRKPT; 2532 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2533 } 2534 } 2535 break; 2536 case EXCP_SC: 2537 if (do_store_exclusive(env)) { 2538 info.si_signo = TARGET_SIGSEGV; 2539 info.si_errno = 0; 2540 info.si_code = TARGET_SEGV_MAPERR; 2541 info._sifields._sigfault._addr = env->active_tc.PC; 2542 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2543 } 2544 break; 2545 case EXCP_DSPDIS: 2546 info.si_signo = TARGET_SIGILL; 2547 info.si_errno = 0; 2548 info.si_code = TARGET_ILL_ILLOPC; 2549 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2550 break; 2551 /* The code below was inspired by the MIPS Linux kernel trap 2552 * handling code in arch/mips/kernel/traps.c. 2553 */ 2554 case EXCP_BREAK: 2555 { 2556 abi_ulong trap_instr; 2557 unsigned int code; 2558 2559 if (env->hflags & MIPS_HFLAG_M16) { 2560 if (env->insn_flags & ASE_MICROMIPS) { 2561 /* microMIPS mode */ 2562 ret = get_user_u16(trap_instr, env->active_tc.PC); 2563 if (ret != 0) { 2564 goto error; 2565 } 2566 2567 if ((trap_instr >> 10) == 0x11) { 2568 /* 16-bit instruction */ 2569 code = trap_instr & 0xf; 2570 } else { 2571 /* 32-bit instruction */ 2572 abi_ulong instr_lo; 2573 2574 ret = get_user_u16(instr_lo, 2575 env->active_tc.PC + 2); 2576 if (ret != 0) { 2577 goto error; 2578 } 2579 trap_instr = (trap_instr << 16) | instr_lo; 2580 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2581 /* Unfortunately, microMIPS also suffers from 2582 the old assembler bug... */ 2583 if (code >= (1 << 10)) { 2584 code >>= 10; 2585 } 2586 } 2587 } else { 2588 /* MIPS16e mode */ 2589 ret = get_user_u16(trap_instr, env->active_tc.PC); 2590 if (ret != 0) { 2591 goto error; 2592 } 2593 code = (trap_instr >> 6) & 0x3f; 2594 } 2595 } else { 2596 ret = get_user_u32(trap_instr, env->active_tc.PC); 2597 if (ret != 0) { 2598 goto error; 2599 } 2600 2601 /* As described in the original Linux kernel code, the 2602 * below checks on 'code' are to work around an old 2603 * assembly bug. 2604 */ 2605 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2606 if (code >= (1 << 10)) { 2607 code >>= 10; 2608 } 2609 } 2610 2611 if (do_break(env, &info, code) != 0) { 2612 goto error; 2613 } 2614 } 2615 break; 2616 case EXCP_TRAP: 2617 { 2618 abi_ulong trap_instr; 2619 unsigned int code = 0; 2620 2621 if (env->hflags & MIPS_HFLAG_M16) { 2622 /* microMIPS mode */ 2623 abi_ulong instr[2]; 2624 2625 ret = get_user_u16(instr[0], env->active_tc.PC) || 2626 get_user_u16(instr[1], env->active_tc.PC + 2); 2627 2628 trap_instr = (instr[0] << 16) | instr[1]; 2629 } else { 2630 ret = get_user_u32(trap_instr, env->active_tc.PC); 2631 } 2632 2633 if (ret != 0) { 2634 goto error; 2635 } 2636 2637 /* The immediate versions don't provide a code. */ 2638 if (!(trap_instr & 0xFC000000)) { 2639 if (env->hflags & MIPS_HFLAG_M16) { 2640 /* microMIPS mode */ 2641 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 2642 } else { 2643 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2644 } 2645 } 2646 2647 if (do_break(env, &info, code) != 0) { 2648 goto error; 2649 } 2650 } 2651 break; 2652 default: 2653 error: 2654 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 2655 abort(); 2656 } 2657 process_pending_signals(env); 2658 } 2659 } 2660 #endif 2661 2662 #ifdef TARGET_OPENRISC 2663 2664 void cpu_loop(CPUOpenRISCState *env) 2665 { 2666 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2667 int trapnr, gdbsig; 2668 abi_long ret; 2669 2670 for (;;) { 2671 cpu_exec_start(cs); 2672 trapnr = cpu_exec(cs); 2673 cpu_exec_end(cs); 2674 process_queued_cpu_work(cs); 2675 gdbsig = 0; 2676 2677 switch (trapnr) { 2678 case EXCP_RESET: 2679 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc); 2680 exit(EXIT_FAILURE); 2681 break; 2682 case EXCP_BUSERR: 2683 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc); 2684 gdbsig = TARGET_SIGBUS; 2685 break; 2686 case EXCP_DPF: 2687 case EXCP_IPF: 2688 cpu_dump_state(cs, stderr, fprintf, 0); 2689 gdbsig = TARGET_SIGSEGV; 2690 break; 2691 case EXCP_TICK: 2692 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc); 2693 break; 2694 case EXCP_ALIGN: 2695 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc); 2696 gdbsig = TARGET_SIGBUS; 2697 break; 2698 case EXCP_ILLEGAL: 2699 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc); 2700 gdbsig = TARGET_SIGILL; 2701 break; 2702 case EXCP_INT: 2703 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc); 2704 break; 2705 case EXCP_DTLBMISS: 2706 case EXCP_ITLBMISS: 2707 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n"); 2708 break; 2709 case EXCP_RANGE: 2710 qemu_log_mask(CPU_LOG_INT, "\nRange\n"); 2711 gdbsig = TARGET_SIGSEGV; 2712 break; 2713 case EXCP_SYSCALL: 2714 env->pc += 4; /* 0xc00; */ 2715 ret = do_syscall(env, 2716 env->gpr[11], /* return value */ 2717 env->gpr[3], /* r3 - r7 are params */ 2718 env->gpr[4], 2719 env->gpr[5], 2720 env->gpr[6], 2721 env->gpr[7], 2722 env->gpr[8], 0, 0); 2723 if (ret == -TARGET_ERESTARTSYS) { 2724 env->pc -= 4; 2725 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2726 env->gpr[11] = ret; 2727 } 2728 break; 2729 case EXCP_FPE: 2730 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n"); 2731 break; 2732 case EXCP_TRAP: 2733 qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); 2734 gdbsig = TARGET_SIGTRAP; 2735 break; 2736 case EXCP_NR: 2737 qemu_log_mask(CPU_LOG_INT, "\nNR\n"); 2738 break; 2739 default: 2740 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 2741 trapnr); 2742 gdbsig = TARGET_SIGILL; 2743 break; 2744 } 2745 if (gdbsig) { 2746 gdb_handlesig(cs, gdbsig); 2747 if (gdbsig != TARGET_SIGTRAP) { 2748 exit(EXIT_FAILURE); 2749 } 2750 } 2751 2752 process_pending_signals(env); 2753 } 2754 } 2755 2756 #endif /* TARGET_OPENRISC */ 2757 2758 #ifdef TARGET_SH4 2759 void cpu_loop(CPUSH4State *env) 2760 { 2761 CPUState *cs = CPU(sh_env_get_cpu(env)); 2762 int trapnr, ret; 2763 target_siginfo_t info; 2764 2765 while (1) { 2766 cpu_exec_start(cs); 2767 trapnr = cpu_exec(cs); 2768 cpu_exec_end(cs); 2769 process_queued_cpu_work(cs); 2770 2771 switch (trapnr) { 2772 case 0x160: 2773 env->pc += 2; 2774 ret = do_syscall(env, 2775 env->gregs[3], 2776 env->gregs[4], 2777 env->gregs[5], 2778 env->gregs[6], 2779 env->gregs[7], 2780 env->gregs[0], 2781 env->gregs[1], 2782 0, 0); 2783 if (ret == -TARGET_ERESTARTSYS) { 2784 env->pc -= 2; 2785 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2786 env->gregs[0] = ret; 2787 } 2788 break; 2789 case EXCP_INTERRUPT: 2790 /* just indicate that signals should be handled asap */ 2791 break; 2792 case EXCP_DEBUG: 2793 { 2794 int sig; 2795 2796 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2797 if (sig) 2798 { 2799 info.si_signo = sig; 2800 info.si_errno = 0; 2801 info.si_code = TARGET_TRAP_BRKPT; 2802 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2803 } 2804 } 2805 break; 2806 case 0xa0: 2807 case 0xc0: 2808 info.si_signo = TARGET_SIGSEGV; 2809 info.si_errno = 0; 2810 info.si_code = TARGET_SEGV_MAPERR; 2811 info._sifields._sigfault._addr = env->tea; 2812 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2813 break; 2814 2815 default: 2816 printf ("Unhandled trap: 0x%x\n", trapnr); 2817 cpu_dump_state(cs, stderr, fprintf, 0); 2818 exit(EXIT_FAILURE); 2819 } 2820 process_pending_signals (env); 2821 } 2822 } 2823 #endif 2824 2825 #ifdef TARGET_CRIS 2826 void cpu_loop(CPUCRISState *env) 2827 { 2828 CPUState *cs = CPU(cris_env_get_cpu(env)); 2829 int trapnr, ret; 2830 target_siginfo_t info; 2831 2832 while (1) { 2833 cpu_exec_start(cs); 2834 trapnr = cpu_exec(cs); 2835 cpu_exec_end(cs); 2836 process_queued_cpu_work(cs); 2837 2838 switch (trapnr) { 2839 case 0xaa: 2840 { 2841 info.si_signo = TARGET_SIGSEGV; 2842 info.si_errno = 0; 2843 /* XXX: check env->error_code */ 2844 info.si_code = TARGET_SEGV_MAPERR; 2845 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2846 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2847 } 2848 break; 2849 case EXCP_INTERRUPT: 2850 /* just indicate that signals should be handled asap */ 2851 break; 2852 case EXCP_BREAK: 2853 ret = do_syscall(env, 2854 env->regs[9], 2855 env->regs[10], 2856 env->regs[11], 2857 env->regs[12], 2858 env->regs[13], 2859 env->pregs[7], 2860 env->pregs[11], 2861 0, 0); 2862 if (ret == -TARGET_ERESTARTSYS) { 2863 env->pc -= 2; 2864 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2865 env->regs[10] = ret; 2866 } 2867 break; 2868 case EXCP_DEBUG: 2869 { 2870 int sig; 2871 2872 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2873 if (sig) 2874 { 2875 info.si_signo = sig; 2876 info.si_errno = 0; 2877 info.si_code = TARGET_TRAP_BRKPT; 2878 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2879 } 2880 } 2881 break; 2882 default: 2883 printf ("Unhandled trap: 0x%x\n", trapnr); 2884 cpu_dump_state(cs, stderr, fprintf, 0); 2885 exit(EXIT_FAILURE); 2886 } 2887 process_pending_signals (env); 2888 } 2889 } 2890 #endif 2891 2892 #ifdef TARGET_MICROBLAZE 2893 void cpu_loop(CPUMBState *env) 2894 { 2895 CPUState *cs = CPU(mb_env_get_cpu(env)); 2896 int trapnr, ret; 2897 target_siginfo_t info; 2898 2899 while (1) { 2900 cpu_exec_start(cs); 2901 trapnr = cpu_exec(cs); 2902 cpu_exec_end(cs); 2903 process_queued_cpu_work(cs); 2904 2905 switch (trapnr) { 2906 case 0xaa: 2907 { 2908 info.si_signo = TARGET_SIGSEGV; 2909 info.si_errno = 0; 2910 /* XXX: check env->error_code */ 2911 info.si_code = TARGET_SEGV_MAPERR; 2912 info._sifields._sigfault._addr = 0; 2913 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2914 } 2915 break; 2916 case EXCP_INTERRUPT: 2917 /* just indicate that signals should be handled asap */ 2918 break; 2919 case EXCP_BREAK: 2920 /* Return address is 4 bytes after the call. */ 2921 env->regs[14] += 4; 2922 env->sregs[SR_PC] = env->regs[14]; 2923 ret = do_syscall(env, 2924 env->regs[12], 2925 env->regs[5], 2926 env->regs[6], 2927 env->regs[7], 2928 env->regs[8], 2929 env->regs[9], 2930 env->regs[10], 2931 0, 0); 2932 if (ret == -TARGET_ERESTARTSYS) { 2933 /* Wind back to before the syscall. */ 2934 env->sregs[SR_PC] -= 4; 2935 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2936 env->regs[3] = ret; 2937 } 2938 /* All syscall exits result in guest r14 being equal to the 2939 * PC we return to, because the kernel syscall exit "rtbd" does 2940 * this. (This is true even for sigreturn(); note that r14 is 2941 * not a userspace-usable register, as the kernel may clobber it 2942 * at any point.) 2943 */ 2944 env->regs[14] = env->sregs[SR_PC]; 2945 break; 2946 case EXCP_HW_EXCP: 2947 env->regs[17] = env->sregs[SR_PC] + 4; 2948 if (env->iflags & D_FLAG) { 2949 env->sregs[SR_ESR] |= 1 << 12; 2950 env->sregs[SR_PC] -= 4; 2951 /* FIXME: if branch was immed, replay the imm as well. */ 2952 } 2953 2954 env->iflags &= ~(IMM_FLAG | D_FLAG); 2955 2956 switch (env->sregs[SR_ESR] & 31) { 2957 case ESR_EC_DIVZERO: 2958 info.si_signo = TARGET_SIGFPE; 2959 info.si_errno = 0; 2960 info.si_code = TARGET_FPE_FLTDIV; 2961 info._sifields._sigfault._addr = 0; 2962 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2963 break; 2964 case ESR_EC_FPU: 2965 info.si_signo = TARGET_SIGFPE; 2966 info.si_errno = 0; 2967 if (env->sregs[SR_FSR] & FSR_IO) { 2968 info.si_code = TARGET_FPE_FLTINV; 2969 } 2970 if (env->sregs[SR_FSR] & FSR_DZ) { 2971 info.si_code = TARGET_FPE_FLTDIV; 2972 } 2973 info._sifields._sigfault._addr = 0; 2974 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2975 break; 2976 default: 2977 printf ("Unhandled hw-exception: 0x%x\n", 2978 env->sregs[SR_ESR] & ESR_EC_MASK); 2979 cpu_dump_state(cs, stderr, fprintf, 0); 2980 exit(EXIT_FAILURE); 2981 break; 2982 } 2983 break; 2984 case EXCP_DEBUG: 2985 { 2986 int sig; 2987 2988 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2989 if (sig) 2990 { 2991 info.si_signo = sig; 2992 info.si_errno = 0; 2993 info.si_code = TARGET_TRAP_BRKPT; 2994 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2995 } 2996 } 2997 break; 2998 default: 2999 printf ("Unhandled trap: 0x%x\n", trapnr); 3000 cpu_dump_state(cs, stderr, fprintf, 0); 3001 exit(EXIT_FAILURE); 3002 } 3003 process_pending_signals (env); 3004 } 3005 } 3006 #endif 3007 3008 #ifdef TARGET_M68K 3009 3010 void cpu_loop(CPUM68KState *env) 3011 { 3012 CPUState *cs = CPU(m68k_env_get_cpu(env)); 3013 int trapnr; 3014 unsigned int n; 3015 target_siginfo_t info; 3016 TaskState *ts = cs->opaque; 3017 3018 for(;;) { 3019 cpu_exec_start(cs); 3020 trapnr = cpu_exec(cs); 3021 cpu_exec_end(cs); 3022 process_queued_cpu_work(cs); 3023 3024 switch(trapnr) { 3025 case EXCP_ILLEGAL: 3026 { 3027 if (ts->sim_syscalls) { 3028 uint16_t nr; 3029 get_user_u16(nr, env->pc + 2); 3030 env->pc += 4; 3031 do_m68k_simcall(env, nr); 3032 } else { 3033 goto do_sigill; 3034 } 3035 } 3036 break; 3037 case EXCP_HALT_INSN: 3038 /* Semihosing syscall. */ 3039 env->pc += 4; 3040 do_m68k_semihosting(env, env->dregs[0]); 3041 break; 3042 case EXCP_LINEA: 3043 case EXCP_LINEF: 3044 case EXCP_UNSUPPORTED: 3045 do_sigill: 3046 info.si_signo = TARGET_SIGILL; 3047 info.si_errno = 0; 3048 info.si_code = TARGET_ILL_ILLOPN; 3049 info._sifields._sigfault._addr = env->pc; 3050 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3051 break; 3052 case EXCP_TRAP0: 3053 { 3054 abi_long ret; 3055 ts->sim_syscalls = 0; 3056 n = env->dregs[0]; 3057 env->pc += 2; 3058 ret = do_syscall(env, 3059 n, 3060 env->dregs[1], 3061 env->dregs[2], 3062 env->dregs[3], 3063 env->dregs[4], 3064 env->dregs[5], 3065 env->aregs[0], 3066 0, 0); 3067 if (ret == -TARGET_ERESTARTSYS) { 3068 env->pc -= 2; 3069 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3070 env->dregs[0] = ret; 3071 } 3072 } 3073 break; 3074 case EXCP_INTERRUPT: 3075 /* just indicate that signals should be handled asap */ 3076 break; 3077 case EXCP_ACCESS: 3078 { 3079 info.si_signo = TARGET_SIGSEGV; 3080 info.si_errno = 0; 3081 /* XXX: check env->error_code */ 3082 info.si_code = TARGET_SEGV_MAPERR; 3083 info._sifields._sigfault._addr = env->mmu.ar; 3084 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3085 } 3086 break; 3087 case EXCP_DEBUG: 3088 { 3089 int sig; 3090 3091 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3092 if (sig) 3093 { 3094 info.si_signo = sig; 3095 info.si_errno = 0; 3096 info.si_code = TARGET_TRAP_BRKPT; 3097 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3098 } 3099 } 3100 break; 3101 default: 3102 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 3103 abort(); 3104 } 3105 process_pending_signals(env); 3106 } 3107 } 3108 #endif /* TARGET_M68K */ 3109 3110 #ifdef TARGET_ALPHA 3111 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 3112 { 3113 target_ulong addr, val, tmp; 3114 target_siginfo_t info; 3115 int ret = 0; 3116 3117 addr = env->lock_addr; 3118 tmp = env->lock_st_addr; 3119 env->lock_addr = -1; 3120 env->lock_st_addr = 0; 3121 3122 start_exclusive(); 3123 mmap_lock(); 3124 3125 if (addr == tmp) { 3126 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3127 goto do_sigsegv; 3128 } 3129 3130 if (val == env->lock_value) { 3131 tmp = env->ir[reg]; 3132 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 3133 goto do_sigsegv; 3134 } 3135 ret = 1; 3136 } 3137 } 3138 env->ir[reg] = ret; 3139 env->pc += 4; 3140 3141 mmap_unlock(); 3142 end_exclusive(); 3143 return; 3144 3145 do_sigsegv: 3146 mmap_unlock(); 3147 end_exclusive(); 3148 3149 info.si_signo = TARGET_SIGSEGV; 3150 info.si_errno = 0; 3151 info.si_code = TARGET_SEGV_MAPERR; 3152 info._sifields._sigfault._addr = addr; 3153 queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info); 3154 } 3155 3156 void cpu_loop(CPUAlphaState *env) 3157 { 3158 CPUState *cs = CPU(alpha_env_get_cpu(env)); 3159 int trapnr; 3160 target_siginfo_t info; 3161 abi_long sysret; 3162 3163 while (1) { 3164 cpu_exec_start(cs); 3165 trapnr = cpu_exec(cs); 3166 cpu_exec_end(cs); 3167 process_queued_cpu_work(cs); 3168 3169 /* All of the traps imply a transition through PALcode, which 3170 implies an REI instruction has been executed. Which means 3171 that the intr_flag should be cleared. */ 3172 env->intr_flag = 0; 3173 3174 switch (trapnr) { 3175 case EXCP_RESET: 3176 fprintf(stderr, "Reset requested. Exit\n"); 3177 exit(EXIT_FAILURE); 3178 break; 3179 case EXCP_MCHK: 3180 fprintf(stderr, "Machine check exception. Exit\n"); 3181 exit(EXIT_FAILURE); 3182 break; 3183 case EXCP_SMP_INTERRUPT: 3184 case EXCP_CLK_INTERRUPT: 3185 case EXCP_DEV_INTERRUPT: 3186 fprintf(stderr, "External interrupt. Exit\n"); 3187 exit(EXIT_FAILURE); 3188 break; 3189 case EXCP_MMFAULT: 3190 env->lock_addr = -1; 3191 info.si_signo = TARGET_SIGSEGV; 3192 info.si_errno = 0; 3193 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 3194 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 3195 info._sifields._sigfault._addr = env->trap_arg0; 3196 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3197 break; 3198 case EXCP_UNALIGN: 3199 env->lock_addr = -1; 3200 info.si_signo = TARGET_SIGBUS; 3201 info.si_errno = 0; 3202 info.si_code = TARGET_BUS_ADRALN; 3203 info._sifields._sigfault._addr = env->trap_arg0; 3204 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3205 break; 3206 case EXCP_OPCDEC: 3207 do_sigill: 3208 env->lock_addr = -1; 3209 info.si_signo = TARGET_SIGILL; 3210 info.si_errno = 0; 3211 info.si_code = TARGET_ILL_ILLOPC; 3212 info._sifields._sigfault._addr = env->pc; 3213 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3214 break; 3215 case EXCP_ARITH: 3216 env->lock_addr = -1; 3217 info.si_signo = TARGET_SIGFPE; 3218 info.si_errno = 0; 3219 info.si_code = TARGET_FPE_FLTINV; 3220 info._sifields._sigfault._addr = env->pc; 3221 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3222 break; 3223 case EXCP_FEN: 3224 /* No-op. Linux simply re-enables the FPU. */ 3225 break; 3226 case EXCP_CALL_PAL: 3227 env->lock_addr = -1; 3228 switch (env->error_code) { 3229 case 0x80: 3230 /* BPT */ 3231 info.si_signo = TARGET_SIGTRAP; 3232 info.si_errno = 0; 3233 info.si_code = TARGET_TRAP_BRKPT; 3234 info._sifields._sigfault._addr = env->pc; 3235 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3236 break; 3237 case 0x81: 3238 /* BUGCHK */ 3239 info.si_signo = TARGET_SIGTRAP; 3240 info.si_errno = 0; 3241 info.si_code = 0; 3242 info._sifields._sigfault._addr = env->pc; 3243 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3244 break; 3245 case 0x83: 3246 /* CALLSYS */ 3247 trapnr = env->ir[IR_V0]; 3248 sysret = do_syscall(env, trapnr, 3249 env->ir[IR_A0], env->ir[IR_A1], 3250 env->ir[IR_A2], env->ir[IR_A3], 3251 env->ir[IR_A4], env->ir[IR_A5], 3252 0, 0); 3253 if (sysret == -TARGET_ERESTARTSYS) { 3254 env->pc -= 4; 3255 break; 3256 } 3257 if (sysret == -TARGET_QEMU_ESIGRETURN) { 3258 break; 3259 } 3260 /* Syscall writes 0 to V0 to bypass error check, similar 3261 to how this is handled internal to Linux kernel. 3262 (Ab)use trapnr temporarily as boolean indicating error. */ 3263 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 3264 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 3265 env->ir[IR_A3] = trapnr; 3266 break; 3267 case 0x86: 3268 /* IMB */ 3269 /* ??? We can probably elide the code using page_unprotect 3270 that is checking for self-modifying code. Instead we 3271 could simply call tb_flush here. Until we work out the 3272 changes required to turn off the extra write protection, 3273 this can be a no-op. */ 3274 break; 3275 case 0x9E: 3276 /* RDUNIQUE */ 3277 /* Handled in the translator for usermode. */ 3278 abort(); 3279 case 0x9F: 3280 /* WRUNIQUE */ 3281 /* Handled in the translator for usermode. */ 3282 abort(); 3283 case 0xAA: 3284 /* GENTRAP */ 3285 info.si_signo = TARGET_SIGFPE; 3286 switch (env->ir[IR_A0]) { 3287 case TARGET_GEN_INTOVF: 3288 info.si_code = TARGET_FPE_INTOVF; 3289 break; 3290 case TARGET_GEN_INTDIV: 3291 info.si_code = TARGET_FPE_INTDIV; 3292 break; 3293 case TARGET_GEN_FLTOVF: 3294 info.si_code = TARGET_FPE_FLTOVF; 3295 break; 3296 case TARGET_GEN_FLTUND: 3297 info.si_code = TARGET_FPE_FLTUND; 3298 break; 3299 case TARGET_GEN_FLTINV: 3300 info.si_code = TARGET_FPE_FLTINV; 3301 break; 3302 case TARGET_GEN_FLTINE: 3303 info.si_code = TARGET_FPE_FLTRES; 3304 break; 3305 case TARGET_GEN_ROPRAND: 3306 info.si_code = 0; 3307 break; 3308 default: 3309 info.si_signo = TARGET_SIGTRAP; 3310 info.si_code = 0; 3311 break; 3312 } 3313 info.si_errno = 0; 3314 info._sifields._sigfault._addr = env->pc; 3315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3316 break; 3317 default: 3318 goto do_sigill; 3319 } 3320 break; 3321 case EXCP_DEBUG: 3322 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); 3323 if (info.si_signo) { 3324 env->lock_addr = -1; 3325 info.si_errno = 0; 3326 info.si_code = TARGET_TRAP_BRKPT; 3327 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3328 } 3329 break; 3330 case EXCP_STL_C: 3331 case EXCP_STQ_C: 3332 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3333 break; 3334 case EXCP_INTERRUPT: 3335 /* Just indicate that signals should be handled asap. */ 3336 break; 3337 default: 3338 printf ("Unhandled trap: 0x%x\n", trapnr); 3339 cpu_dump_state(cs, stderr, fprintf, 0); 3340 exit(EXIT_FAILURE); 3341 } 3342 process_pending_signals (env); 3343 } 3344 } 3345 #endif /* TARGET_ALPHA */ 3346 3347 #ifdef TARGET_S390X 3348 void cpu_loop(CPUS390XState *env) 3349 { 3350 CPUState *cs = CPU(s390_env_get_cpu(env)); 3351 int trapnr, n, sig; 3352 target_siginfo_t info; 3353 target_ulong addr; 3354 abi_long ret; 3355 3356 while (1) { 3357 cpu_exec_start(cs); 3358 trapnr = cpu_exec(cs); 3359 cpu_exec_end(cs); 3360 process_queued_cpu_work(cs); 3361 3362 switch (trapnr) { 3363 case EXCP_INTERRUPT: 3364 /* Just indicate that signals should be handled asap. */ 3365 break; 3366 3367 case EXCP_SVC: 3368 n = env->int_svc_code; 3369 if (!n) { 3370 /* syscalls > 255 */ 3371 n = env->regs[1]; 3372 } 3373 env->psw.addr += env->int_svc_ilen; 3374 ret = do_syscall(env, n, env->regs[2], env->regs[3], 3375 env->regs[4], env->regs[5], 3376 env->regs[6], env->regs[7], 0, 0); 3377 if (ret == -TARGET_ERESTARTSYS) { 3378 env->psw.addr -= env->int_svc_ilen; 3379 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3380 env->regs[2] = ret; 3381 } 3382 break; 3383 3384 case EXCP_DEBUG: 3385 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3386 if (sig) { 3387 n = TARGET_TRAP_BRKPT; 3388 goto do_signal_pc; 3389 } 3390 break; 3391 case EXCP_PGM: 3392 n = env->int_pgm_code; 3393 switch (n) { 3394 case PGM_OPERATION: 3395 case PGM_PRIVILEGED: 3396 sig = TARGET_SIGILL; 3397 n = TARGET_ILL_ILLOPC; 3398 goto do_signal_pc; 3399 case PGM_PROTECTION: 3400 case PGM_ADDRESSING: 3401 sig = TARGET_SIGSEGV; 3402 /* XXX: check env->error_code */ 3403 n = TARGET_SEGV_MAPERR; 3404 addr = env->__excp_addr; 3405 goto do_signal; 3406 case PGM_EXECUTE: 3407 case PGM_SPECIFICATION: 3408 case PGM_SPECIAL_OP: 3409 case PGM_OPERAND: 3410 do_sigill_opn: 3411 sig = TARGET_SIGILL; 3412 n = TARGET_ILL_ILLOPN; 3413 goto do_signal_pc; 3414 3415 case PGM_FIXPT_OVERFLOW: 3416 sig = TARGET_SIGFPE; 3417 n = TARGET_FPE_INTOVF; 3418 goto do_signal_pc; 3419 case PGM_FIXPT_DIVIDE: 3420 sig = TARGET_SIGFPE; 3421 n = TARGET_FPE_INTDIV; 3422 goto do_signal_pc; 3423 3424 case PGM_DATA: 3425 n = (env->fpc >> 8) & 0xff; 3426 if (n == 0xff) { 3427 /* compare-and-trap */ 3428 goto do_sigill_opn; 3429 } else { 3430 /* An IEEE exception, simulated or otherwise. */ 3431 if (n & 0x80) { 3432 n = TARGET_FPE_FLTINV; 3433 } else if (n & 0x40) { 3434 n = TARGET_FPE_FLTDIV; 3435 } else if (n & 0x20) { 3436 n = TARGET_FPE_FLTOVF; 3437 } else if (n & 0x10) { 3438 n = TARGET_FPE_FLTUND; 3439 } else if (n & 0x08) { 3440 n = TARGET_FPE_FLTRES; 3441 } else { 3442 /* ??? Quantum exception; BFP, DFP error. */ 3443 goto do_sigill_opn; 3444 } 3445 sig = TARGET_SIGFPE; 3446 goto do_signal_pc; 3447 } 3448 3449 default: 3450 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3451 cpu_dump_state(cs, stderr, fprintf, 0); 3452 exit(EXIT_FAILURE); 3453 } 3454 break; 3455 3456 do_signal_pc: 3457 addr = env->psw.addr; 3458 do_signal: 3459 info.si_signo = sig; 3460 info.si_errno = 0; 3461 info.si_code = n; 3462 info._sifields._sigfault._addr = addr; 3463 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3464 break; 3465 3466 default: 3467 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3468 cpu_dump_state(cs, stderr, fprintf, 0); 3469 exit(EXIT_FAILURE); 3470 } 3471 process_pending_signals (env); 3472 } 3473 } 3474 3475 #endif /* TARGET_S390X */ 3476 3477 #ifdef TARGET_TILEGX 3478 3479 static void gen_sigill_reg(CPUTLGState *env) 3480 { 3481 target_siginfo_t info; 3482 3483 info.si_signo = TARGET_SIGILL; 3484 info.si_errno = 0; 3485 info.si_code = TARGET_ILL_PRVREG; 3486 info._sifields._sigfault._addr = env->pc; 3487 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3488 } 3489 3490 static void do_signal(CPUTLGState *env, int signo, int sigcode) 3491 { 3492 target_siginfo_t info; 3493 3494 info.si_signo = signo; 3495 info.si_errno = 0; 3496 info._sifields._sigfault._addr = env->pc; 3497 3498 if (signo == TARGET_SIGSEGV) { 3499 /* The passed in sigcode is a dummy; check for a page mapping 3500 and pass either MAPERR or ACCERR. */ 3501 target_ulong addr = env->excaddr; 3502 info._sifields._sigfault._addr = addr; 3503 if (page_check_range(addr, 1, PAGE_VALID) < 0) { 3504 sigcode = TARGET_SEGV_MAPERR; 3505 } else { 3506 sigcode = TARGET_SEGV_ACCERR; 3507 } 3508 } 3509 info.si_code = sigcode; 3510 3511 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3512 } 3513 3514 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) 3515 { 3516 env->excaddr = addr; 3517 do_signal(env, TARGET_SIGSEGV, 0); 3518 } 3519 3520 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) 3521 { 3522 if (unlikely(reg >= TILEGX_R_COUNT)) { 3523 switch (reg) { 3524 case TILEGX_R_SN: 3525 case TILEGX_R_ZERO: 3526 return; 3527 case TILEGX_R_IDN0: 3528 case TILEGX_R_IDN1: 3529 case TILEGX_R_UDN0: 3530 case TILEGX_R_UDN1: 3531 case TILEGX_R_UDN2: 3532 case TILEGX_R_UDN3: 3533 gen_sigill_reg(env); 3534 return; 3535 default: 3536 g_assert_not_reached(); 3537 } 3538 } 3539 env->regs[reg] = val; 3540 } 3541 3542 /* 3543 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in 3544 * memory at the address held in the first source register. If the values are 3545 * not equal, then no memory operation is performed. If the values are equal, 3546 * the 8-byte quantity from the second source register is written into memory 3547 * at the address held in the first source register. In either case, the result 3548 * of the instruction is the value read from memory. The compare and write to 3549 * memory are atomic and thus can be used for synchronization purposes. This 3550 * instruction only operates for addresses aligned to a 8-byte boundary. 3551 * Unaligned memory access causes an Unaligned Data Reference interrupt. 3552 * 3553 * Functional Description (64-bit) 3554 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); 3555 * rf[Dest] = memVal; 3556 * if (memVal == SPR[CmpValueSPR]) 3557 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); 3558 * 3559 * Functional Description (32-bit) 3560 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); 3561 * rf[Dest] = memVal; 3562 * if (memVal == signExtend32 (SPR[CmpValueSPR])) 3563 * memoryWriteWord (rf[SrcA], rf[SrcB]); 3564 * 3565 * 3566 * This function also processes exch and exch4 which need not process SPR. 3567 */ 3568 static void do_exch(CPUTLGState *env, bool quad, bool cmp) 3569 { 3570 target_ulong addr; 3571 target_long val, sprval; 3572 3573 start_exclusive(); 3574 3575 addr = env->atomic_srca; 3576 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3577 goto sigsegv_maperr; 3578 } 3579 3580 if (cmp) { 3581 if (quad) { 3582 sprval = env->spregs[TILEGX_SPR_CMPEXCH]; 3583 } else { 3584 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); 3585 } 3586 } 3587 3588 if (!cmp || val == sprval) { 3589 target_long valb = env->atomic_srcb; 3590 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3591 goto sigsegv_maperr; 3592 } 3593 } 3594 3595 set_regval(env, env->atomic_dstr, val); 3596 end_exclusive(); 3597 return; 3598 3599 sigsegv_maperr: 3600 end_exclusive(); 3601 gen_sigsegv_maperr(env, addr); 3602 } 3603 3604 static void do_fetch(CPUTLGState *env, int trapnr, bool quad) 3605 { 3606 int8_t write = 1; 3607 target_ulong addr; 3608 target_long val, valb; 3609 3610 start_exclusive(); 3611 3612 addr = env->atomic_srca; 3613 valb = env->atomic_srcb; 3614 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3615 goto sigsegv_maperr; 3616 } 3617 3618 switch (trapnr) { 3619 case TILEGX_EXCP_OPCODE_FETCHADD: 3620 case TILEGX_EXCP_OPCODE_FETCHADD4: 3621 valb += val; 3622 break; 3623 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3624 valb += val; 3625 if (valb < 0) { 3626 write = 0; 3627 } 3628 break; 3629 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3630 valb += val; 3631 if ((int32_t)valb < 0) { 3632 write = 0; 3633 } 3634 break; 3635 case TILEGX_EXCP_OPCODE_FETCHAND: 3636 case TILEGX_EXCP_OPCODE_FETCHAND4: 3637 valb &= val; 3638 break; 3639 case TILEGX_EXCP_OPCODE_FETCHOR: 3640 case TILEGX_EXCP_OPCODE_FETCHOR4: 3641 valb |= val; 3642 break; 3643 default: 3644 g_assert_not_reached(); 3645 } 3646 3647 if (write) { 3648 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3649 goto sigsegv_maperr; 3650 } 3651 } 3652 3653 set_regval(env, env->atomic_dstr, val); 3654 end_exclusive(); 3655 return; 3656 3657 sigsegv_maperr: 3658 end_exclusive(); 3659 gen_sigsegv_maperr(env, addr); 3660 } 3661 3662 void cpu_loop(CPUTLGState *env) 3663 { 3664 CPUState *cs = CPU(tilegx_env_get_cpu(env)); 3665 int trapnr; 3666 3667 while (1) { 3668 cpu_exec_start(cs); 3669 trapnr = cpu_exec(cs); 3670 cpu_exec_end(cs); 3671 process_queued_cpu_work(cs); 3672 3673 switch (trapnr) { 3674 case TILEGX_EXCP_SYSCALL: 3675 { 3676 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR], 3677 env->regs[0], env->regs[1], 3678 env->regs[2], env->regs[3], 3679 env->regs[4], env->regs[5], 3680 env->regs[6], env->regs[7]); 3681 if (ret == -TARGET_ERESTARTSYS) { 3682 env->pc -= 8; 3683 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3684 env->regs[TILEGX_R_RE] = ret; 3685 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0; 3686 } 3687 break; 3688 } 3689 case TILEGX_EXCP_OPCODE_EXCH: 3690 do_exch(env, true, false); 3691 break; 3692 case TILEGX_EXCP_OPCODE_EXCH4: 3693 do_exch(env, false, false); 3694 break; 3695 case TILEGX_EXCP_OPCODE_CMPEXCH: 3696 do_exch(env, true, true); 3697 break; 3698 case TILEGX_EXCP_OPCODE_CMPEXCH4: 3699 do_exch(env, false, true); 3700 break; 3701 case TILEGX_EXCP_OPCODE_FETCHADD: 3702 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3703 case TILEGX_EXCP_OPCODE_FETCHAND: 3704 case TILEGX_EXCP_OPCODE_FETCHOR: 3705 do_fetch(env, trapnr, true); 3706 break; 3707 case TILEGX_EXCP_OPCODE_FETCHADD4: 3708 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3709 case TILEGX_EXCP_OPCODE_FETCHAND4: 3710 case TILEGX_EXCP_OPCODE_FETCHOR4: 3711 do_fetch(env, trapnr, false); 3712 break; 3713 case TILEGX_EXCP_SIGNAL: 3714 do_signal(env, env->signo, env->sigcode); 3715 break; 3716 case TILEGX_EXCP_REG_IDN_ACCESS: 3717 case TILEGX_EXCP_REG_UDN_ACCESS: 3718 gen_sigill_reg(env); 3719 break; 3720 default: 3721 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); 3722 g_assert_not_reached(); 3723 } 3724 process_pending_signals(env); 3725 } 3726 } 3727 3728 #endif 3729 3730 THREAD CPUState *thread_cpu; 3731 3732 bool qemu_cpu_is_self(CPUState *cpu) 3733 { 3734 return thread_cpu == cpu; 3735 } 3736 3737 void qemu_cpu_kick(CPUState *cpu) 3738 { 3739 cpu_exit(cpu); 3740 } 3741 3742 void task_settid(TaskState *ts) 3743 { 3744 if (ts->ts_tid == 0) { 3745 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3746 } 3747 } 3748 3749 void stop_all_tasks(void) 3750 { 3751 /* 3752 * We trust that when using NPTL, start_exclusive() 3753 * handles thread stopping correctly. 3754 */ 3755 start_exclusive(); 3756 } 3757 3758 /* Assumes contents are already zeroed. */ 3759 void init_task_state(TaskState *ts) 3760 { 3761 ts->used = 1; 3762 } 3763 3764 CPUArchState *cpu_copy(CPUArchState *env) 3765 { 3766 CPUState *cpu = ENV_GET_CPU(env); 3767 CPUState *new_cpu = cpu_init(cpu_model); 3768 CPUArchState *new_env = new_cpu->env_ptr; 3769 CPUBreakpoint *bp; 3770 CPUWatchpoint *wp; 3771 3772 /* Reset non arch specific state */ 3773 cpu_reset(new_cpu); 3774 3775 memcpy(new_env, env, sizeof(CPUArchState)); 3776 3777 /* Clone all break/watchpoints. 3778 Note: Once we support ptrace with hw-debug register access, make sure 3779 BP_CPU break/watchpoints are handled correctly on clone. */ 3780 QTAILQ_INIT(&new_cpu->breakpoints); 3781 QTAILQ_INIT(&new_cpu->watchpoints); 3782 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 3783 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); 3784 } 3785 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { 3786 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); 3787 } 3788 3789 return new_env; 3790 } 3791 3792 static void handle_arg_help(const char *arg) 3793 { 3794 usage(EXIT_SUCCESS); 3795 } 3796 3797 static void handle_arg_log(const char *arg) 3798 { 3799 int mask; 3800 3801 mask = qemu_str_to_log_mask(arg); 3802 if (!mask) { 3803 qemu_print_log_usage(stdout); 3804 exit(EXIT_FAILURE); 3805 } 3806 qemu_log_needs_buffers(); 3807 qemu_set_log(mask); 3808 } 3809 3810 static void handle_arg_log_filename(const char *arg) 3811 { 3812 qemu_set_log_filename(arg, &error_fatal); 3813 } 3814 3815 static void handle_arg_set_env(const char *arg) 3816 { 3817 char *r, *p, *token; 3818 r = p = strdup(arg); 3819 while ((token = strsep(&p, ",")) != NULL) { 3820 if (envlist_setenv(envlist, token) != 0) { 3821 usage(EXIT_FAILURE); 3822 } 3823 } 3824 free(r); 3825 } 3826 3827 static void handle_arg_unset_env(const char *arg) 3828 { 3829 char *r, *p, *token; 3830 r = p = strdup(arg); 3831 while ((token = strsep(&p, ",")) != NULL) { 3832 if (envlist_unsetenv(envlist, token) != 0) { 3833 usage(EXIT_FAILURE); 3834 } 3835 } 3836 free(r); 3837 } 3838 3839 static void handle_arg_argv0(const char *arg) 3840 { 3841 argv0 = strdup(arg); 3842 } 3843 3844 static void handle_arg_stack_size(const char *arg) 3845 { 3846 char *p; 3847 guest_stack_size = strtoul(arg, &p, 0); 3848 if (guest_stack_size == 0) { 3849 usage(EXIT_FAILURE); 3850 } 3851 3852 if (*p == 'M') { 3853 guest_stack_size *= 1024 * 1024; 3854 } else if (*p == 'k' || *p == 'K') { 3855 guest_stack_size *= 1024; 3856 } 3857 } 3858 3859 static void handle_arg_ld_prefix(const char *arg) 3860 { 3861 interp_prefix = strdup(arg); 3862 } 3863 3864 static void handle_arg_pagesize(const char *arg) 3865 { 3866 qemu_host_page_size = atoi(arg); 3867 if (qemu_host_page_size == 0 || 3868 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3869 fprintf(stderr, "page size must be a power of two\n"); 3870 exit(EXIT_FAILURE); 3871 } 3872 } 3873 3874 static void handle_arg_randseed(const char *arg) 3875 { 3876 unsigned long long seed; 3877 3878 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) { 3879 fprintf(stderr, "Invalid seed number: %s\n", arg); 3880 exit(EXIT_FAILURE); 3881 } 3882 srand(seed); 3883 } 3884 3885 static void handle_arg_gdb(const char *arg) 3886 { 3887 gdbstub_port = atoi(arg); 3888 } 3889 3890 static void handle_arg_uname(const char *arg) 3891 { 3892 qemu_uname_release = strdup(arg); 3893 } 3894 3895 static void handle_arg_cpu(const char *arg) 3896 { 3897 cpu_model = strdup(arg); 3898 if (cpu_model == NULL || is_help_option(cpu_model)) { 3899 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3900 #if defined(cpu_list) 3901 cpu_list(stdout, &fprintf); 3902 #endif 3903 exit(EXIT_FAILURE); 3904 } 3905 } 3906 3907 static void handle_arg_guest_base(const char *arg) 3908 { 3909 guest_base = strtol(arg, NULL, 0); 3910 have_guest_base = 1; 3911 } 3912 3913 static void handle_arg_reserved_va(const char *arg) 3914 { 3915 char *p; 3916 int shift = 0; 3917 reserved_va = strtoul(arg, &p, 0); 3918 switch (*p) { 3919 case 'k': 3920 case 'K': 3921 shift = 10; 3922 break; 3923 case 'M': 3924 shift = 20; 3925 break; 3926 case 'G': 3927 shift = 30; 3928 break; 3929 } 3930 if (shift) { 3931 unsigned long unshifted = reserved_va; 3932 p++; 3933 reserved_va <<= shift; 3934 if (((reserved_va >> shift) != unshifted) 3935 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3936 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3937 #endif 3938 ) { 3939 fprintf(stderr, "Reserved virtual address too big\n"); 3940 exit(EXIT_FAILURE); 3941 } 3942 } 3943 if (*p) { 3944 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3945 exit(EXIT_FAILURE); 3946 } 3947 } 3948 3949 static void handle_arg_singlestep(const char *arg) 3950 { 3951 singlestep = 1; 3952 } 3953 3954 static void handle_arg_strace(const char *arg) 3955 { 3956 do_strace = 1; 3957 } 3958 3959 static void handle_arg_version(const char *arg) 3960 { 3961 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3962 "\n" QEMU_COPYRIGHT "\n"); 3963 exit(EXIT_SUCCESS); 3964 } 3965 3966 static char *trace_file; 3967 static void handle_arg_trace(const char *arg) 3968 { 3969 g_free(trace_file); 3970 trace_file = trace_opt_parse(arg); 3971 } 3972 3973 struct qemu_argument { 3974 const char *argv; 3975 const char *env; 3976 bool has_arg; 3977 void (*handle_opt)(const char *arg); 3978 const char *example; 3979 const char *help; 3980 }; 3981 3982 static const struct qemu_argument arg_table[] = { 3983 {"h", "", false, handle_arg_help, 3984 "", "print this help"}, 3985 {"help", "", false, handle_arg_help, 3986 "", ""}, 3987 {"g", "QEMU_GDB", true, handle_arg_gdb, 3988 "port", "wait gdb connection to 'port'"}, 3989 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3990 "path", "set the elf interpreter prefix to 'path'"}, 3991 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3992 "size", "set the stack size to 'size' bytes"}, 3993 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3994 "model", "select CPU (-cpu help for list)"}, 3995 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3996 "var=value", "sets targets environment variable (see below)"}, 3997 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3998 "var", "unsets targets environment variable (see below)"}, 3999 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 4000 "argv0", "forces target process argv[0] to be 'argv0'"}, 4001 {"r", "QEMU_UNAME", true, handle_arg_uname, 4002 "uname", "set qemu uname release string to 'uname'"}, 4003 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 4004 "address", "set guest_base address to 'address'"}, 4005 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 4006 "size", "reserve 'size' bytes for guest virtual address space"}, 4007 {"d", "QEMU_LOG", true, handle_arg_log, 4008 "item[,...]", "enable logging of specified items " 4009 "(use '-d help' for a list of items)"}, 4010 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 4011 "logfile", "write logs to 'logfile' (default stderr)"}, 4012 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 4013 "pagesize", "set the host page size to 'pagesize'"}, 4014 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 4015 "", "run in singlestep mode"}, 4016 {"strace", "QEMU_STRACE", false, handle_arg_strace, 4017 "", "log system calls"}, 4018 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed, 4019 "", "Seed for pseudo-random number generator"}, 4020 {"trace", "QEMU_TRACE", true, handle_arg_trace, 4021 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"}, 4022 {"version", "QEMU_VERSION", false, handle_arg_version, 4023 "", "display version information and exit"}, 4024 {NULL, NULL, false, NULL, NULL, NULL} 4025 }; 4026 4027 static void usage(int exitcode) 4028 { 4029 const struct qemu_argument *arginfo; 4030 int maxarglen; 4031 int maxenvlen; 4032 4033 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 4034 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 4035 "\n" 4036 "Options and associated environment variables:\n" 4037 "\n"); 4038 4039 /* Calculate column widths. We must always have at least enough space 4040 * for the column header. 4041 */ 4042 maxarglen = strlen("Argument"); 4043 maxenvlen = strlen("Env-variable"); 4044 4045 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4046 int arglen = strlen(arginfo->argv); 4047 if (arginfo->has_arg) { 4048 arglen += strlen(arginfo->example) + 1; 4049 } 4050 if (strlen(arginfo->env) > maxenvlen) { 4051 maxenvlen = strlen(arginfo->env); 4052 } 4053 if (arglen > maxarglen) { 4054 maxarglen = arglen; 4055 } 4056 } 4057 4058 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 4059 maxenvlen, "Env-variable"); 4060 4061 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4062 if (arginfo->has_arg) { 4063 printf("-%s %-*s %-*s %s\n", arginfo->argv, 4064 (int)(maxarglen - strlen(arginfo->argv) - 1), 4065 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 4066 } else { 4067 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 4068 maxenvlen, arginfo->env, 4069 arginfo->help); 4070 } 4071 } 4072 4073 printf("\n" 4074 "Defaults:\n" 4075 "QEMU_LD_PREFIX = %s\n" 4076 "QEMU_STACK_SIZE = %ld byte\n", 4077 interp_prefix, 4078 guest_stack_size); 4079 4080 printf("\n" 4081 "You can use -E and -U options or the QEMU_SET_ENV and\n" 4082 "QEMU_UNSET_ENV environment variables to set and unset\n" 4083 "environment variables for the target process.\n" 4084 "It is possible to provide several variables by separating them\n" 4085 "by commas in getsubopt(3) style. Additionally it is possible to\n" 4086 "provide the -E and -U options multiple times.\n" 4087 "The following lines are equivalent:\n" 4088 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 4089 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 4090 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 4091 "Note that if you provide several changes to a single variable\n" 4092 "the last change will stay in effect.\n"); 4093 4094 exit(exitcode); 4095 } 4096 4097 static int parse_args(int argc, char **argv) 4098 { 4099 const char *r; 4100 int optind; 4101 const struct qemu_argument *arginfo; 4102 4103 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4104 if (arginfo->env == NULL) { 4105 continue; 4106 } 4107 4108 r = getenv(arginfo->env); 4109 if (r != NULL) { 4110 arginfo->handle_opt(r); 4111 } 4112 } 4113 4114 optind = 1; 4115 for (;;) { 4116 if (optind >= argc) { 4117 break; 4118 } 4119 r = argv[optind]; 4120 if (r[0] != '-') { 4121 break; 4122 } 4123 optind++; 4124 r++; 4125 if (!strcmp(r, "-")) { 4126 break; 4127 } 4128 /* Treat --foo the same as -foo. */ 4129 if (r[0] == '-') { 4130 r++; 4131 } 4132 4133 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4134 if (!strcmp(r, arginfo->argv)) { 4135 if (arginfo->has_arg) { 4136 if (optind >= argc) { 4137 (void) fprintf(stderr, 4138 "qemu: missing argument for option '%s'\n", r); 4139 exit(EXIT_FAILURE); 4140 } 4141 arginfo->handle_opt(argv[optind]); 4142 optind++; 4143 } else { 4144 arginfo->handle_opt(NULL); 4145 } 4146 break; 4147 } 4148 } 4149 4150 /* no option matched the current argv */ 4151 if (arginfo->handle_opt == NULL) { 4152 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r); 4153 exit(EXIT_FAILURE); 4154 } 4155 } 4156 4157 if (optind >= argc) { 4158 (void) fprintf(stderr, "qemu: no user program specified\n"); 4159 exit(EXIT_FAILURE); 4160 } 4161 4162 filename = argv[optind]; 4163 exec_path = argv[optind]; 4164 4165 return optind; 4166 } 4167 4168 int main(int argc, char **argv, char **envp) 4169 { 4170 struct target_pt_regs regs1, *regs = ®s1; 4171 struct image_info info1, *info = &info1; 4172 struct linux_binprm bprm; 4173 TaskState *ts; 4174 CPUArchState *env; 4175 CPUState *cpu; 4176 int optind; 4177 char **target_environ, **wrk; 4178 char **target_argv; 4179 int target_argc; 4180 int i; 4181 int ret; 4182 int execfd; 4183 4184 module_call_init(MODULE_INIT_TRACE); 4185 qemu_init_cpu_list(); 4186 module_call_init(MODULE_INIT_QOM); 4187 4188 if ((envlist = envlist_create()) == NULL) { 4189 (void) fprintf(stderr, "Unable to allocate envlist\n"); 4190 exit(EXIT_FAILURE); 4191 } 4192 4193 /* add current environment into the list */ 4194 for (wrk = environ; *wrk != NULL; wrk++) { 4195 (void) envlist_setenv(envlist, *wrk); 4196 } 4197 4198 /* Read the stack limit from the kernel. If it's "unlimited", 4199 then we can do little else besides use the default. */ 4200 { 4201 struct rlimit lim; 4202 if (getrlimit(RLIMIT_STACK, &lim) == 0 4203 && lim.rlim_cur != RLIM_INFINITY 4204 && lim.rlim_cur == (target_long)lim.rlim_cur) { 4205 guest_stack_size = lim.rlim_cur; 4206 } 4207 } 4208 4209 cpu_model = NULL; 4210 4211 srand(time(NULL)); 4212 4213 qemu_add_opts(&qemu_trace_opts); 4214 4215 optind = parse_args(argc, argv); 4216 4217 if (!trace_init_backends()) { 4218 exit(1); 4219 } 4220 trace_init_file(trace_file); 4221 4222 /* Zero out regs */ 4223 memset(regs, 0, sizeof(struct target_pt_regs)); 4224 4225 /* Zero out image_info */ 4226 memset(info, 0, sizeof(struct image_info)); 4227 4228 memset(&bprm, 0, sizeof (bprm)); 4229 4230 /* Scan interp_prefix dir for replacement files. */ 4231 init_paths(interp_prefix); 4232 4233 init_qemu_uname_release(); 4234 4235 if (cpu_model == NULL) { 4236 #if defined(TARGET_I386) 4237 #ifdef TARGET_X86_64 4238 cpu_model = "qemu64"; 4239 #else 4240 cpu_model = "qemu32"; 4241 #endif 4242 #elif defined(TARGET_ARM) 4243 cpu_model = "any"; 4244 #elif defined(TARGET_UNICORE32) 4245 cpu_model = "any"; 4246 #elif defined(TARGET_M68K) 4247 cpu_model = "any"; 4248 #elif defined(TARGET_SPARC) 4249 #ifdef TARGET_SPARC64 4250 cpu_model = "TI UltraSparc II"; 4251 #else 4252 cpu_model = "Fujitsu MB86904"; 4253 #endif 4254 #elif defined(TARGET_MIPS) 4255 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 4256 cpu_model = "5KEf"; 4257 #else 4258 cpu_model = "24Kf"; 4259 #endif 4260 #elif defined TARGET_OPENRISC 4261 cpu_model = "or1200"; 4262 #elif defined(TARGET_PPC) 4263 # ifdef TARGET_PPC64 4264 cpu_model = "POWER8"; 4265 # else 4266 cpu_model = "750"; 4267 # endif 4268 #elif defined TARGET_SH4 4269 cpu_model = TYPE_SH7785_CPU; 4270 #else 4271 cpu_model = "any"; 4272 #endif 4273 } 4274 tcg_exec_init(0); 4275 /* NOTE: we need to init the CPU at this stage to get 4276 qemu_host_page_size */ 4277 cpu = cpu_init(cpu_model); 4278 if (!cpu) { 4279 fprintf(stderr, "Unable to find CPU definition\n"); 4280 exit(EXIT_FAILURE); 4281 } 4282 env = cpu->env_ptr; 4283 cpu_reset(cpu); 4284 4285 thread_cpu = cpu; 4286 4287 if (getenv("QEMU_STRACE")) { 4288 do_strace = 1; 4289 } 4290 4291 if (getenv("QEMU_RAND_SEED")) { 4292 handle_arg_randseed(getenv("QEMU_RAND_SEED")); 4293 } 4294 4295 target_environ = envlist_to_environ(envlist, NULL); 4296 envlist_free(envlist); 4297 4298 /* 4299 * Now that page sizes are configured in cpu_init() we can do 4300 * proper page alignment for guest_base. 4301 */ 4302 guest_base = HOST_PAGE_ALIGN(guest_base); 4303 4304 if (reserved_va || have_guest_base) { 4305 guest_base = init_guest_space(guest_base, reserved_va, 0, 4306 have_guest_base); 4307 if (guest_base == (unsigned long)-1) { 4308 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 4309 "space for use as guest address space (check your virtual " 4310 "memory ulimit setting or reserve less using -R option)\n", 4311 reserved_va); 4312 exit(EXIT_FAILURE); 4313 } 4314 4315 if (reserved_va) { 4316 mmap_next_start = reserved_va; 4317 } 4318 } 4319 4320 /* 4321 * Read in mmap_min_addr kernel parameter. This value is used 4322 * When loading the ELF image to determine whether guest_base 4323 * is needed. It is also used in mmap_find_vma. 4324 */ 4325 { 4326 FILE *fp; 4327 4328 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 4329 unsigned long tmp; 4330 if (fscanf(fp, "%lu", &tmp) == 1) { 4331 mmap_min_addr = tmp; 4332 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr); 4333 } 4334 fclose(fp); 4335 } 4336 } 4337 4338 /* 4339 * Prepare copy of argv vector for target. 4340 */ 4341 target_argc = argc - optind; 4342 target_argv = calloc(target_argc + 1, sizeof (char *)); 4343 if (target_argv == NULL) { 4344 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 4345 exit(EXIT_FAILURE); 4346 } 4347 4348 /* 4349 * If argv0 is specified (using '-0' switch) we replace 4350 * argv[0] pointer with the given one. 4351 */ 4352 i = 0; 4353 if (argv0 != NULL) { 4354 target_argv[i++] = strdup(argv0); 4355 } 4356 for (; i < target_argc; i++) { 4357 target_argv[i] = strdup(argv[optind + i]); 4358 } 4359 target_argv[target_argc] = NULL; 4360 4361 ts = g_new0(TaskState, 1); 4362 init_task_state(ts); 4363 /* build Task State */ 4364 ts->info = info; 4365 ts->bprm = &bprm; 4366 cpu->opaque = ts; 4367 task_settid(ts); 4368 4369 execfd = qemu_getauxval(AT_EXECFD); 4370 if (execfd == 0) { 4371 execfd = open(filename, O_RDONLY); 4372 if (execfd < 0) { 4373 printf("Error while loading %s: %s\n", filename, strerror(errno)); 4374 _exit(EXIT_FAILURE); 4375 } 4376 } 4377 4378 ret = loader_exec(execfd, filename, target_argv, target_environ, regs, 4379 info, &bprm); 4380 if (ret != 0) { 4381 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 4382 _exit(EXIT_FAILURE); 4383 } 4384 4385 for (wrk = target_environ; *wrk; wrk++) { 4386 free(*wrk); 4387 } 4388 4389 free(target_environ); 4390 4391 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { 4392 qemu_log("guest_base 0x%lx\n", guest_base); 4393 log_page_dump(); 4394 4395 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 4396 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 4397 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 4398 info->start_code); 4399 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 4400 info->start_data); 4401 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 4402 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 4403 info->start_stack); 4404 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 4405 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 4406 } 4407 4408 target_set_brk(info->brk); 4409 syscall_init(); 4410 signal_init(); 4411 4412 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 4413 generating the prologue until now so that the prologue can take 4414 the real value of GUEST_BASE into account. */ 4415 tcg_prologue_init(&tcg_ctx); 4416 4417 #if defined(TARGET_I386) 4418 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 4419 env->hflags |= HF_PE_MASK | HF_CPL_MASK; 4420 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4421 env->cr[4] |= CR4_OSFXSR_MASK; 4422 env->hflags |= HF_OSFXSR_MASK; 4423 } 4424 #ifndef TARGET_ABI32 4425 /* enable 64 bit mode if possible */ 4426 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 4427 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 4428 exit(EXIT_FAILURE); 4429 } 4430 env->cr[4] |= CR4_PAE_MASK; 4431 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 4432 env->hflags |= HF_LMA_MASK; 4433 #endif 4434 4435 /* flags setup : we activate the IRQs by default as in user mode */ 4436 env->eflags |= IF_MASK; 4437 4438 /* linux register setup */ 4439 #ifndef TARGET_ABI32 4440 env->regs[R_EAX] = regs->rax; 4441 env->regs[R_EBX] = regs->rbx; 4442 env->regs[R_ECX] = regs->rcx; 4443 env->regs[R_EDX] = regs->rdx; 4444 env->regs[R_ESI] = regs->rsi; 4445 env->regs[R_EDI] = regs->rdi; 4446 env->regs[R_EBP] = regs->rbp; 4447 env->regs[R_ESP] = regs->rsp; 4448 env->eip = regs->rip; 4449 #else 4450 env->regs[R_EAX] = regs->eax; 4451 env->regs[R_EBX] = regs->ebx; 4452 env->regs[R_ECX] = regs->ecx; 4453 env->regs[R_EDX] = regs->edx; 4454 env->regs[R_ESI] = regs->esi; 4455 env->regs[R_EDI] = regs->edi; 4456 env->regs[R_EBP] = regs->ebp; 4457 env->regs[R_ESP] = regs->esp; 4458 env->eip = regs->eip; 4459 #endif 4460 4461 /* linux interrupt setup */ 4462 #ifndef TARGET_ABI32 4463 env->idt.limit = 511; 4464 #else 4465 env->idt.limit = 255; 4466 #endif 4467 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 4468 PROT_READ|PROT_WRITE, 4469 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4470 idt_table = g2h(env->idt.base); 4471 set_idt(0, 0); 4472 set_idt(1, 0); 4473 set_idt(2, 0); 4474 set_idt(3, 3); 4475 set_idt(4, 3); 4476 set_idt(5, 0); 4477 set_idt(6, 0); 4478 set_idt(7, 0); 4479 set_idt(8, 0); 4480 set_idt(9, 0); 4481 set_idt(10, 0); 4482 set_idt(11, 0); 4483 set_idt(12, 0); 4484 set_idt(13, 0); 4485 set_idt(14, 0); 4486 set_idt(15, 0); 4487 set_idt(16, 0); 4488 set_idt(17, 0); 4489 set_idt(18, 0); 4490 set_idt(19, 0); 4491 set_idt(0x80, 3); 4492 4493 /* linux segment setup */ 4494 { 4495 uint64_t *gdt_table; 4496 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 4497 PROT_READ|PROT_WRITE, 4498 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4499 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 4500 gdt_table = g2h(env->gdt.base); 4501 #ifdef TARGET_ABI32 4502 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4503 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4504 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4505 #else 4506 /* 64 bit code segment */ 4507 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4508 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4509 DESC_L_MASK | 4510 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4511 #endif 4512 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 4513 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4514 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 4515 } 4516 cpu_x86_load_seg(env, R_CS, __USER_CS); 4517 cpu_x86_load_seg(env, R_SS, __USER_DS); 4518 #ifdef TARGET_ABI32 4519 cpu_x86_load_seg(env, R_DS, __USER_DS); 4520 cpu_x86_load_seg(env, R_ES, __USER_DS); 4521 cpu_x86_load_seg(env, R_FS, __USER_DS); 4522 cpu_x86_load_seg(env, R_GS, __USER_DS); 4523 /* This hack makes Wine work... */ 4524 env->segs[R_FS].selector = 0; 4525 #else 4526 cpu_x86_load_seg(env, R_DS, 0); 4527 cpu_x86_load_seg(env, R_ES, 0); 4528 cpu_x86_load_seg(env, R_FS, 0); 4529 cpu_x86_load_seg(env, R_GS, 0); 4530 #endif 4531 #elif defined(TARGET_AARCH64) 4532 { 4533 int i; 4534 4535 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 4536 fprintf(stderr, 4537 "The selected ARM CPU does not support 64 bit mode\n"); 4538 exit(EXIT_FAILURE); 4539 } 4540 4541 for (i = 0; i < 31; i++) { 4542 env->xregs[i] = regs->regs[i]; 4543 } 4544 env->pc = regs->pc; 4545 env->xregs[31] = regs->sp; 4546 } 4547 #elif defined(TARGET_ARM) 4548 { 4549 int i; 4550 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, 4551 CPSRWriteByInstr); 4552 for(i = 0; i < 16; i++) { 4553 env->regs[i] = regs->uregs[i]; 4554 } 4555 #ifdef TARGET_WORDS_BIGENDIAN 4556 /* Enable BE8. */ 4557 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 4558 && (info->elf_flags & EF_ARM_BE8)) { 4559 env->uncached_cpsr |= CPSR_E; 4560 env->cp15.sctlr_el[1] |= SCTLR_E0E; 4561 } else { 4562 env->cp15.sctlr_el[1] |= SCTLR_B; 4563 } 4564 #endif 4565 } 4566 #elif defined(TARGET_UNICORE32) 4567 { 4568 int i; 4569 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 4570 for (i = 0; i < 32; i++) { 4571 env->regs[i] = regs->uregs[i]; 4572 } 4573 } 4574 #elif defined(TARGET_SPARC) 4575 { 4576 int i; 4577 env->pc = regs->pc; 4578 env->npc = regs->npc; 4579 env->y = regs->y; 4580 for(i = 0; i < 8; i++) 4581 env->gregs[i] = regs->u_regs[i]; 4582 for(i = 0; i < 8; i++) 4583 env->regwptr[i] = regs->u_regs[i + 8]; 4584 } 4585 #elif defined(TARGET_PPC) 4586 { 4587 int i; 4588 4589 #if defined(TARGET_PPC64) 4590 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; 4591 #if defined(TARGET_ABI32) 4592 env->msr &= ~((target_ulong)1 << flag); 4593 #else 4594 env->msr |= (target_ulong)1 << flag; 4595 #endif 4596 #endif 4597 env->nip = regs->nip; 4598 for(i = 0; i < 32; i++) { 4599 env->gpr[i] = regs->gpr[i]; 4600 } 4601 } 4602 #elif defined(TARGET_M68K) 4603 { 4604 env->pc = regs->pc; 4605 env->dregs[0] = regs->d0; 4606 env->dregs[1] = regs->d1; 4607 env->dregs[2] = regs->d2; 4608 env->dregs[3] = regs->d3; 4609 env->dregs[4] = regs->d4; 4610 env->dregs[5] = regs->d5; 4611 env->dregs[6] = regs->d6; 4612 env->dregs[7] = regs->d7; 4613 env->aregs[0] = regs->a0; 4614 env->aregs[1] = regs->a1; 4615 env->aregs[2] = regs->a2; 4616 env->aregs[3] = regs->a3; 4617 env->aregs[4] = regs->a4; 4618 env->aregs[5] = regs->a5; 4619 env->aregs[6] = regs->a6; 4620 env->aregs[7] = regs->usp; 4621 env->sr = regs->sr; 4622 ts->sim_syscalls = 1; 4623 } 4624 #elif defined(TARGET_MICROBLAZE) 4625 { 4626 env->regs[0] = regs->r0; 4627 env->regs[1] = regs->r1; 4628 env->regs[2] = regs->r2; 4629 env->regs[3] = regs->r3; 4630 env->regs[4] = regs->r4; 4631 env->regs[5] = regs->r5; 4632 env->regs[6] = regs->r6; 4633 env->regs[7] = regs->r7; 4634 env->regs[8] = regs->r8; 4635 env->regs[9] = regs->r9; 4636 env->regs[10] = regs->r10; 4637 env->regs[11] = regs->r11; 4638 env->regs[12] = regs->r12; 4639 env->regs[13] = regs->r13; 4640 env->regs[14] = regs->r14; 4641 env->regs[15] = regs->r15; 4642 env->regs[16] = regs->r16; 4643 env->regs[17] = regs->r17; 4644 env->regs[18] = regs->r18; 4645 env->regs[19] = regs->r19; 4646 env->regs[20] = regs->r20; 4647 env->regs[21] = regs->r21; 4648 env->regs[22] = regs->r22; 4649 env->regs[23] = regs->r23; 4650 env->regs[24] = regs->r24; 4651 env->regs[25] = regs->r25; 4652 env->regs[26] = regs->r26; 4653 env->regs[27] = regs->r27; 4654 env->regs[28] = regs->r28; 4655 env->regs[29] = regs->r29; 4656 env->regs[30] = regs->r30; 4657 env->regs[31] = regs->r31; 4658 env->sregs[SR_PC] = regs->pc; 4659 } 4660 #elif defined(TARGET_MIPS) 4661 { 4662 int i; 4663 4664 for(i = 0; i < 32; i++) { 4665 env->active_tc.gpr[i] = regs->regs[i]; 4666 } 4667 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 4668 if (regs->cp0_epc & 1) { 4669 env->hflags |= MIPS_HFLAG_M16; 4670 } 4671 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != 4672 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { 4673 if ((env->active_fpu.fcr31_rw_bitmask & 4674 (1 << FCR31_NAN2008)) == 0) { 4675 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); 4676 exit(1); 4677 } 4678 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { 4679 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); 4680 } else { 4681 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); 4682 } 4683 restore_snan_bit_mode(env); 4684 } 4685 } 4686 #elif defined(TARGET_OPENRISC) 4687 { 4688 int i; 4689 4690 for (i = 0; i < 32; i++) { 4691 env->gpr[i] = regs->gpr[i]; 4692 } 4693 4694 env->sr = regs->sr; 4695 env->pc = regs->pc; 4696 } 4697 #elif defined(TARGET_SH4) 4698 { 4699 int i; 4700 4701 for(i = 0; i < 16; i++) { 4702 env->gregs[i] = regs->regs[i]; 4703 } 4704 env->pc = regs->pc; 4705 } 4706 #elif defined(TARGET_ALPHA) 4707 { 4708 int i; 4709 4710 for(i = 0; i < 28; i++) { 4711 env->ir[i] = ((abi_ulong *)regs)[i]; 4712 } 4713 env->ir[IR_SP] = regs->usp; 4714 env->pc = regs->pc; 4715 } 4716 #elif defined(TARGET_CRIS) 4717 { 4718 env->regs[0] = regs->r0; 4719 env->regs[1] = regs->r1; 4720 env->regs[2] = regs->r2; 4721 env->regs[3] = regs->r3; 4722 env->regs[4] = regs->r4; 4723 env->regs[5] = regs->r5; 4724 env->regs[6] = regs->r6; 4725 env->regs[7] = regs->r7; 4726 env->regs[8] = regs->r8; 4727 env->regs[9] = regs->r9; 4728 env->regs[10] = regs->r10; 4729 env->regs[11] = regs->r11; 4730 env->regs[12] = regs->r12; 4731 env->regs[13] = regs->r13; 4732 env->regs[14] = info->start_stack; 4733 env->regs[15] = regs->acr; 4734 env->pc = regs->erp; 4735 } 4736 #elif defined(TARGET_S390X) 4737 { 4738 int i; 4739 for (i = 0; i < 16; i++) { 4740 env->regs[i] = regs->gprs[i]; 4741 } 4742 env->psw.mask = regs->psw.mask; 4743 env->psw.addr = regs->psw.addr; 4744 } 4745 #elif defined(TARGET_TILEGX) 4746 { 4747 int i; 4748 for (i = 0; i < TILEGX_R_COUNT; i++) { 4749 env->regs[i] = regs->regs[i]; 4750 } 4751 for (i = 0; i < TILEGX_SPR_COUNT; i++) { 4752 env->spregs[i] = 0; 4753 } 4754 env->pc = regs->pc; 4755 } 4756 #else 4757 #error unsupported target CPU 4758 #endif 4759 4760 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4761 ts->stack_base = info->start_stack; 4762 ts->heap_base = info->brk; 4763 /* This will be filled in on the first SYS_HEAPINFO call. */ 4764 ts->heap_limit = 0; 4765 #endif 4766 4767 if (gdbstub_port) { 4768 if (gdbserver_start(gdbstub_port) < 0) { 4769 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4770 gdbstub_port); 4771 exit(EXIT_FAILURE); 4772 } 4773 gdb_handlesig(cpu, 0); 4774 } 4775 cpu_loop(env); 4776 /* never exits */ 4777 return 0; 4778 } 4779