1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <stdlib.h> 20 #include <stdio.h> 21 #include <stdarg.h> 22 #include <string.h> 23 #include <errno.h> 24 #include <unistd.h> 25 #include <sys/mman.h> 26 #include <sys/syscall.h> 27 #include <sys/resource.h> 28 29 #include "qemu.h" 30 #include "qemu-common.h" 31 #include "cpu.h" 32 #include "tcg.h" 33 #include "qemu/timer.h" 34 #include "qemu/envlist.h" 35 #include "elf.h" 36 37 char *exec_path; 38 39 int singlestep; 40 const char *filename; 41 const char *argv0; 42 int gdbstub_port; 43 envlist_t *envlist; 44 static const char *cpu_model; 45 unsigned long mmap_min_addr; 46 #if defined(CONFIG_USE_GUEST_BASE) 47 unsigned long guest_base; 48 int have_guest_base; 49 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 50 /* 51 * When running 32-on-64 we should make sure we can fit all of the possible 52 * guest address space into a contiguous chunk of virtual host memory. 53 * 54 * This way we will never overlap with our own libraries or binaries or stack 55 * or anything else that QEMU maps. 56 */ 57 # ifdef TARGET_MIPS 58 /* MIPS only supports 31 bits of virtual address space for user space */ 59 unsigned long reserved_va = 0x77000000; 60 # else 61 unsigned long reserved_va = 0xf7000000; 62 # endif 63 #else 64 unsigned long reserved_va; 65 #endif 66 #endif 67 68 static void usage(void); 69 70 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 71 const char *qemu_uname_release; 72 73 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 74 we allocate a bigger stack. Need a better solution, for example 75 by remapping the process stack directly at the right place */ 76 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 77 78 void gemu_log(const char *fmt, ...) 79 { 80 va_list ap; 81 82 va_start(ap, fmt); 83 vfprintf(stderr, fmt, ap); 84 va_end(ap); 85 } 86 87 #if defined(TARGET_I386) 88 int cpu_get_pic_interrupt(CPUX86State *env) 89 { 90 return -1; 91 } 92 #endif 93 94 /***********************************************************/ 95 /* Helper routines for implementing atomic operations. */ 96 97 /* To implement exclusive operations we force all cpus to syncronise. 98 We don't require a full sync, only that no cpus are executing guest code. 99 The alternative is to map target atomic ops onto host equivalents, 100 which requires quite a lot of per host/target work. */ 101 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; 102 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 103 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 104 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 105 static int pending_cpus; 106 107 /* Make sure everything is in a consistent state for calling fork(). */ 108 void fork_start(void) 109 { 110 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 111 pthread_mutex_lock(&exclusive_lock); 112 mmap_fork_start(); 113 } 114 115 void fork_end(int child) 116 { 117 mmap_fork_end(child); 118 if (child) { 119 CPUState *cpu, *next_cpu; 120 /* Child processes created by fork() only have a single thread. 121 Discard information about the parent threads. */ 122 CPU_FOREACH_SAFE(cpu, next_cpu) { 123 if (cpu != thread_cpu) { 124 QTAILQ_REMOVE(&cpus, thread_cpu, node); 125 } 126 } 127 pending_cpus = 0; 128 pthread_mutex_init(&exclusive_lock, NULL); 129 pthread_mutex_init(&cpu_list_mutex, NULL); 130 pthread_cond_init(&exclusive_cond, NULL); 131 pthread_cond_init(&exclusive_resume, NULL); 132 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL); 133 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); 134 } else { 135 pthread_mutex_unlock(&exclusive_lock); 136 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 137 } 138 } 139 140 /* Wait for pending exclusive operations to complete. The exclusive lock 141 must be held. */ 142 static inline void exclusive_idle(void) 143 { 144 while (pending_cpus) { 145 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 146 } 147 } 148 149 /* Start an exclusive operation. 150 Must only be called from outside cpu_arm_exec. */ 151 static inline void start_exclusive(void) 152 { 153 CPUState *other_cpu; 154 155 pthread_mutex_lock(&exclusive_lock); 156 exclusive_idle(); 157 158 pending_cpus = 1; 159 /* Make all other cpus stop executing. */ 160 CPU_FOREACH(other_cpu) { 161 if (other_cpu->running) { 162 pending_cpus++; 163 cpu_exit(other_cpu); 164 } 165 } 166 if (pending_cpus > 1) { 167 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 168 } 169 } 170 171 /* Finish an exclusive operation. */ 172 static inline void __attribute__((unused)) end_exclusive(void) 173 { 174 pending_cpus = 0; 175 pthread_cond_broadcast(&exclusive_resume); 176 pthread_mutex_unlock(&exclusive_lock); 177 } 178 179 /* Wait for exclusive ops to finish, and begin cpu execution. */ 180 static inline void cpu_exec_start(CPUState *cpu) 181 { 182 pthread_mutex_lock(&exclusive_lock); 183 exclusive_idle(); 184 cpu->running = true; 185 pthread_mutex_unlock(&exclusive_lock); 186 } 187 188 /* Mark cpu as not executing, and release pending exclusive ops. */ 189 static inline void cpu_exec_end(CPUState *cpu) 190 { 191 pthread_mutex_lock(&exclusive_lock); 192 cpu->running = false; 193 if (pending_cpus > 1) { 194 pending_cpus--; 195 if (pending_cpus == 1) { 196 pthread_cond_signal(&exclusive_cond); 197 } 198 } 199 exclusive_idle(); 200 pthread_mutex_unlock(&exclusive_lock); 201 } 202 203 void cpu_list_lock(void) 204 { 205 pthread_mutex_lock(&cpu_list_mutex); 206 } 207 208 void cpu_list_unlock(void) 209 { 210 pthread_mutex_unlock(&cpu_list_mutex); 211 } 212 213 214 #ifdef TARGET_I386 215 /***********************************************************/ 216 /* CPUX86 core interface */ 217 218 void cpu_smm_update(CPUX86State *env) 219 { 220 } 221 222 uint64_t cpu_get_tsc(CPUX86State *env) 223 { 224 return cpu_get_real_ticks(); 225 } 226 227 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 228 int flags) 229 { 230 unsigned int e1, e2; 231 uint32_t *p; 232 e1 = (addr << 16) | (limit & 0xffff); 233 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 234 e2 |= flags; 235 p = ptr; 236 p[0] = tswap32(e1); 237 p[1] = tswap32(e2); 238 } 239 240 static uint64_t *idt_table; 241 #ifdef TARGET_X86_64 242 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 243 uint64_t addr, unsigned int sel) 244 { 245 uint32_t *p, e1, e2; 246 e1 = (addr & 0xffff) | (sel << 16); 247 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 248 p = ptr; 249 p[0] = tswap32(e1); 250 p[1] = tswap32(e2); 251 p[2] = tswap32(addr >> 32); 252 p[3] = 0; 253 } 254 /* only dpl matters as we do only user space emulation */ 255 static void set_idt(int n, unsigned int dpl) 256 { 257 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 258 } 259 #else 260 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 261 uint32_t addr, unsigned int sel) 262 { 263 uint32_t *p, e1, e2; 264 e1 = (addr & 0xffff) | (sel << 16); 265 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 266 p = ptr; 267 p[0] = tswap32(e1); 268 p[1] = tswap32(e2); 269 } 270 271 /* only dpl matters as we do only user space emulation */ 272 static void set_idt(int n, unsigned int dpl) 273 { 274 set_gate(idt_table + n, 0, dpl, 0, 0); 275 } 276 #endif 277 278 void cpu_loop(CPUX86State *env) 279 { 280 CPUState *cs = CPU(x86_env_get_cpu(env)); 281 int trapnr; 282 abi_ulong pc; 283 target_siginfo_t info; 284 285 for(;;) { 286 cpu_exec_start(cs); 287 trapnr = cpu_x86_exec(env); 288 cpu_exec_end(cs); 289 switch(trapnr) { 290 case 0x80: 291 /* linux syscall from int $0x80 */ 292 env->regs[R_EAX] = do_syscall(env, 293 env->regs[R_EAX], 294 env->regs[R_EBX], 295 env->regs[R_ECX], 296 env->regs[R_EDX], 297 env->regs[R_ESI], 298 env->regs[R_EDI], 299 env->regs[R_EBP], 300 0, 0); 301 break; 302 #ifndef TARGET_ABI32 303 case EXCP_SYSCALL: 304 /* linux syscall from syscall instruction */ 305 env->regs[R_EAX] = do_syscall(env, 306 env->regs[R_EAX], 307 env->regs[R_EDI], 308 env->regs[R_ESI], 309 env->regs[R_EDX], 310 env->regs[10], 311 env->regs[8], 312 env->regs[9], 313 0, 0); 314 break; 315 #endif 316 case EXCP0B_NOSEG: 317 case EXCP0C_STACK: 318 info.si_signo = SIGBUS; 319 info.si_errno = 0; 320 info.si_code = TARGET_SI_KERNEL; 321 info._sifields._sigfault._addr = 0; 322 queue_signal(env, info.si_signo, &info); 323 break; 324 case EXCP0D_GPF: 325 /* XXX: potential problem if ABI32 */ 326 #ifndef TARGET_X86_64 327 if (env->eflags & VM_MASK) { 328 handle_vm86_fault(env); 329 } else 330 #endif 331 { 332 info.si_signo = SIGSEGV; 333 info.si_errno = 0; 334 info.si_code = TARGET_SI_KERNEL; 335 info._sifields._sigfault._addr = 0; 336 queue_signal(env, info.si_signo, &info); 337 } 338 break; 339 case EXCP0E_PAGE: 340 info.si_signo = SIGSEGV; 341 info.si_errno = 0; 342 if (!(env->error_code & 1)) 343 info.si_code = TARGET_SEGV_MAPERR; 344 else 345 info.si_code = TARGET_SEGV_ACCERR; 346 info._sifields._sigfault._addr = env->cr[2]; 347 queue_signal(env, info.si_signo, &info); 348 break; 349 case EXCP00_DIVZ: 350 #ifndef TARGET_X86_64 351 if (env->eflags & VM_MASK) { 352 handle_vm86_trap(env, trapnr); 353 } else 354 #endif 355 { 356 /* division by zero */ 357 info.si_signo = SIGFPE; 358 info.si_errno = 0; 359 info.si_code = TARGET_FPE_INTDIV; 360 info._sifields._sigfault._addr = env->eip; 361 queue_signal(env, info.si_signo, &info); 362 } 363 break; 364 case EXCP01_DB: 365 case EXCP03_INT3: 366 #ifndef TARGET_X86_64 367 if (env->eflags & VM_MASK) { 368 handle_vm86_trap(env, trapnr); 369 } else 370 #endif 371 { 372 info.si_signo = SIGTRAP; 373 info.si_errno = 0; 374 if (trapnr == EXCP01_DB) { 375 info.si_code = TARGET_TRAP_BRKPT; 376 info._sifields._sigfault._addr = env->eip; 377 } else { 378 info.si_code = TARGET_SI_KERNEL; 379 info._sifields._sigfault._addr = 0; 380 } 381 queue_signal(env, info.si_signo, &info); 382 } 383 break; 384 case EXCP04_INTO: 385 case EXCP05_BOUND: 386 #ifndef TARGET_X86_64 387 if (env->eflags & VM_MASK) { 388 handle_vm86_trap(env, trapnr); 389 } else 390 #endif 391 { 392 info.si_signo = SIGSEGV; 393 info.si_errno = 0; 394 info.si_code = TARGET_SI_KERNEL; 395 info._sifields._sigfault._addr = 0; 396 queue_signal(env, info.si_signo, &info); 397 } 398 break; 399 case EXCP06_ILLOP: 400 info.si_signo = SIGILL; 401 info.si_errno = 0; 402 info.si_code = TARGET_ILL_ILLOPN; 403 info._sifields._sigfault._addr = env->eip; 404 queue_signal(env, info.si_signo, &info); 405 break; 406 case EXCP_INTERRUPT: 407 /* just indicate that signals should be handled asap */ 408 break; 409 case EXCP_DEBUG: 410 { 411 int sig; 412 413 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 414 if (sig) 415 { 416 info.si_signo = sig; 417 info.si_errno = 0; 418 info.si_code = TARGET_TRAP_BRKPT; 419 queue_signal(env, info.si_signo, &info); 420 } 421 } 422 break; 423 default: 424 pc = env->segs[R_CS].base + env->eip; 425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 426 (long)pc, trapnr); 427 abort(); 428 } 429 process_pending_signals(env); 430 } 431 } 432 #endif 433 434 #ifdef TARGET_ARM 435 436 #define get_user_code_u32(x, gaddr, doswap) \ 437 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 438 if (!__r && (doswap)) { \ 439 (x) = bswap32(x); \ 440 } \ 441 __r; \ 442 }) 443 444 #define get_user_code_u16(x, gaddr, doswap) \ 445 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 446 if (!__r && (doswap)) { \ 447 (x) = bswap16(x); \ 448 } \ 449 __r; \ 450 }) 451 452 #ifdef TARGET_ABI32 453 /* Commpage handling -- there is no commpage for AArch64 */ 454 455 /* 456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 457 * Input: 458 * r0 = pointer to oldval 459 * r1 = pointer to newval 460 * r2 = pointer to target value 461 * 462 * Output: 463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 464 * C set if *ptr was changed, clear if no exchange happened 465 * 466 * Note segv's in kernel helpers are a bit tricky, we can set the 467 * data address sensibly but the PC address is just the entry point. 468 */ 469 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 470 { 471 uint64_t oldval, newval, val; 472 uint32_t addr, cpsr; 473 target_siginfo_t info; 474 475 /* Based on the 32 bit code in do_kernel_trap */ 476 477 /* XXX: This only works between threads, not between processes. 478 It's probably possible to implement this with native host 479 operations. However things like ldrex/strex are much harder so 480 there's not much point trying. */ 481 start_exclusive(); 482 cpsr = cpsr_read(env); 483 addr = env->regs[2]; 484 485 if (get_user_u64(oldval, env->regs[0])) { 486 env->exception.vaddress = env->regs[0]; 487 goto segv; 488 }; 489 490 if (get_user_u64(newval, env->regs[1])) { 491 env->exception.vaddress = env->regs[1]; 492 goto segv; 493 }; 494 495 if (get_user_u64(val, addr)) { 496 env->exception.vaddress = addr; 497 goto segv; 498 } 499 500 if (val == oldval) { 501 val = newval; 502 503 if (put_user_u64(val, addr)) { 504 env->exception.vaddress = addr; 505 goto segv; 506 }; 507 508 env->regs[0] = 0; 509 cpsr |= CPSR_C; 510 } else { 511 env->regs[0] = -1; 512 cpsr &= ~CPSR_C; 513 } 514 cpsr_write(env, cpsr, CPSR_C); 515 end_exclusive(); 516 return; 517 518 segv: 519 end_exclusive(); 520 /* We get the PC of the entry address - which is as good as anything, 521 on a real kernel what you get depends on which mode it uses. */ 522 info.si_signo = SIGSEGV; 523 info.si_errno = 0; 524 /* XXX: check env->error_code */ 525 info.si_code = TARGET_SEGV_MAPERR; 526 info._sifields._sigfault._addr = env->exception.vaddress; 527 queue_signal(env, info.si_signo, &info); 528 529 end_exclusive(); 530 } 531 532 /* Handle a jump to the kernel code page. */ 533 static int 534 do_kernel_trap(CPUARMState *env) 535 { 536 uint32_t addr; 537 uint32_t cpsr; 538 uint32_t val; 539 540 switch (env->regs[15]) { 541 case 0xffff0fa0: /* __kernel_memory_barrier */ 542 /* ??? No-op. Will need to do better for SMP. */ 543 break; 544 case 0xffff0fc0: /* __kernel_cmpxchg */ 545 /* XXX: This only works between threads, not between processes. 546 It's probably possible to implement this with native host 547 operations. However things like ldrex/strex are much harder so 548 there's not much point trying. */ 549 start_exclusive(); 550 cpsr = cpsr_read(env); 551 addr = env->regs[2]; 552 /* FIXME: This should SEGV if the access fails. */ 553 if (get_user_u32(val, addr)) 554 val = ~env->regs[0]; 555 if (val == env->regs[0]) { 556 val = env->regs[1]; 557 /* FIXME: Check for segfaults. */ 558 put_user_u32(val, addr); 559 env->regs[0] = 0; 560 cpsr |= CPSR_C; 561 } else { 562 env->regs[0] = -1; 563 cpsr &= ~CPSR_C; 564 } 565 cpsr_write(env, cpsr, CPSR_C); 566 end_exclusive(); 567 break; 568 case 0xffff0fe0: /* __kernel_get_tls */ 569 env->regs[0] = env->cp15.tpidrro_el[0]; 570 break; 571 case 0xffff0f60: /* __kernel_cmpxchg64 */ 572 arm_kernel_cmpxchg64_helper(env); 573 break; 574 575 default: 576 return 1; 577 } 578 /* Jump back to the caller. */ 579 addr = env->regs[14]; 580 if (addr & 1) { 581 env->thumb = 1; 582 addr &= ~1; 583 } 584 env->regs[15] = addr; 585 586 return 0; 587 } 588 589 /* Store exclusive handling for AArch32 */ 590 static int do_strex(CPUARMState *env) 591 { 592 uint64_t val; 593 int size; 594 int rc = 1; 595 int segv = 0; 596 uint32_t addr; 597 start_exclusive(); 598 if (env->exclusive_addr != env->exclusive_test) { 599 goto fail; 600 } 601 /* We know we're always AArch32 so the address is in uint32_t range 602 * unless it was the -1 exclusive-monitor-lost value (which won't 603 * match exclusive_test above). 604 */ 605 assert(extract64(env->exclusive_addr, 32, 32) == 0); 606 addr = env->exclusive_addr; 607 size = env->exclusive_info & 0xf; 608 switch (size) { 609 case 0: 610 segv = get_user_u8(val, addr); 611 break; 612 case 1: 613 segv = get_user_u16(val, addr); 614 break; 615 case 2: 616 case 3: 617 segv = get_user_u32(val, addr); 618 break; 619 default: 620 abort(); 621 } 622 if (segv) { 623 env->exception.vaddress = addr; 624 goto done; 625 } 626 if (size == 3) { 627 uint32_t valhi; 628 segv = get_user_u32(valhi, addr + 4); 629 if (segv) { 630 env->exception.vaddress = addr + 4; 631 goto done; 632 } 633 val = deposit64(val, 32, 32, valhi); 634 } 635 if (val != env->exclusive_val) { 636 goto fail; 637 } 638 639 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 640 switch (size) { 641 case 0: 642 segv = put_user_u8(val, addr); 643 break; 644 case 1: 645 segv = put_user_u16(val, addr); 646 break; 647 case 2: 648 case 3: 649 segv = put_user_u32(val, addr); 650 break; 651 } 652 if (segv) { 653 env->exception.vaddress = addr; 654 goto done; 655 } 656 if (size == 3) { 657 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 658 segv = put_user_u32(val, addr + 4); 659 if (segv) { 660 env->exception.vaddress = addr + 4; 661 goto done; 662 } 663 } 664 rc = 0; 665 fail: 666 env->regs[15] += 4; 667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 668 done: 669 end_exclusive(); 670 return segv; 671 } 672 673 void cpu_loop(CPUARMState *env) 674 { 675 CPUState *cs = CPU(arm_env_get_cpu(env)); 676 int trapnr; 677 unsigned int n, insn; 678 target_siginfo_t info; 679 uint32_t addr; 680 681 for(;;) { 682 cpu_exec_start(cs); 683 trapnr = cpu_arm_exec(env); 684 cpu_exec_end(cs); 685 switch(trapnr) { 686 case EXCP_UDEF: 687 { 688 TaskState *ts = cs->opaque; 689 uint32_t opcode; 690 int rc; 691 692 /* we handle the FPU emulation here, as Linux */ 693 /* we get the opcode */ 694 /* FIXME - what to do if get_user() fails? */ 695 get_user_code_u32(opcode, env->regs[15], env->bswap_code); 696 697 rc = EmulateAll(opcode, &ts->fpa, env); 698 if (rc == 0) { /* illegal instruction */ 699 info.si_signo = SIGILL; 700 info.si_errno = 0; 701 info.si_code = TARGET_ILL_ILLOPN; 702 info._sifields._sigfault._addr = env->regs[15]; 703 queue_signal(env, info.si_signo, &info); 704 } else if (rc < 0) { /* FP exception */ 705 int arm_fpe=0; 706 707 /* translate softfloat flags to FPSR flags */ 708 if (-rc & float_flag_invalid) 709 arm_fpe |= BIT_IOC; 710 if (-rc & float_flag_divbyzero) 711 arm_fpe |= BIT_DZC; 712 if (-rc & float_flag_overflow) 713 arm_fpe |= BIT_OFC; 714 if (-rc & float_flag_underflow) 715 arm_fpe |= BIT_UFC; 716 if (-rc & float_flag_inexact) 717 arm_fpe |= BIT_IXC; 718 719 FPSR fpsr = ts->fpa.fpsr; 720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 721 722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 723 info.si_signo = SIGFPE; 724 info.si_errno = 0; 725 726 /* ordered by priority, least first */ 727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 732 733 info._sifields._sigfault._addr = env->regs[15]; 734 queue_signal(env, info.si_signo, &info); 735 } else { 736 env->regs[15] += 4; 737 } 738 739 /* accumulate unenabled exceptions */ 740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 741 fpsr |= BIT_IXC; 742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 743 fpsr |= BIT_UFC; 744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 745 fpsr |= BIT_OFC; 746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 747 fpsr |= BIT_DZC; 748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 749 fpsr |= BIT_IOC; 750 ts->fpa.fpsr=fpsr; 751 } else { /* everything OK */ 752 /* increment PC */ 753 env->regs[15] += 4; 754 } 755 } 756 break; 757 case EXCP_SWI: 758 case EXCP_BKPT: 759 { 760 env->eabi = 1; 761 /* system call */ 762 if (trapnr == EXCP_BKPT) { 763 if (env->thumb) { 764 /* FIXME - what to do if get_user() fails? */ 765 get_user_code_u16(insn, env->regs[15], env->bswap_code); 766 n = insn & 0xff; 767 env->regs[15] += 2; 768 } else { 769 /* FIXME - what to do if get_user() fails? */ 770 get_user_code_u32(insn, env->regs[15], env->bswap_code); 771 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 772 env->regs[15] += 4; 773 } 774 } else { 775 if (env->thumb) { 776 /* FIXME - what to do if get_user() fails? */ 777 get_user_code_u16(insn, env->regs[15] - 2, 778 env->bswap_code); 779 n = insn & 0xff; 780 } else { 781 /* FIXME - what to do if get_user() fails? */ 782 get_user_code_u32(insn, env->regs[15] - 4, 783 env->bswap_code); 784 n = insn & 0xffffff; 785 } 786 } 787 788 if (n == ARM_NR_cacheflush) { 789 /* nop */ 790 } else if (n == ARM_NR_semihosting 791 || n == ARM_NR_thumb_semihosting) { 792 env->regs[0] = do_arm_semihosting (env); 793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 794 /* linux syscall */ 795 if (env->thumb || n == 0) { 796 n = env->regs[7]; 797 } else { 798 n -= ARM_SYSCALL_BASE; 799 env->eabi = 0; 800 } 801 if ( n > ARM_NR_BASE) { 802 switch (n) { 803 case ARM_NR_cacheflush: 804 /* nop */ 805 break; 806 case ARM_NR_set_tls: 807 cpu_set_tls(env, env->regs[0]); 808 env->regs[0] = 0; 809 break; 810 case ARM_NR_breakpoint: 811 env->regs[15] -= env->thumb ? 2 : 4; 812 goto excp_debug; 813 default: 814 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 815 n); 816 env->regs[0] = -TARGET_ENOSYS; 817 break; 818 } 819 } else { 820 env->regs[0] = do_syscall(env, 821 n, 822 env->regs[0], 823 env->regs[1], 824 env->regs[2], 825 env->regs[3], 826 env->regs[4], 827 env->regs[5], 828 0, 0); 829 } 830 } else { 831 goto error; 832 } 833 } 834 break; 835 case EXCP_INTERRUPT: 836 /* just indicate that signals should be handled asap */ 837 break; 838 case EXCP_STREX: 839 if (!do_strex(env)) { 840 break; 841 } 842 /* fall through for segv */ 843 case EXCP_PREFETCH_ABORT: 844 case EXCP_DATA_ABORT: 845 addr = env->exception.vaddress; 846 { 847 info.si_signo = SIGSEGV; 848 info.si_errno = 0; 849 /* XXX: check env->error_code */ 850 info.si_code = TARGET_SEGV_MAPERR; 851 info._sifields._sigfault._addr = addr; 852 queue_signal(env, info.si_signo, &info); 853 } 854 break; 855 case EXCP_DEBUG: 856 excp_debug: 857 { 858 int sig; 859 860 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 861 if (sig) 862 { 863 info.si_signo = sig; 864 info.si_errno = 0; 865 info.si_code = TARGET_TRAP_BRKPT; 866 queue_signal(env, info.si_signo, &info); 867 } 868 } 869 break; 870 case EXCP_KERNEL_TRAP: 871 if (do_kernel_trap(env)) 872 goto error; 873 break; 874 default: 875 error: 876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 877 trapnr); 878 cpu_dump_state(cs, stderr, fprintf, 0); 879 abort(); 880 } 881 process_pending_signals(env); 882 } 883 } 884 885 #else 886 887 /* 888 * Handle AArch64 store-release exclusive 889 * 890 * rs = gets the status result of store exclusive 891 * rt = is the register that is stored 892 * rt2 = is the second register store (in STP) 893 * 894 */ 895 static int do_strex_a64(CPUARMState *env) 896 { 897 uint64_t val; 898 int size; 899 bool is_pair; 900 int rc = 1; 901 int segv = 0; 902 uint64_t addr; 903 int rs, rt, rt2; 904 905 start_exclusive(); 906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ 907 size = extract32(env->exclusive_info, 0, 2); 908 is_pair = extract32(env->exclusive_info, 2, 1); 909 rs = extract32(env->exclusive_info, 4, 5); 910 rt = extract32(env->exclusive_info, 9, 5); 911 rt2 = extract32(env->exclusive_info, 14, 5); 912 913 addr = env->exclusive_addr; 914 915 if (addr != env->exclusive_test) { 916 goto finish; 917 } 918 919 switch (size) { 920 case 0: 921 segv = get_user_u8(val, addr); 922 break; 923 case 1: 924 segv = get_user_u16(val, addr); 925 break; 926 case 2: 927 segv = get_user_u32(val, addr); 928 break; 929 case 3: 930 segv = get_user_u64(val, addr); 931 break; 932 default: 933 abort(); 934 } 935 if (segv) { 936 env->exception.vaddress = addr; 937 goto error; 938 } 939 if (val != env->exclusive_val) { 940 goto finish; 941 } 942 if (is_pair) { 943 if (size == 2) { 944 segv = get_user_u32(val, addr + 4); 945 } else { 946 segv = get_user_u64(val, addr + 8); 947 } 948 if (segv) { 949 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 950 goto error; 951 } 952 if (val != env->exclusive_high) { 953 goto finish; 954 } 955 } 956 /* handle the zero register */ 957 val = rt == 31 ? 0 : env->xregs[rt]; 958 switch (size) { 959 case 0: 960 segv = put_user_u8(val, addr); 961 break; 962 case 1: 963 segv = put_user_u16(val, addr); 964 break; 965 case 2: 966 segv = put_user_u32(val, addr); 967 break; 968 case 3: 969 segv = put_user_u64(val, addr); 970 break; 971 } 972 if (segv) { 973 goto error; 974 } 975 if (is_pair) { 976 /* handle the zero register */ 977 val = rt2 == 31 ? 0 : env->xregs[rt2]; 978 if (size == 2) { 979 segv = put_user_u32(val, addr + 4); 980 } else { 981 segv = put_user_u64(val, addr + 8); 982 } 983 if (segv) { 984 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 985 goto error; 986 } 987 } 988 rc = 0; 989 finish: 990 env->pc += 4; 991 /* rs == 31 encodes a write to the ZR, thus throwing away 992 * the status return. This is rather silly but valid. 993 */ 994 if (rs < 31) { 995 env->xregs[rs] = rc; 996 } 997 error: 998 /* instruction faulted, PC does not advance */ 999 /* either way a strex releases any exclusive lock we have */ 1000 env->exclusive_addr = -1; 1001 end_exclusive(); 1002 return segv; 1003 } 1004 1005 /* AArch64 main loop */ 1006 void cpu_loop(CPUARMState *env) 1007 { 1008 CPUState *cs = CPU(arm_env_get_cpu(env)); 1009 int trapnr, sig; 1010 target_siginfo_t info; 1011 1012 for (;;) { 1013 cpu_exec_start(cs); 1014 trapnr = cpu_arm_exec(env); 1015 cpu_exec_end(cs); 1016 1017 switch (trapnr) { 1018 case EXCP_SWI: 1019 env->xregs[0] = do_syscall(env, 1020 env->xregs[8], 1021 env->xregs[0], 1022 env->xregs[1], 1023 env->xregs[2], 1024 env->xregs[3], 1025 env->xregs[4], 1026 env->xregs[5], 1027 0, 0); 1028 break; 1029 case EXCP_INTERRUPT: 1030 /* just indicate that signals should be handled asap */ 1031 break; 1032 case EXCP_UDEF: 1033 info.si_signo = SIGILL; 1034 info.si_errno = 0; 1035 info.si_code = TARGET_ILL_ILLOPN; 1036 info._sifields._sigfault._addr = env->pc; 1037 queue_signal(env, info.si_signo, &info); 1038 break; 1039 case EXCP_STREX: 1040 if (!do_strex_a64(env)) { 1041 break; 1042 } 1043 /* fall through for segv */ 1044 case EXCP_PREFETCH_ABORT: 1045 case EXCP_DATA_ABORT: 1046 info.si_signo = SIGSEGV; 1047 info.si_errno = 0; 1048 /* XXX: check env->error_code */ 1049 info.si_code = TARGET_SEGV_MAPERR; 1050 info._sifields._sigfault._addr = env->exception.vaddress; 1051 queue_signal(env, info.si_signo, &info); 1052 break; 1053 case EXCP_DEBUG: 1054 case EXCP_BKPT: 1055 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1056 if (sig) { 1057 info.si_signo = sig; 1058 info.si_errno = 0; 1059 info.si_code = TARGET_TRAP_BRKPT; 1060 queue_signal(env, info.si_signo, &info); 1061 } 1062 break; 1063 default: 1064 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 1065 trapnr); 1066 cpu_dump_state(cs, stderr, fprintf, 0); 1067 abort(); 1068 } 1069 process_pending_signals(env); 1070 /* Exception return on AArch64 always clears the exclusive monitor, 1071 * so any return to running guest code implies this. 1072 * A strex (successful or otherwise) also clears the monitor, so 1073 * we don't need to specialcase EXCP_STREX. 1074 */ 1075 env->exclusive_addr = -1; 1076 } 1077 } 1078 #endif /* ndef TARGET_ABI32 */ 1079 1080 #endif 1081 1082 #ifdef TARGET_UNICORE32 1083 1084 void cpu_loop(CPUUniCore32State *env) 1085 { 1086 CPUState *cs = CPU(uc32_env_get_cpu(env)); 1087 int trapnr; 1088 unsigned int n, insn; 1089 target_siginfo_t info; 1090 1091 for (;;) { 1092 cpu_exec_start(cs); 1093 trapnr = uc32_cpu_exec(env); 1094 cpu_exec_end(cs); 1095 switch (trapnr) { 1096 case UC32_EXCP_PRIV: 1097 { 1098 /* system call */ 1099 get_user_u32(insn, env->regs[31] - 4); 1100 n = insn & 0xffffff; 1101 1102 if (n >= UC32_SYSCALL_BASE) { 1103 /* linux syscall */ 1104 n -= UC32_SYSCALL_BASE; 1105 if (n == UC32_SYSCALL_NR_set_tls) { 1106 cpu_set_tls(env, env->regs[0]); 1107 env->regs[0] = 0; 1108 } else { 1109 env->regs[0] = do_syscall(env, 1110 n, 1111 env->regs[0], 1112 env->regs[1], 1113 env->regs[2], 1114 env->regs[3], 1115 env->regs[4], 1116 env->regs[5], 1117 0, 0); 1118 } 1119 } else { 1120 goto error; 1121 } 1122 } 1123 break; 1124 case UC32_EXCP_DTRAP: 1125 case UC32_EXCP_ITRAP: 1126 info.si_signo = SIGSEGV; 1127 info.si_errno = 0; 1128 /* XXX: check env->error_code */ 1129 info.si_code = TARGET_SEGV_MAPERR; 1130 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 1131 queue_signal(env, info.si_signo, &info); 1132 break; 1133 case EXCP_INTERRUPT: 1134 /* just indicate that signals should be handled asap */ 1135 break; 1136 case EXCP_DEBUG: 1137 { 1138 int sig; 1139 1140 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1141 if (sig) { 1142 info.si_signo = sig; 1143 info.si_errno = 0; 1144 info.si_code = TARGET_TRAP_BRKPT; 1145 queue_signal(env, info.si_signo, &info); 1146 } 1147 } 1148 break; 1149 default: 1150 goto error; 1151 } 1152 process_pending_signals(env); 1153 } 1154 1155 error: 1156 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1157 cpu_dump_state(cs, stderr, fprintf, 0); 1158 abort(); 1159 } 1160 #endif 1161 1162 #ifdef TARGET_SPARC 1163 #define SPARC64_STACK_BIAS 2047 1164 1165 //#define DEBUG_WIN 1166 1167 /* WARNING: dealing with register windows _is_ complicated. More info 1168 can be found at http://www.sics.se/~psm/sparcstack.html */ 1169 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 1170 { 1171 index = (index + cwp * 16) % (16 * env->nwindows); 1172 /* wrap handling : if cwp is on the last window, then we use the 1173 registers 'after' the end */ 1174 if (index < 8 && env->cwp == env->nwindows - 1) 1175 index += 16 * env->nwindows; 1176 return index; 1177 } 1178 1179 /* save the register window 'cwp1' */ 1180 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1181 { 1182 unsigned int i; 1183 abi_ulong sp_ptr; 1184 1185 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1186 #ifdef TARGET_SPARC64 1187 if (sp_ptr & 3) 1188 sp_ptr += SPARC64_STACK_BIAS; 1189 #endif 1190 #if defined(DEBUG_WIN) 1191 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1192 sp_ptr, cwp1); 1193 #endif 1194 for(i = 0; i < 16; i++) { 1195 /* FIXME - what to do if put_user() fails? */ 1196 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1197 sp_ptr += sizeof(abi_ulong); 1198 } 1199 } 1200 1201 static void save_window(CPUSPARCState *env) 1202 { 1203 #ifndef TARGET_SPARC64 1204 unsigned int new_wim; 1205 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1206 ((1LL << env->nwindows) - 1); 1207 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1208 env->wim = new_wim; 1209 #else 1210 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1211 env->cansave++; 1212 env->canrestore--; 1213 #endif 1214 } 1215 1216 static void restore_window(CPUSPARCState *env) 1217 { 1218 #ifndef TARGET_SPARC64 1219 unsigned int new_wim; 1220 #endif 1221 unsigned int i, cwp1; 1222 abi_ulong sp_ptr; 1223 1224 #ifndef TARGET_SPARC64 1225 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1226 ((1LL << env->nwindows) - 1); 1227 #endif 1228 1229 /* restore the invalid window */ 1230 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1231 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1232 #ifdef TARGET_SPARC64 1233 if (sp_ptr & 3) 1234 sp_ptr += SPARC64_STACK_BIAS; 1235 #endif 1236 #if defined(DEBUG_WIN) 1237 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1238 sp_ptr, cwp1); 1239 #endif 1240 for(i = 0; i < 16; i++) { 1241 /* FIXME - what to do if get_user() fails? */ 1242 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1243 sp_ptr += sizeof(abi_ulong); 1244 } 1245 #ifdef TARGET_SPARC64 1246 env->canrestore++; 1247 if (env->cleanwin < env->nwindows - 1) 1248 env->cleanwin++; 1249 env->cansave--; 1250 #else 1251 env->wim = new_wim; 1252 #endif 1253 } 1254 1255 static void flush_windows(CPUSPARCState *env) 1256 { 1257 int offset, cwp1; 1258 1259 offset = 1; 1260 for(;;) { 1261 /* if restore would invoke restore_window(), then we can stop */ 1262 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1263 #ifndef TARGET_SPARC64 1264 if (env->wim & (1 << cwp1)) 1265 break; 1266 #else 1267 if (env->canrestore == 0) 1268 break; 1269 env->cansave++; 1270 env->canrestore--; 1271 #endif 1272 save_window_offset(env, cwp1); 1273 offset++; 1274 } 1275 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1276 #ifndef TARGET_SPARC64 1277 /* set wim so that restore will reload the registers */ 1278 env->wim = 1 << cwp1; 1279 #endif 1280 #if defined(DEBUG_WIN) 1281 printf("flush_windows: nb=%d\n", offset - 1); 1282 #endif 1283 } 1284 1285 void cpu_loop (CPUSPARCState *env) 1286 { 1287 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1288 int trapnr; 1289 abi_long ret; 1290 target_siginfo_t info; 1291 1292 while (1) { 1293 cpu_exec_start(cs); 1294 trapnr = cpu_sparc_exec (env); 1295 cpu_exec_end(cs); 1296 1297 /* Compute PSR before exposing state. */ 1298 if (env->cc_op != CC_OP_FLAGS) { 1299 cpu_get_psr(env); 1300 } 1301 1302 switch (trapnr) { 1303 #ifndef TARGET_SPARC64 1304 case 0x88: 1305 case 0x90: 1306 #else 1307 case 0x110: 1308 case 0x16d: 1309 #endif 1310 ret = do_syscall (env, env->gregs[1], 1311 env->regwptr[0], env->regwptr[1], 1312 env->regwptr[2], env->regwptr[3], 1313 env->regwptr[4], env->regwptr[5], 1314 0, 0); 1315 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1316 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1317 env->xcc |= PSR_CARRY; 1318 #else 1319 env->psr |= PSR_CARRY; 1320 #endif 1321 ret = -ret; 1322 } else { 1323 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1324 env->xcc &= ~PSR_CARRY; 1325 #else 1326 env->psr &= ~PSR_CARRY; 1327 #endif 1328 } 1329 env->regwptr[0] = ret; 1330 /* next instruction */ 1331 env->pc = env->npc; 1332 env->npc = env->npc + 4; 1333 break; 1334 case 0x83: /* flush windows */ 1335 #ifdef TARGET_ABI32 1336 case 0x103: 1337 #endif 1338 flush_windows(env); 1339 /* next instruction */ 1340 env->pc = env->npc; 1341 env->npc = env->npc + 4; 1342 break; 1343 #ifndef TARGET_SPARC64 1344 case TT_WIN_OVF: /* window overflow */ 1345 save_window(env); 1346 break; 1347 case TT_WIN_UNF: /* window underflow */ 1348 restore_window(env); 1349 break; 1350 case TT_TFAULT: 1351 case TT_DFAULT: 1352 { 1353 info.si_signo = TARGET_SIGSEGV; 1354 info.si_errno = 0; 1355 /* XXX: check env->error_code */ 1356 info.si_code = TARGET_SEGV_MAPERR; 1357 info._sifields._sigfault._addr = env->mmuregs[4]; 1358 queue_signal(env, info.si_signo, &info); 1359 } 1360 break; 1361 #else 1362 case TT_SPILL: /* window overflow */ 1363 save_window(env); 1364 break; 1365 case TT_FILL: /* window underflow */ 1366 restore_window(env); 1367 break; 1368 case TT_TFAULT: 1369 case TT_DFAULT: 1370 { 1371 info.si_signo = TARGET_SIGSEGV; 1372 info.si_errno = 0; 1373 /* XXX: check env->error_code */ 1374 info.si_code = TARGET_SEGV_MAPERR; 1375 if (trapnr == TT_DFAULT) 1376 info._sifields._sigfault._addr = env->dmmuregs[4]; 1377 else 1378 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1379 queue_signal(env, info.si_signo, &info); 1380 } 1381 break; 1382 #ifndef TARGET_ABI32 1383 case 0x16e: 1384 flush_windows(env); 1385 sparc64_get_context(env); 1386 break; 1387 case 0x16f: 1388 flush_windows(env); 1389 sparc64_set_context(env); 1390 break; 1391 #endif 1392 #endif 1393 case EXCP_INTERRUPT: 1394 /* just indicate that signals should be handled asap */ 1395 break; 1396 case TT_ILL_INSN: 1397 { 1398 info.si_signo = TARGET_SIGILL; 1399 info.si_errno = 0; 1400 info.si_code = TARGET_ILL_ILLOPC; 1401 info._sifields._sigfault._addr = env->pc; 1402 queue_signal(env, info.si_signo, &info); 1403 } 1404 break; 1405 case EXCP_DEBUG: 1406 { 1407 int sig; 1408 1409 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1410 if (sig) 1411 { 1412 info.si_signo = sig; 1413 info.si_errno = 0; 1414 info.si_code = TARGET_TRAP_BRKPT; 1415 queue_signal(env, info.si_signo, &info); 1416 } 1417 } 1418 break; 1419 default: 1420 printf ("Unhandled trap: 0x%x\n", trapnr); 1421 cpu_dump_state(cs, stderr, fprintf, 0); 1422 exit (1); 1423 } 1424 process_pending_signals (env); 1425 } 1426 } 1427 1428 #endif 1429 1430 #ifdef TARGET_PPC 1431 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1432 { 1433 /* TO FIX */ 1434 return 0; 1435 } 1436 1437 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1438 { 1439 return cpu_ppc_get_tb(env); 1440 } 1441 1442 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1443 { 1444 return cpu_ppc_get_tb(env) >> 32; 1445 } 1446 1447 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1448 { 1449 return cpu_ppc_get_tb(env); 1450 } 1451 1452 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1453 { 1454 return cpu_ppc_get_tb(env) >> 32; 1455 } 1456 1457 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1458 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1459 1460 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1461 { 1462 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1463 } 1464 1465 /* XXX: to be fixed */ 1466 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1467 { 1468 return -1; 1469 } 1470 1471 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1472 { 1473 return -1; 1474 } 1475 1476 #define EXCP_DUMP(env, fmt, ...) \ 1477 do { \ 1478 CPUState *cs = ENV_GET_CPU(env); \ 1479 fprintf(stderr, fmt , ## __VA_ARGS__); \ 1480 cpu_dump_state(cs, stderr, fprintf, 0); \ 1481 qemu_log(fmt, ## __VA_ARGS__); \ 1482 if (qemu_log_enabled()) { \ 1483 log_cpu_state(cs, 0); \ 1484 } \ 1485 } while (0) 1486 1487 static int do_store_exclusive(CPUPPCState *env) 1488 { 1489 target_ulong addr; 1490 target_ulong page_addr; 1491 target_ulong val, val2 __attribute__((unused)) = 0; 1492 int flags; 1493 int segv = 0; 1494 1495 addr = env->reserve_ea; 1496 page_addr = addr & TARGET_PAGE_MASK; 1497 start_exclusive(); 1498 mmap_lock(); 1499 flags = page_get_flags(page_addr); 1500 if ((flags & PAGE_READ) == 0) { 1501 segv = 1; 1502 } else { 1503 int reg = env->reserve_info & 0x1f; 1504 int size = env->reserve_info >> 5; 1505 int stored = 0; 1506 1507 if (addr == env->reserve_addr) { 1508 switch (size) { 1509 case 1: segv = get_user_u8(val, addr); break; 1510 case 2: segv = get_user_u16(val, addr); break; 1511 case 4: segv = get_user_u32(val, addr); break; 1512 #if defined(TARGET_PPC64) 1513 case 8: segv = get_user_u64(val, addr); break; 1514 case 16: { 1515 segv = get_user_u64(val, addr); 1516 if (!segv) { 1517 segv = get_user_u64(val2, addr + 8); 1518 } 1519 break; 1520 } 1521 #endif 1522 default: abort(); 1523 } 1524 if (!segv && val == env->reserve_val) { 1525 val = env->gpr[reg]; 1526 switch (size) { 1527 case 1: segv = put_user_u8(val, addr); break; 1528 case 2: segv = put_user_u16(val, addr); break; 1529 case 4: segv = put_user_u32(val, addr); break; 1530 #if defined(TARGET_PPC64) 1531 case 8: segv = put_user_u64(val, addr); break; 1532 case 16: { 1533 if (val2 == env->reserve_val2) { 1534 if (msr_le) { 1535 val2 = val; 1536 val = env->gpr[reg+1]; 1537 } else { 1538 val2 = env->gpr[reg+1]; 1539 } 1540 segv = put_user_u64(val, addr); 1541 if (!segv) { 1542 segv = put_user_u64(val2, addr + 8); 1543 } 1544 } 1545 break; 1546 } 1547 #endif 1548 default: abort(); 1549 } 1550 if (!segv) { 1551 stored = 1; 1552 } 1553 } 1554 } 1555 env->crf[0] = (stored << 1) | xer_so; 1556 env->reserve_addr = (target_ulong)-1; 1557 } 1558 if (!segv) { 1559 env->nip += 4; 1560 } 1561 mmap_unlock(); 1562 end_exclusive(); 1563 return segv; 1564 } 1565 1566 void cpu_loop(CPUPPCState *env) 1567 { 1568 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1569 target_siginfo_t info; 1570 int trapnr; 1571 target_ulong ret; 1572 1573 for(;;) { 1574 cpu_exec_start(cs); 1575 trapnr = cpu_ppc_exec(env); 1576 cpu_exec_end(cs); 1577 switch(trapnr) { 1578 case POWERPC_EXCP_NONE: 1579 /* Just go on */ 1580 break; 1581 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1582 cpu_abort(cs, "Critical interrupt while in user mode. " 1583 "Aborting\n"); 1584 break; 1585 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1586 cpu_abort(cs, "Machine check exception while in user mode. " 1587 "Aborting\n"); 1588 break; 1589 case POWERPC_EXCP_DSI: /* Data storage exception */ 1590 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", 1591 env->spr[SPR_DAR]); 1592 /* XXX: check this. Seems bugged */ 1593 switch (env->error_code & 0xFF000000) { 1594 case 0x40000000: 1595 info.si_signo = TARGET_SIGSEGV; 1596 info.si_errno = 0; 1597 info.si_code = TARGET_SEGV_MAPERR; 1598 break; 1599 case 0x04000000: 1600 info.si_signo = TARGET_SIGILL; 1601 info.si_errno = 0; 1602 info.si_code = TARGET_ILL_ILLADR; 1603 break; 1604 case 0x08000000: 1605 info.si_signo = TARGET_SIGSEGV; 1606 info.si_errno = 0; 1607 info.si_code = TARGET_SEGV_ACCERR; 1608 break; 1609 default: 1610 /* Let's send a regular segfault... */ 1611 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1612 env->error_code); 1613 info.si_signo = TARGET_SIGSEGV; 1614 info.si_errno = 0; 1615 info.si_code = TARGET_SEGV_MAPERR; 1616 break; 1617 } 1618 info._sifields._sigfault._addr = env->nip; 1619 queue_signal(env, info.si_signo, &info); 1620 break; 1621 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1622 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx 1623 "\n", env->spr[SPR_SRR0]); 1624 /* XXX: check this */ 1625 switch (env->error_code & 0xFF000000) { 1626 case 0x40000000: 1627 info.si_signo = TARGET_SIGSEGV; 1628 info.si_errno = 0; 1629 info.si_code = TARGET_SEGV_MAPERR; 1630 break; 1631 case 0x10000000: 1632 case 0x08000000: 1633 info.si_signo = TARGET_SIGSEGV; 1634 info.si_errno = 0; 1635 info.si_code = TARGET_SEGV_ACCERR; 1636 break; 1637 default: 1638 /* Let's send a regular segfault... */ 1639 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1640 env->error_code); 1641 info.si_signo = TARGET_SIGSEGV; 1642 info.si_errno = 0; 1643 info.si_code = TARGET_SEGV_MAPERR; 1644 break; 1645 } 1646 info._sifields._sigfault._addr = env->nip - 4; 1647 queue_signal(env, info.si_signo, &info); 1648 break; 1649 case POWERPC_EXCP_EXTERNAL: /* External input */ 1650 cpu_abort(cs, "External interrupt while in user mode. " 1651 "Aborting\n"); 1652 break; 1653 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1654 EXCP_DUMP(env, "Unaligned memory access\n"); 1655 /* XXX: check this */ 1656 info.si_signo = TARGET_SIGBUS; 1657 info.si_errno = 0; 1658 info.si_code = TARGET_BUS_ADRALN; 1659 info._sifields._sigfault._addr = env->nip - 4; 1660 queue_signal(env, info.si_signo, &info); 1661 break; 1662 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1663 /* XXX: check this */ 1664 switch (env->error_code & ~0xF) { 1665 case POWERPC_EXCP_FP: 1666 EXCP_DUMP(env, "Floating point program exception\n"); 1667 info.si_signo = TARGET_SIGFPE; 1668 info.si_errno = 0; 1669 switch (env->error_code & 0xF) { 1670 case POWERPC_EXCP_FP_OX: 1671 info.si_code = TARGET_FPE_FLTOVF; 1672 break; 1673 case POWERPC_EXCP_FP_UX: 1674 info.si_code = TARGET_FPE_FLTUND; 1675 break; 1676 case POWERPC_EXCP_FP_ZX: 1677 case POWERPC_EXCP_FP_VXZDZ: 1678 info.si_code = TARGET_FPE_FLTDIV; 1679 break; 1680 case POWERPC_EXCP_FP_XX: 1681 info.si_code = TARGET_FPE_FLTRES; 1682 break; 1683 case POWERPC_EXCP_FP_VXSOFT: 1684 info.si_code = TARGET_FPE_FLTINV; 1685 break; 1686 case POWERPC_EXCP_FP_VXSNAN: 1687 case POWERPC_EXCP_FP_VXISI: 1688 case POWERPC_EXCP_FP_VXIDI: 1689 case POWERPC_EXCP_FP_VXIMZ: 1690 case POWERPC_EXCP_FP_VXVC: 1691 case POWERPC_EXCP_FP_VXSQRT: 1692 case POWERPC_EXCP_FP_VXCVI: 1693 info.si_code = TARGET_FPE_FLTSUB; 1694 break; 1695 default: 1696 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1697 env->error_code); 1698 break; 1699 } 1700 break; 1701 case POWERPC_EXCP_INVAL: 1702 EXCP_DUMP(env, "Invalid instruction\n"); 1703 info.si_signo = TARGET_SIGILL; 1704 info.si_errno = 0; 1705 switch (env->error_code & 0xF) { 1706 case POWERPC_EXCP_INVAL_INVAL: 1707 info.si_code = TARGET_ILL_ILLOPC; 1708 break; 1709 case POWERPC_EXCP_INVAL_LSWX: 1710 info.si_code = TARGET_ILL_ILLOPN; 1711 break; 1712 case POWERPC_EXCP_INVAL_SPR: 1713 info.si_code = TARGET_ILL_PRVREG; 1714 break; 1715 case POWERPC_EXCP_INVAL_FP: 1716 info.si_code = TARGET_ILL_COPROC; 1717 break; 1718 default: 1719 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1720 env->error_code & 0xF); 1721 info.si_code = TARGET_ILL_ILLADR; 1722 break; 1723 } 1724 break; 1725 case POWERPC_EXCP_PRIV: 1726 EXCP_DUMP(env, "Privilege violation\n"); 1727 info.si_signo = TARGET_SIGILL; 1728 info.si_errno = 0; 1729 switch (env->error_code & 0xF) { 1730 case POWERPC_EXCP_PRIV_OPC: 1731 info.si_code = TARGET_ILL_PRVOPC; 1732 break; 1733 case POWERPC_EXCP_PRIV_REG: 1734 info.si_code = TARGET_ILL_PRVREG; 1735 break; 1736 default: 1737 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1738 env->error_code & 0xF); 1739 info.si_code = TARGET_ILL_PRVOPC; 1740 break; 1741 } 1742 break; 1743 case POWERPC_EXCP_TRAP: 1744 cpu_abort(cs, "Tried to call a TRAP\n"); 1745 break; 1746 default: 1747 /* Should not happen ! */ 1748 cpu_abort(cs, "Unknown program exception (%02x)\n", 1749 env->error_code); 1750 break; 1751 } 1752 info._sifields._sigfault._addr = env->nip - 4; 1753 queue_signal(env, info.si_signo, &info); 1754 break; 1755 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1756 EXCP_DUMP(env, "No floating point allowed\n"); 1757 info.si_signo = TARGET_SIGILL; 1758 info.si_errno = 0; 1759 info.si_code = TARGET_ILL_COPROC; 1760 info._sifields._sigfault._addr = env->nip - 4; 1761 queue_signal(env, info.si_signo, &info); 1762 break; 1763 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1764 cpu_abort(cs, "Syscall exception while in user mode. " 1765 "Aborting\n"); 1766 break; 1767 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1768 EXCP_DUMP(env, "No APU instruction allowed\n"); 1769 info.si_signo = TARGET_SIGILL; 1770 info.si_errno = 0; 1771 info.si_code = TARGET_ILL_COPROC; 1772 info._sifields._sigfault._addr = env->nip - 4; 1773 queue_signal(env, info.si_signo, &info); 1774 break; 1775 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1776 cpu_abort(cs, "Decrementer interrupt while in user mode. " 1777 "Aborting\n"); 1778 break; 1779 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1780 cpu_abort(cs, "Fix interval timer interrupt while in user mode. " 1781 "Aborting\n"); 1782 break; 1783 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1784 cpu_abort(cs, "Watchdog timer interrupt while in user mode. " 1785 "Aborting\n"); 1786 break; 1787 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1788 cpu_abort(cs, "Data TLB exception while in user mode. " 1789 "Aborting\n"); 1790 break; 1791 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1792 cpu_abort(cs, "Instruction TLB exception while in user mode. " 1793 "Aborting\n"); 1794 break; 1795 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1796 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1797 info.si_signo = TARGET_SIGILL; 1798 info.si_errno = 0; 1799 info.si_code = TARGET_ILL_COPROC; 1800 info._sifields._sigfault._addr = env->nip - 4; 1801 queue_signal(env, info.si_signo, &info); 1802 break; 1803 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1804 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); 1805 break; 1806 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1807 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); 1808 break; 1809 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1810 cpu_abort(cs, "Performance monitor exception not handled\n"); 1811 break; 1812 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1813 cpu_abort(cs, "Doorbell interrupt while in user mode. " 1814 "Aborting\n"); 1815 break; 1816 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1817 cpu_abort(cs, "Doorbell critical interrupt while in user mode. " 1818 "Aborting\n"); 1819 break; 1820 case POWERPC_EXCP_RESET: /* System reset exception */ 1821 cpu_abort(cs, "Reset interrupt while in user mode. " 1822 "Aborting\n"); 1823 break; 1824 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1825 cpu_abort(cs, "Data segment exception while in user mode. " 1826 "Aborting\n"); 1827 break; 1828 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1829 cpu_abort(cs, "Instruction segment exception " 1830 "while in user mode. Aborting\n"); 1831 break; 1832 /* PowerPC 64 with hypervisor mode support */ 1833 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1834 cpu_abort(cs, "Hypervisor decrementer interrupt " 1835 "while in user mode. Aborting\n"); 1836 break; 1837 case POWERPC_EXCP_TRACE: /* Trace exception */ 1838 /* Nothing to do: 1839 * we use this exception to emulate step-by-step execution mode. 1840 */ 1841 break; 1842 /* PowerPC 64 with hypervisor mode support */ 1843 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1844 cpu_abort(cs, "Hypervisor data storage exception " 1845 "while in user mode. Aborting\n"); 1846 break; 1847 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1848 cpu_abort(cs, "Hypervisor instruction storage exception " 1849 "while in user mode. Aborting\n"); 1850 break; 1851 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1852 cpu_abort(cs, "Hypervisor data segment exception " 1853 "while in user mode. Aborting\n"); 1854 break; 1855 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1856 cpu_abort(cs, "Hypervisor instruction segment exception " 1857 "while in user mode. Aborting\n"); 1858 break; 1859 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1860 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1861 info.si_signo = TARGET_SIGILL; 1862 info.si_errno = 0; 1863 info.si_code = TARGET_ILL_COPROC; 1864 info._sifields._sigfault._addr = env->nip - 4; 1865 queue_signal(env, info.si_signo, &info); 1866 break; 1867 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1868 cpu_abort(cs, "Programmable interval timer interrupt " 1869 "while in user mode. Aborting\n"); 1870 break; 1871 case POWERPC_EXCP_IO: /* IO error exception */ 1872 cpu_abort(cs, "IO error exception while in user mode. " 1873 "Aborting\n"); 1874 break; 1875 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1876 cpu_abort(cs, "Run mode exception while in user mode. " 1877 "Aborting\n"); 1878 break; 1879 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1880 cpu_abort(cs, "Emulation trap exception not handled\n"); 1881 break; 1882 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1883 cpu_abort(cs, "Instruction fetch TLB exception " 1884 "while in user-mode. Aborting"); 1885 break; 1886 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1887 cpu_abort(cs, "Data load TLB exception while in user-mode. " 1888 "Aborting"); 1889 break; 1890 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1891 cpu_abort(cs, "Data store TLB exception while in user-mode. " 1892 "Aborting"); 1893 break; 1894 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1895 cpu_abort(cs, "Floating-point assist exception not handled\n"); 1896 break; 1897 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1898 cpu_abort(cs, "Instruction address breakpoint exception " 1899 "not handled\n"); 1900 break; 1901 case POWERPC_EXCP_SMI: /* System management interrupt */ 1902 cpu_abort(cs, "System management interrupt while in user mode. " 1903 "Aborting\n"); 1904 break; 1905 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1906 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " 1907 "Aborting\n"); 1908 break; 1909 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1910 cpu_abort(cs, "Performance monitor exception not handled\n"); 1911 break; 1912 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1913 cpu_abort(cs, "Vector assist exception not handled\n"); 1914 break; 1915 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1916 cpu_abort(cs, "Soft patch exception not handled\n"); 1917 break; 1918 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1919 cpu_abort(cs, "Maintenance exception while in user mode. " 1920 "Aborting\n"); 1921 break; 1922 case POWERPC_EXCP_STOP: /* stop translation */ 1923 /* We did invalidate the instruction cache. Go on */ 1924 break; 1925 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1926 /* We just stopped because of a branch. Go on */ 1927 break; 1928 case POWERPC_EXCP_SYSCALL_USER: 1929 /* system call in user-mode emulation */ 1930 /* WARNING: 1931 * PPC ABI uses overflow flag in cr0 to signal an error 1932 * in syscalls. 1933 */ 1934 env->crf[0] &= ~0x1; 1935 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1936 env->gpr[5], env->gpr[6], env->gpr[7], 1937 env->gpr[8], 0, 0); 1938 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1939 /* Returning from a successful sigreturn syscall. 1940 Avoid corrupting register state. */ 1941 break; 1942 } 1943 if (ret > (target_ulong)(-515)) { 1944 env->crf[0] |= 0x1; 1945 ret = -ret; 1946 } 1947 env->gpr[3] = ret; 1948 break; 1949 case POWERPC_EXCP_STCX: 1950 if (do_store_exclusive(env)) { 1951 info.si_signo = TARGET_SIGSEGV; 1952 info.si_errno = 0; 1953 info.si_code = TARGET_SEGV_MAPERR; 1954 info._sifields._sigfault._addr = env->nip; 1955 queue_signal(env, info.si_signo, &info); 1956 } 1957 break; 1958 case EXCP_DEBUG: 1959 { 1960 int sig; 1961 1962 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1963 if (sig) { 1964 info.si_signo = sig; 1965 info.si_errno = 0; 1966 info.si_code = TARGET_TRAP_BRKPT; 1967 queue_signal(env, info.si_signo, &info); 1968 } 1969 } 1970 break; 1971 case EXCP_INTERRUPT: 1972 /* just indicate that signals should be handled asap */ 1973 break; 1974 default: 1975 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr); 1976 break; 1977 } 1978 process_pending_signals(env); 1979 } 1980 } 1981 #endif 1982 1983 #ifdef TARGET_MIPS 1984 1985 # ifdef TARGET_ABI_MIPSO32 1986 # define MIPS_SYS(name, args) args, 1987 static const uint8_t mips_syscall_args[] = { 1988 MIPS_SYS(sys_syscall , 8) /* 4000 */ 1989 MIPS_SYS(sys_exit , 1) 1990 MIPS_SYS(sys_fork , 0) 1991 MIPS_SYS(sys_read , 3) 1992 MIPS_SYS(sys_write , 3) 1993 MIPS_SYS(sys_open , 3) /* 4005 */ 1994 MIPS_SYS(sys_close , 1) 1995 MIPS_SYS(sys_waitpid , 3) 1996 MIPS_SYS(sys_creat , 2) 1997 MIPS_SYS(sys_link , 2) 1998 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1999 MIPS_SYS(sys_execve , 0) 2000 MIPS_SYS(sys_chdir , 1) 2001 MIPS_SYS(sys_time , 1) 2002 MIPS_SYS(sys_mknod , 3) 2003 MIPS_SYS(sys_chmod , 2) /* 4015 */ 2004 MIPS_SYS(sys_lchown , 3) 2005 MIPS_SYS(sys_ni_syscall , 0) 2006 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 2007 MIPS_SYS(sys_lseek , 3) 2008 MIPS_SYS(sys_getpid , 0) /* 4020 */ 2009 MIPS_SYS(sys_mount , 5) 2010 MIPS_SYS(sys_umount , 1) 2011 MIPS_SYS(sys_setuid , 1) 2012 MIPS_SYS(sys_getuid , 0) 2013 MIPS_SYS(sys_stime , 1) /* 4025 */ 2014 MIPS_SYS(sys_ptrace , 4) 2015 MIPS_SYS(sys_alarm , 1) 2016 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 2017 MIPS_SYS(sys_pause , 0) 2018 MIPS_SYS(sys_utime , 2) /* 4030 */ 2019 MIPS_SYS(sys_ni_syscall , 0) 2020 MIPS_SYS(sys_ni_syscall , 0) 2021 MIPS_SYS(sys_access , 2) 2022 MIPS_SYS(sys_nice , 1) 2023 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 2024 MIPS_SYS(sys_sync , 0) 2025 MIPS_SYS(sys_kill , 2) 2026 MIPS_SYS(sys_rename , 2) 2027 MIPS_SYS(sys_mkdir , 2) 2028 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 2029 MIPS_SYS(sys_dup , 1) 2030 MIPS_SYS(sys_pipe , 0) 2031 MIPS_SYS(sys_times , 1) 2032 MIPS_SYS(sys_ni_syscall , 0) 2033 MIPS_SYS(sys_brk , 1) /* 4045 */ 2034 MIPS_SYS(sys_setgid , 1) 2035 MIPS_SYS(sys_getgid , 0) 2036 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 2037 MIPS_SYS(sys_geteuid , 0) 2038 MIPS_SYS(sys_getegid , 0) /* 4050 */ 2039 MIPS_SYS(sys_acct , 0) 2040 MIPS_SYS(sys_umount2 , 2) 2041 MIPS_SYS(sys_ni_syscall , 0) 2042 MIPS_SYS(sys_ioctl , 3) 2043 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 2044 MIPS_SYS(sys_ni_syscall , 2) 2045 MIPS_SYS(sys_setpgid , 2) 2046 MIPS_SYS(sys_ni_syscall , 0) 2047 MIPS_SYS(sys_olduname , 1) 2048 MIPS_SYS(sys_umask , 1) /* 4060 */ 2049 MIPS_SYS(sys_chroot , 1) 2050 MIPS_SYS(sys_ustat , 2) 2051 MIPS_SYS(sys_dup2 , 2) 2052 MIPS_SYS(sys_getppid , 0) 2053 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 2054 MIPS_SYS(sys_setsid , 0) 2055 MIPS_SYS(sys_sigaction , 3) 2056 MIPS_SYS(sys_sgetmask , 0) 2057 MIPS_SYS(sys_ssetmask , 1) 2058 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 2059 MIPS_SYS(sys_setregid , 2) 2060 MIPS_SYS(sys_sigsuspend , 0) 2061 MIPS_SYS(sys_sigpending , 1) 2062 MIPS_SYS(sys_sethostname , 2) 2063 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 2064 MIPS_SYS(sys_getrlimit , 2) 2065 MIPS_SYS(sys_getrusage , 2) 2066 MIPS_SYS(sys_gettimeofday, 2) 2067 MIPS_SYS(sys_settimeofday, 2) 2068 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 2069 MIPS_SYS(sys_setgroups , 2) 2070 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 2071 MIPS_SYS(sys_symlink , 2) 2072 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 2073 MIPS_SYS(sys_readlink , 3) /* 4085 */ 2074 MIPS_SYS(sys_uselib , 1) 2075 MIPS_SYS(sys_swapon , 2) 2076 MIPS_SYS(sys_reboot , 3) 2077 MIPS_SYS(old_readdir , 3) 2078 MIPS_SYS(old_mmap , 6) /* 4090 */ 2079 MIPS_SYS(sys_munmap , 2) 2080 MIPS_SYS(sys_truncate , 2) 2081 MIPS_SYS(sys_ftruncate , 2) 2082 MIPS_SYS(sys_fchmod , 2) 2083 MIPS_SYS(sys_fchown , 3) /* 4095 */ 2084 MIPS_SYS(sys_getpriority , 2) 2085 MIPS_SYS(sys_setpriority , 3) 2086 MIPS_SYS(sys_ni_syscall , 0) 2087 MIPS_SYS(sys_statfs , 2) 2088 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 2089 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 2090 MIPS_SYS(sys_socketcall , 2) 2091 MIPS_SYS(sys_syslog , 3) 2092 MIPS_SYS(sys_setitimer , 3) 2093 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 2094 MIPS_SYS(sys_newstat , 2) 2095 MIPS_SYS(sys_newlstat , 2) 2096 MIPS_SYS(sys_newfstat , 2) 2097 MIPS_SYS(sys_uname , 1) 2098 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 2099 MIPS_SYS(sys_vhangup , 0) 2100 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 2101 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 2102 MIPS_SYS(sys_wait4 , 4) 2103 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 2104 MIPS_SYS(sys_sysinfo , 1) 2105 MIPS_SYS(sys_ipc , 6) 2106 MIPS_SYS(sys_fsync , 1) 2107 MIPS_SYS(sys_sigreturn , 0) 2108 MIPS_SYS(sys_clone , 6) /* 4120 */ 2109 MIPS_SYS(sys_setdomainname, 2) 2110 MIPS_SYS(sys_newuname , 1) 2111 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 2112 MIPS_SYS(sys_adjtimex , 1) 2113 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 2114 MIPS_SYS(sys_sigprocmask , 3) 2115 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 2116 MIPS_SYS(sys_init_module , 5) 2117 MIPS_SYS(sys_delete_module, 1) 2118 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 2119 MIPS_SYS(sys_quotactl , 0) 2120 MIPS_SYS(sys_getpgid , 1) 2121 MIPS_SYS(sys_fchdir , 1) 2122 MIPS_SYS(sys_bdflush , 2) 2123 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 2124 MIPS_SYS(sys_personality , 1) 2125 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 2126 MIPS_SYS(sys_setfsuid , 1) 2127 MIPS_SYS(sys_setfsgid , 1) 2128 MIPS_SYS(sys_llseek , 5) /* 4140 */ 2129 MIPS_SYS(sys_getdents , 3) 2130 MIPS_SYS(sys_select , 5) 2131 MIPS_SYS(sys_flock , 2) 2132 MIPS_SYS(sys_msync , 3) 2133 MIPS_SYS(sys_readv , 3) /* 4145 */ 2134 MIPS_SYS(sys_writev , 3) 2135 MIPS_SYS(sys_cacheflush , 3) 2136 MIPS_SYS(sys_cachectl , 3) 2137 MIPS_SYS(sys_sysmips , 4) 2138 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 2139 MIPS_SYS(sys_getsid , 1) 2140 MIPS_SYS(sys_fdatasync , 0) 2141 MIPS_SYS(sys_sysctl , 1) 2142 MIPS_SYS(sys_mlock , 2) 2143 MIPS_SYS(sys_munlock , 2) /* 4155 */ 2144 MIPS_SYS(sys_mlockall , 1) 2145 MIPS_SYS(sys_munlockall , 0) 2146 MIPS_SYS(sys_sched_setparam, 2) 2147 MIPS_SYS(sys_sched_getparam, 2) 2148 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 2149 MIPS_SYS(sys_sched_getscheduler, 1) 2150 MIPS_SYS(sys_sched_yield , 0) 2151 MIPS_SYS(sys_sched_get_priority_max, 1) 2152 MIPS_SYS(sys_sched_get_priority_min, 1) 2153 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 2154 MIPS_SYS(sys_nanosleep, 2) 2155 MIPS_SYS(sys_mremap , 5) 2156 MIPS_SYS(sys_accept , 3) 2157 MIPS_SYS(sys_bind , 3) 2158 MIPS_SYS(sys_connect , 3) /* 4170 */ 2159 MIPS_SYS(sys_getpeername , 3) 2160 MIPS_SYS(sys_getsockname , 3) 2161 MIPS_SYS(sys_getsockopt , 5) 2162 MIPS_SYS(sys_listen , 2) 2163 MIPS_SYS(sys_recv , 4) /* 4175 */ 2164 MIPS_SYS(sys_recvfrom , 6) 2165 MIPS_SYS(sys_recvmsg , 3) 2166 MIPS_SYS(sys_send , 4) 2167 MIPS_SYS(sys_sendmsg , 3) 2168 MIPS_SYS(sys_sendto , 6) /* 4180 */ 2169 MIPS_SYS(sys_setsockopt , 5) 2170 MIPS_SYS(sys_shutdown , 2) 2171 MIPS_SYS(sys_socket , 3) 2172 MIPS_SYS(sys_socketpair , 4) 2173 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 2174 MIPS_SYS(sys_getresuid , 3) 2175 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 2176 MIPS_SYS(sys_poll , 3) 2177 MIPS_SYS(sys_nfsservctl , 3) 2178 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 2179 MIPS_SYS(sys_getresgid , 3) 2180 MIPS_SYS(sys_prctl , 5) 2181 MIPS_SYS(sys_rt_sigreturn, 0) 2182 MIPS_SYS(sys_rt_sigaction, 4) 2183 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 2184 MIPS_SYS(sys_rt_sigpending, 2) 2185 MIPS_SYS(sys_rt_sigtimedwait, 4) 2186 MIPS_SYS(sys_rt_sigqueueinfo, 3) 2187 MIPS_SYS(sys_rt_sigsuspend, 0) 2188 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 2189 MIPS_SYS(sys_pwrite64 , 6) 2190 MIPS_SYS(sys_chown , 3) 2191 MIPS_SYS(sys_getcwd , 2) 2192 MIPS_SYS(sys_capget , 2) 2193 MIPS_SYS(sys_capset , 2) /* 4205 */ 2194 MIPS_SYS(sys_sigaltstack , 2) 2195 MIPS_SYS(sys_sendfile , 4) 2196 MIPS_SYS(sys_ni_syscall , 0) 2197 MIPS_SYS(sys_ni_syscall , 0) 2198 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2199 MIPS_SYS(sys_truncate64 , 4) 2200 MIPS_SYS(sys_ftruncate64 , 4) 2201 MIPS_SYS(sys_stat64 , 2) 2202 MIPS_SYS(sys_lstat64 , 2) 2203 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2204 MIPS_SYS(sys_pivot_root , 2) 2205 MIPS_SYS(sys_mincore , 3) 2206 MIPS_SYS(sys_madvise , 3) 2207 MIPS_SYS(sys_getdents64 , 3) 2208 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2209 MIPS_SYS(sys_ni_syscall , 0) 2210 MIPS_SYS(sys_gettid , 0) 2211 MIPS_SYS(sys_readahead , 5) 2212 MIPS_SYS(sys_setxattr , 5) 2213 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2214 MIPS_SYS(sys_fsetxattr , 5) 2215 MIPS_SYS(sys_getxattr , 4) 2216 MIPS_SYS(sys_lgetxattr , 4) 2217 MIPS_SYS(sys_fgetxattr , 4) 2218 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2219 MIPS_SYS(sys_llistxattr , 3) 2220 MIPS_SYS(sys_flistxattr , 3) 2221 MIPS_SYS(sys_removexattr , 2) 2222 MIPS_SYS(sys_lremovexattr, 2) 2223 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2224 MIPS_SYS(sys_tkill , 2) 2225 MIPS_SYS(sys_sendfile64 , 5) 2226 MIPS_SYS(sys_futex , 6) 2227 MIPS_SYS(sys_sched_setaffinity, 3) 2228 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2229 MIPS_SYS(sys_io_setup , 2) 2230 MIPS_SYS(sys_io_destroy , 1) 2231 MIPS_SYS(sys_io_getevents, 5) 2232 MIPS_SYS(sys_io_submit , 3) 2233 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2234 MIPS_SYS(sys_exit_group , 1) 2235 MIPS_SYS(sys_lookup_dcookie, 3) 2236 MIPS_SYS(sys_epoll_create, 1) 2237 MIPS_SYS(sys_epoll_ctl , 4) 2238 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2239 MIPS_SYS(sys_remap_file_pages, 5) 2240 MIPS_SYS(sys_set_tid_address, 1) 2241 MIPS_SYS(sys_restart_syscall, 0) 2242 MIPS_SYS(sys_fadvise64_64, 7) 2243 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2244 MIPS_SYS(sys_fstatfs64 , 2) 2245 MIPS_SYS(sys_timer_create, 3) 2246 MIPS_SYS(sys_timer_settime, 4) 2247 MIPS_SYS(sys_timer_gettime, 2) 2248 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2249 MIPS_SYS(sys_timer_delete, 1) 2250 MIPS_SYS(sys_clock_settime, 2) 2251 MIPS_SYS(sys_clock_gettime, 2) 2252 MIPS_SYS(sys_clock_getres, 2) 2253 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2254 MIPS_SYS(sys_tgkill , 3) 2255 MIPS_SYS(sys_utimes , 2) 2256 MIPS_SYS(sys_mbind , 4) 2257 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2258 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2259 MIPS_SYS(sys_mq_open , 4) 2260 MIPS_SYS(sys_mq_unlink , 1) 2261 MIPS_SYS(sys_mq_timedsend, 5) 2262 MIPS_SYS(sys_mq_timedreceive, 5) 2263 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2264 MIPS_SYS(sys_mq_getsetattr, 3) 2265 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2266 MIPS_SYS(sys_waitid , 4) 2267 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2268 MIPS_SYS(sys_add_key , 5) 2269 MIPS_SYS(sys_request_key, 4) 2270 MIPS_SYS(sys_keyctl , 5) 2271 MIPS_SYS(sys_set_thread_area, 1) 2272 MIPS_SYS(sys_inotify_init, 0) 2273 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2274 MIPS_SYS(sys_inotify_rm_watch, 2) 2275 MIPS_SYS(sys_migrate_pages, 4) 2276 MIPS_SYS(sys_openat, 4) 2277 MIPS_SYS(sys_mkdirat, 3) 2278 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2279 MIPS_SYS(sys_fchownat, 5) 2280 MIPS_SYS(sys_futimesat, 3) 2281 MIPS_SYS(sys_fstatat64, 4) 2282 MIPS_SYS(sys_unlinkat, 3) 2283 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2284 MIPS_SYS(sys_linkat, 5) 2285 MIPS_SYS(sys_symlinkat, 3) 2286 MIPS_SYS(sys_readlinkat, 4) 2287 MIPS_SYS(sys_fchmodat, 3) 2288 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2289 MIPS_SYS(sys_pselect6, 6) 2290 MIPS_SYS(sys_ppoll, 5) 2291 MIPS_SYS(sys_unshare, 1) 2292 MIPS_SYS(sys_splice, 6) 2293 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2294 MIPS_SYS(sys_tee, 4) 2295 MIPS_SYS(sys_vmsplice, 4) 2296 MIPS_SYS(sys_move_pages, 6) 2297 MIPS_SYS(sys_set_robust_list, 2) 2298 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2299 MIPS_SYS(sys_kexec_load, 4) 2300 MIPS_SYS(sys_getcpu, 3) 2301 MIPS_SYS(sys_epoll_pwait, 6) 2302 MIPS_SYS(sys_ioprio_set, 3) 2303 MIPS_SYS(sys_ioprio_get, 2) 2304 MIPS_SYS(sys_utimensat, 4) 2305 MIPS_SYS(sys_signalfd, 3) 2306 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2307 MIPS_SYS(sys_eventfd, 1) 2308 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2309 MIPS_SYS(sys_timerfd_create, 2) 2310 MIPS_SYS(sys_timerfd_gettime, 2) 2311 MIPS_SYS(sys_timerfd_settime, 4) 2312 MIPS_SYS(sys_signalfd4, 4) 2313 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2314 MIPS_SYS(sys_epoll_create1, 1) 2315 MIPS_SYS(sys_dup3, 3) 2316 MIPS_SYS(sys_pipe2, 2) 2317 MIPS_SYS(sys_inotify_init1, 1) 2318 MIPS_SYS(sys_preadv, 6) /* 4330 */ 2319 MIPS_SYS(sys_pwritev, 6) 2320 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2321 MIPS_SYS(sys_perf_event_open, 5) 2322 MIPS_SYS(sys_accept4, 4) 2323 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2324 MIPS_SYS(sys_fanotify_init, 2) 2325 MIPS_SYS(sys_fanotify_mark, 6) 2326 MIPS_SYS(sys_prlimit64, 4) 2327 MIPS_SYS(sys_name_to_handle_at, 5) 2328 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2329 MIPS_SYS(sys_clock_adjtime, 2) 2330 MIPS_SYS(sys_syncfs, 1) 2331 }; 2332 # undef MIPS_SYS 2333 # endif /* O32 */ 2334 2335 static int do_store_exclusive(CPUMIPSState *env) 2336 { 2337 target_ulong addr; 2338 target_ulong page_addr; 2339 target_ulong val; 2340 int flags; 2341 int segv = 0; 2342 int reg; 2343 int d; 2344 2345 addr = env->lladdr; 2346 page_addr = addr & TARGET_PAGE_MASK; 2347 start_exclusive(); 2348 mmap_lock(); 2349 flags = page_get_flags(page_addr); 2350 if ((flags & PAGE_READ) == 0) { 2351 segv = 1; 2352 } else { 2353 reg = env->llreg & 0x1f; 2354 d = (env->llreg & 0x20) != 0; 2355 if (d) { 2356 segv = get_user_s64(val, addr); 2357 } else { 2358 segv = get_user_s32(val, addr); 2359 } 2360 if (!segv) { 2361 if (val != env->llval) { 2362 env->active_tc.gpr[reg] = 0; 2363 } else { 2364 if (d) { 2365 segv = put_user_u64(env->llnewval, addr); 2366 } else { 2367 segv = put_user_u32(env->llnewval, addr); 2368 } 2369 if (!segv) { 2370 env->active_tc.gpr[reg] = 1; 2371 } 2372 } 2373 } 2374 } 2375 env->lladdr = -1; 2376 if (!segv) { 2377 env->active_tc.PC += 4; 2378 } 2379 mmap_unlock(); 2380 end_exclusive(); 2381 return segv; 2382 } 2383 2384 /* Break codes */ 2385 enum { 2386 BRK_OVERFLOW = 6, 2387 BRK_DIVZERO = 7 2388 }; 2389 2390 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2391 unsigned int code) 2392 { 2393 int ret = -1; 2394 2395 switch (code) { 2396 case BRK_OVERFLOW: 2397 case BRK_DIVZERO: 2398 info->si_signo = TARGET_SIGFPE; 2399 info->si_errno = 0; 2400 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2401 queue_signal(env, info->si_signo, &*info); 2402 ret = 0; 2403 break; 2404 default: 2405 info->si_signo = TARGET_SIGTRAP; 2406 info->si_errno = 0; 2407 queue_signal(env, info->si_signo, &*info); 2408 ret = 0; 2409 break; 2410 } 2411 2412 return ret; 2413 } 2414 2415 void cpu_loop(CPUMIPSState *env) 2416 { 2417 CPUState *cs = CPU(mips_env_get_cpu(env)); 2418 target_siginfo_t info; 2419 int trapnr; 2420 abi_long ret; 2421 # ifdef TARGET_ABI_MIPSO32 2422 unsigned int syscall_num; 2423 # endif 2424 2425 for(;;) { 2426 cpu_exec_start(cs); 2427 trapnr = cpu_mips_exec(env); 2428 cpu_exec_end(cs); 2429 switch(trapnr) { 2430 case EXCP_SYSCALL: 2431 env->active_tc.PC += 4; 2432 # ifdef TARGET_ABI_MIPSO32 2433 syscall_num = env->active_tc.gpr[2] - 4000; 2434 if (syscall_num >= sizeof(mips_syscall_args)) { 2435 ret = -TARGET_ENOSYS; 2436 } else { 2437 int nb_args; 2438 abi_ulong sp_reg; 2439 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2440 2441 nb_args = mips_syscall_args[syscall_num]; 2442 sp_reg = env->active_tc.gpr[29]; 2443 switch (nb_args) { 2444 /* these arguments are taken from the stack */ 2445 case 8: 2446 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2447 goto done_syscall; 2448 } 2449 case 7: 2450 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2451 goto done_syscall; 2452 } 2453 case 6: 2454 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2455 goto done_syscall; 2456 } 2457 case 5: 2458 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2459 goto done_syscall; 2460 } 2461 default: 2462 break; 2463 } 2464 ret = do_syscall(env, env->active_tc.gpr[2], 2465 env->active_tc.gpr[4], 2466 env->active_tc.gpr[5], 2467 env->active_tc.gpr[6], 2468 env->active_tc.gpr[7], 2469 arg5, arg6, arg7, arg8); 2470 } 2471 done_syscall: 2472 # else 2473 ret = do_syscall(env, env->active_tc.gpr[2], 2474 env->active_tc.gpr[4], env->active_tc.gpr[5], 2475 env->active_tc.gpr[6], env->active_tc.gpr[7], 2476 env->active_tc.gpr[8], env->active_tc.gpr[9], 2477 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2478 # endif /* O32 */ 2479 if (ret == -TARGET_QEMU_ESIGRETURN) { 2480 /* Returning from a successful sigreturn syscall. 2481 Avoid clobbering register state. */ 2482 break; 2483 } 2484 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2485 env->active_tc.gpr[7] = 1; /* error flag */ 2486 ret = -ret; 2487 } else { 2488 env->active_tc.gpr[7] = 0; /* error flag */ 2489 } 2490 env->active_tc.gpr[2] = ret; 2491 break; 2492 case EXCP_TLBL: 2493 case EXCP_TLBS: 2494 case EXCP_AdEL: 2495 case EXCP_AdES: 2496 info.si_signo = TARGET_SIGSEGV; 2497 info.si_errno = 0; 2498 /* XXX: check env->error_code */ 2499 info.si_code = TARGET_SEGV_MAPERR; 2500 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2501 queue_signal(env, info.si_signo, &info); 2502 break; 2503 case EXCP_CpU: 2504 case EXCP_RI: 2505 info.si_signo = TARGET_SIGILL; 2506 info.si_errno = 0; 2507 info.si_code = 0; 2508 queue_signal(env, info.si_signo, &info); 2509 break; 2510 case EXCP_INTERRUPT: 2511 /* just indicate that signals should be handled asap */ 2512 break; 2513 case EXCP_DEBUG: 2514 { 2515 int sig; 2516 2517 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2518 if (sig) 2519 { 2520 info.si_signo = sig; 2521 info.si_errno = 0; 2522 info.si_code = TARGET_TRAP_BRKPT; 2523 queue_signal(env, info.si_signo, &info); 2524 } 2525 } 2526 break; 2527 case EXCP_SC: 2528 if (do_store_exclusive(env)) { 2529 info.si_signo = TARGET_SIGSEGV; 2530 info.si_errno = 0; 2531 info.si_code = TARGET_SEGV_MAPERR; 2532 info._sifields._sigfault._addr = env->active_tc.PC; 2533 queue_signal(env, info.si_signo, &info); 2534 } 2535 break; 2536 case EXCP_DSPDIS: 2537 info.si_signo = TARGET_SIGILL; 2538 info.si_errno = 0; 2539 info.si_code = TARGET_ILL_ILLOPC; 2540 queue_signal(env, info.si_signo, &info); 2541 break; 2542 /* The code below was inspired by the MIPS Linux kernel trap 2543 * handling code in arch/mips/kernel/traps.c. 2544 */ 2545 case EXCP_BREAK: 2546 { 2547 abi_ulong trap_instr; 2548 unsigned int code; 2549 2550 if (env->hflags & MIPS_HFLAG_M16) { 2551 if (env->insn_flags & ASE_MICROMIPS) { 2552 /* microMIPS mode */ 2553 ret = get_user_u16(trap_instr, env->active_tc.PC); 2554 if (ret != 0) { 2555 goto error; 2556 } 2557 2558 if ((trap_instr >> 10) == 0x11) { 2559 /* 16-bit instruction */ 2560 code = trap_instr & 0xf; 2561 } else { 2562 /* 32-bit instruction */ 2563 abi_ulong instr_lo; 2564 2565 ret = get_user_u16(instr_lo, 2566 env->active_tc.PC + 2); 2567 if (ret != 0) { 2568 goto error; 2569 } 2570 trap_instr = (trap_instr << 16) | instr_lo; 2571 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2572 /* Unfortunately, microMIPS also suffers from 2573 the old assembler bug... */ 2574 if (code >= (1 << 10)) { 2575 code >>= 10; 2576 } 2577 } 2578 } else { 2579 /* MIPS16e mode */ 2580 ret = get_user_u16(trap_instr, env->active_tc.PC); 2581 if (ret != 0) { 2582 goto error; 2583 } 2584 code = (trap_instr >> 6) & 0x3f; 2585 } 2586 } else { 2587 ret = get_user_ual(trap_instr, env->active_tc.PC); 2588 if (ret != 0) { 2589 goto error; 2590 } 2591 2592 /* As described in the original Linux kernel code, the 2593 * below checks on 'code' are to work around an old 2594 * assembly bug. 2595 */ 2596 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2597 if (code >= (1 << 10)) { 2598 code >>= 10; 2599 } 2600 } 2601 2602 if (do_break(env, &info, code) != 0) { 2603 goto error; 2604 } 2605 } 2606 break; 2607 case EXCP_TRAP: 2608 { 2609 abi_ulong trap_instr; 2610 unsigned int code = 0; 2611 2612 if (env->hflags & MIPS_HFLAG_M16) { 2613 /* microMIPS mode */ 2614 abi_ulong instr[2]; 2615 2616 ret = get_user_u16(instr[0], env->active_tc.PC) || 2617 get_user_u16(instr[1], env->active_tc.PC + 2); 2618 2619 trap_instr = (instr[0] << 16) | instr[1]; 2620 } else { 2621 ret = get_user_ual(trap_instr, env->active_tc.PC); 2622 } 2623 2624 if (ret != 0) { 2625 goto error; 2626 } 2627 2628 /* The immediate versions don't provide a code. */ 2629 if (!(trap_instr & 0xFC000000)) { 2630 if (env->hflags & MIPS_HFLAG_M16) { 2631 /* microMIPS mode */ 2632 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 2633 } else { 2634 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2635 } 2636 } 2637 2638 if (do_break(env, &info, code) != 0) { 2639 goto error; 2640 } 2641 } 2642 break; 2643 default: 2644 error: 2645 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2646 trapnr); 2647 cpu_dump_state(cs, stderr, fprintf, 0); 2648 abort(); 2649 } 2650 process_pending_signals(env); 2651 } 2652 } 2653 #endif 2654 2655 #ifdef TARGET_OPENRISC 2656 2657 void cpu_loop(CPUOpenRISCState *env) 2658 { 2659 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2660 int trapnr, gdbsig; 2661 2662 for (;;) { 2663 cpu_exec_start(cs); 2664 trapnr = cpu_exec(env); 2665 cpu_exec_end(cs); 2666 gdbsig = 0; 2667 2668 switch (trapnr) { 2669 case EXCP_RESET: 2670 qemu_log("\nReset request, exit, pc is %#x\n", env->pc); 2671 exit(1); 2672 break; 2673 case EXCP_BUSERR: 2674 qemu_log("\nBus error, exit, pc is %#x\n", env->pc); 2675 gdbsig = SIGBUS; 2676 break; 2677 case EXCP_DPF: 2678 case EXCP_IPF: 2679 cpu_dump_state(cs, stderr, fprintf, 0); 2680 gdbsig = TARGET_SIGSEGV; 2681 break; 2682 case EXCP_TICK: 2683 qemu_log("\nTick time interrupt pc is %#x\n", env->pc); 2684 break; 2685 case EXCP_ALIGN: 2686 qemu_log("\nAlignment pc is %#x\n", env->pc); 2687 gdbsig = SIGBUS; 2688 break; 2689 case EXCP_ILLEGAL: 2690 qemu_log("\nIllegal instructionpc is %#x\n", env->pc); 2691 gdbsig = SIGILL; 2692 break; 2693 case EXCP_INT: 2694 qemu_log("\nExternal interruptpc is %#x\n", env->pc); 2695 break; 2696 case EXCP_DTLBMISS: 2697 case EXCP_ITLBMISS: 2698 qemu_log("\nTLB miss\n"); 2699 break; 2700 case EXCP_RANGE: 2701 qemu_log("\nRange\n"); 2702 gdbsig = SIGSEGV; 2703 break; 2704 case EXCP_SYSCALL: 2705 env->pc += 4; /* 0xc00; */ 2706 env->gpr[11] = do_syscall(env, 2707 env->gpr[11], /* return value */ 2708 env->gpr[3], /* r3 - r7 are params */ 2709 env->gpr[4], 2710 env->gpr[5], 2711 env->gpr[6], 2712 env->gpr[7], 2713 env->gpr[8], 0, 0); 2714 break; 2715 case EXCP_FPE: 2716 qemu_log("\nFloating point error\n"); 2717 break; 2718 case EXCP_TRAP: 2719 qemu_log("\nTrap\n"); 2720 gdbsig = SIGTRAP; 2721 break; 2722 case EXCP_NR: 2723 qemu_log("\nNR\n"); 2724 break; 2725 default: 2726 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n", 2727 trapnr); 2728 cpu_dump_state(cs, stderr, fprintf, 0); 2729 gdbsig = TARGET_SIGILL; 2730 break; 2731 } 2732 if (gdbsig) { 2733 gdb_handlesig(cs, gdbsig); 2734 if (gdbsig != TARGET_SIGTRAP) { 2735 exit(1); 2736 } 2737 } 2738 2739 process_pending_signals(env); 2740 } 2741 } 2742 2743 #endif /* TARGET_OPENRISC */ 2744 2745 #ifdef TARGET_SH4 2746 void cpu_loop(CPUSH4State *env) 2747 { 2748 CPUState *cs = CPU(sh_env_get_cpu(env)); 2749 int trapnr, ret; 2750 target_siginfo_t info; 2751 2752 while (1) { 2753 cpu_exec_start(cs); 2754 trapnr = cpu_sh4_exec (env); 2755 cpu_exec_end(cs); 2756 2757 switch (trapnr) { 2758 case 0x160: 2759 env->pc += 2; 2760 ret = do_syscall(env, 2761 env->gregs[3], 2762 env->gregs[4], 2763 env->gregs[5], 2764 env->gregs[6], 2765 env->gregs[7], 2766 env->gregs[0], 2767 env->gregs[1], 2768 0, 0); 2769 env->gregs[0] = ret; 2770 break; 2771 case EXCP_INTERRUPT: 2772 /* just indicate that signals should be handled asap */ 2773 break; 2774 case EXCP_DEBUG: 2775 { 2776 int sig; 2777 2778 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2779 if (sig) 2780 { 2781 info.si_signo = sig; 2782 info.si_errno = 0; 2783 info.si_code = TARGET_TRAP_BRKPT; 2784 queue_signal(env, info.si_signo, &info); 2785 } 2786 } 2787 break; 2788 case 0xa0: 2789 case 0xc0: 2790 info.si_signo = SIGSEGV; 2791 info.si_errno = 0; 2792 info.si_code = TARGET_SEGV_MAPERR; 2793 info._sifields._sigfault._addr = env->tea; 2794 queue_signal(env, info.si_signo, &info); 2795 break; 2796 2797 default: 2798 printf ("Unhandled trap: 0x%x\n", trapnr); 2799 cpu_dump_state(cs, stderr, fprintf, 0); 2800 exit (1); 2801 } 2802 process_pending_signals (env); 2803 } 2804 } 2805 #endif 2806 2807 #ifdef TARGET_CRIS 2808 void cpu_loop(CPUCRISState *env) 2809 { 2810 CPUState *cs = CPU(cris_env_get_cpu(env)); 2811 int trapnr, ret; 2812 target_siginfo_t info; 2813 2814 while (1) { 2815 cpu_exec_start(cs); 2816 trapnr = cpu_cris_exec (env); 2817 cpu_exec_end(cs); 2818 switch (trapnr) { 2819 case 0xaa: 2820 { 2821 info.si_signo = SIGSEGV; 2822 info.si_errno = 0; 2823 /* XXX: check env->error_code */ 2824 info.si_code = TARGET_SEGV_MAPERR; 2825 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2826 queue_signal(env, info.si_signo, &info); 2827 } 2828 break; 2829 case EXCP_INTERRUPT: 2830 /* just indicate that signals should be handled asap */ 2831 break; 2832 case EXCP_BREAK: 2833 ret = do_syscall(env, 2834 env->regs[9], 2835 env->regs[10], 2836 env->regs[11], 2837 env->regs[12], 2838 env->regs[13], 2839 env->pregs[7], 2840 env->pregs[11], 2841 0, 0); 2842 env->regs[10] = ret; 2843 break; 2844 case EXCP_DEBUG: 2845 { 2846 int sig; 2847 2848 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2849 if (sig) 2850 { 2851 info.si_signo = sig; 2852 info.si_errno = 0; 2853 info.si_code = TARGET_TRAP_BRKPT; 2854 queue_signal(env, info.si_signo, &info); 2855 } 2856 } 2857 break; 2858 default: 2859 printf ("Unhandled trap: 0x%x\n", trapnr); 2860 cpu_dump_state(cs, stderr, fprintf, 0); 2861 exit (1); 2862 } 2863 process_pending_signals (env); 2864 } 2865 } 2866 #endif 2867 2868 #ifdef TARGET_MICROBLAZE 2869 void cpu_loop(CPUMBState *env) 2870 { 2871 CPUState *cs = CPU(mb_env_get_cpu(env)); 2872 int trapnr, ret; 2873 target_siginfo_t info; 2874 2875 while (1) { 2876 cpu_exec_start(cs); 2877 trapnr = cpu_mb_exec (env); 2878 cpu_exec_end(cs); 2879 switch (trapnr) { 2880 case 0xaa: 2881 { 2882 info.si_signo = SIGSEGV; 2883 info.si_errno = 0; 2884 /* XXX: check env->error_code */ 2885 info.si_code = TARGET_SEGV_MAPERR; 2886 info._sifields._sigfault._addr = 0; 2887 queue_signal(env, info.si_signo, &info); 2888 } 2889 break; 2890 case EXCP_INTERRUPT: 2891 /* just indicate that signals should be handled asap */ 2892 break; 2893 case EXCP_BREAK: 2894 /* Return address is 4 bytes after the call. */ 2895 env->regs[14] += 4; 2896 env->sregs[SR_PC] = env->regs[14]; 2897 ret = do_syscall(env, 2898 env->regs[12], 2899 env->regs[5], 2900 env->regs[6], 2901 env->regs[7], 2902 env->regs[8], 2903 env->regs[9], 2904 env->regs[10], 2905 0, 0); 2906 env->regs[3] = ret; 2907 break; 2908 case EXCP_HW_EXCP: 2909 env->regs[17] = env->sregs[SR_PC] + 4; 2910 if (env->iflags & D_FLAG) { 2911 env->sregs[SR_ESR] |= 1 << 12; 2912 env->sregs[SR_PC] -= 4; 2913 /* FIXME: if branch was immed, replay the imm as well. */ 2914 } 2915 2916 env->iflags &= ~(IMM_FLAG | D_FLAG); 2917 2918 switch (env->sregs[SR_ESR] & 31) { 2919 case ESR_EC_DIVZERO: 2920 info.si_signo = SIGFPE; 2921 info.si_errno = 0; 2922 info.si_code = TARGET_FPE_FLTDIV; 2923 info._sifields._sigfault._addr = 0; 2924 queue_signal(env, info.si_signo, &info); 2925 break; 2926 case ESR_EC_FPU: 2927 info.si_signo = SIGFPE; 2928 info.si_errno = 0; 2929 if (env->sregs[SR_FSR] & FSR_IO) { 2930 info.si_code = TARGET_FPE_FLTINV; 2931 } 2932 if (env->sregs[SR_FSR] & FSR_DZ) { 2933 info.si_code = TARGET_FPE_FLTDIV; 2934 } 2935 info._sifields._sigfault._addr = 0; 2936 queue_signal(env, info.si_signo, &info); 2937 break; 2938 default: 2939 printf ("Unhandled hw-exception: 0x%x\n", 2940 env->sregs[SR_ESR] & ESR_EC_MASK); 2941 cpu_dump_state(cs, stderr, fprintf, 0); 2942 exit (1); 2943 break; 2944 } 2945 break; 2946 case EXCP_DEBUG: 2947 { 2948 int sig; 2949 2950 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2951 if (sig) 2952 { 2953 info.si_signo = sig; 2954 info.si_errno = 0; 2955 info.si_code = TARGET_TRAP_BRKPT; 2956 queue_signal(env, info.si_signo, &info); 2957 } 2958 } 2959 break; 2960 default: 2961 printf ("Unhandled trap: 0x%x\n", trapnr); 2962 cpu_dump_state(cs, stderr, fprintf, 0); 2963 exit (1); 2964 } 2965 process_pending_signals (env); 2966 } 2967 } 2968 #endif 2969 2970 #ifdef TARGET_M68K 2971 2972 void cpu_loop(CPUM68KState *env) 2973 { 2974 CPUState *cs = CPU(m68k_env_get_cpu(env)); 2975 int trapnr; 2976 unsigned int n; 2977 target_siginfo_t info; 2978 TaskState *ts = cs->opaque; 2979 2980 for(;;) { 2981 cpu_exec_start(cs); 2982 trapnr = cpu_m68k_exec(env); 2983 cpu_exec_end(cs); 2984 switch(trapnr) { 2985 case EXCP_ILLEGAL: 2986 { 2987 if (ts->sim_syscalls) { 2988 uint16_t nr; 2989 get_user_u16(nr, env->pc + 2); 2990 env->pc += 4; 2991 do_m68k_simcall(env, nr); 2992 } else { 2993 goto do_sigill; 2994 } 2995 } 2996 break; 2997 case EXCP_HALT_INSN: 2998 /* Semihosing syscall. */ 2999 env->pc += 4; 3000 do_m68k_semihosting(env, env->dregs[0]); 3001 break; 3002 case EXCP_LINEA: 3003 case EXCP_LINEF: 3004 case EXCP_UNSUPPORTED: 3005 do_sigill: 3006 info.si_signo = SIGILL; 3007 info.si_errno = 0; 3008 info.si_code = TARGET_ILL_ILLOPN; 3009 info._sifields._sigfault._addr = env->pc; 3010 queue_signal(env, info.si_signo, &info); 3011 break; 3012 case EXCP_TRAP0: 3013 { 3014 ts->sim_syscalls = 0; 3015 n = env->dregs[0]; 3016 env->pc += 2; 3017 env->dregs[0] = do_syscall(env, 3018 n, 3019 env->dregs[1], 3020 env->dregs[2], 3021 env->dregs[3], 3022 env->dregs[4], 3023 env->dregs[5], 3024 env->aregs[0], 3025 0, 0); 3026 } 3027 break; 3028 case EXCP_INTERRUPT: 3029 /* just indicate that signals should be handled asap */ 3030 break; 3031 case EXCP_ACCESS: 3032 { 3033 info.si_signo = SIGSEGV; 3034 info.si_errno = 0; 3035 /* XXX: check env->error_code */ 3036 info.si_code = TARGET_SEGV_MAPERR; 3037 info._sifields._sigfault._addr = env->mmu.ar; 3038 queue_signal(env, info.si_signo, &info); 3039 } 3040 break; 3041 case EXCP_DEBUG: 3042 { 3043 int sig; 3044 3045 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3046 if (sig) 3047 { 3048 info.si_signo = sig; 3049 info.si_errno = 0; 3050 info.si_code = TARGET_TRAP_BRKPT; 3051 queue_signal(env, info.si_signo, &info); 3052 } 3053 } 3054 break; 3055 default: 3056 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 3057 trapnr); 3058 cpu_dump_state(cs, stderr, fprintf, 0); 3059 abort(); 3060 } 3061 process_pending_signals(env); 3062 } 3063 } 3064 #endif /* TARGET_M68K */ 3065 3066 #ifdef TARGET_ALPHA 3067 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 3068 { 3069 target_ulong addr, val, tmp; 3070 target_siginfo_t info; 3071 int ret = 0; 3072 3073 addr = env->lock_addr; 3074 tmp = env->lock_st_addr; 3075 env->lock_addr = -1; 3076 env->lock_st_addr = 0; 3077 3078 start_exclusive(); 3079 mmap_lock(); 3080 3081 if (addr == tmp) { 3082 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3083 goto do_sigsegv; 3084 } 3085 3086 if (val == env->lock_value) { 3087 tmp = env->ir[reg]; 3088 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 3089 goto do_sigsegv; 3090 } 3091 ret = 1; 3092 } 3093 } 3094 env->ir[reg] = ret; 3095 env->pc += 4; 3096 3097 mmap_unlock(); 3098 end_exclusive(); 3099 return; 3100 3101 do_sigsegv: 3102 mmap_unlock(); 3103 end_exclusive(); 3104 3105 info.si_signo = TARGET_SIGSEGV; 3106 info.si_errno = 0; 3107 info.si_code = TARGET_SEGV_MAPERR; 3108 info._sifields._sigfault._addr = addr; 3109 queue_signal(env, TARGET_SIGSEGV, &info); 3110 } 3111 3112 void cpu_loop(CPUAlphaState *env) 3113 { 3114 CPUState *cs = CPU(alpha_env_get_cpu(env)); 3115 int trapnr; 3116 target_siginfo_t info; 3117 abi_long sysret; 3118 3119 while (1) { 3120 cpu_exec_start(cs); 3121 trapnr = cpu_alpha_exec (env); 3122 cpu_exec_end(cs); 3123 3124 /* All of the traps imply a transition through PALcode, which 3125 implies an REI instruction has been executed. Which means 3126 that the intr_flag should be cleared. */ 3127 env->intr_flag = 0; 3128 3129 switch (trapnr) { 3130 case EXCP_RESET: 3131 fprintf(stderr, "Reset requested. Exit\n"); 3132 exit(1); 3133 break; 3134 case EXCP_MCHK: 3135 fprintf(stderr, "Machine check exception. Exit\n"); 3136 exit(1); 3137 break; 3138 case EXCP_SMP_INTERRUPT: 3139 case EXCP_CLK_INTERRUPT: 3140 case EXCP_DEV_INTERRUPT: 3141 fprintf(stderr, "External interrupt. Exit\n"); 3142 exit(1); 3143 break; 3144 case EXCP_MMFAULT: 3145 env->lock_addr = -1; 3146 info.si_signo = TARGET_SIGSEGV; 3147 info.si_errno = 0; 3148 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 3149 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 3150 info._sifields._sigfault._addr = env->trap_arg0; 3151 queue_signal(env, info.si_signo, &info); 3152 break; 3153 case EXCP_UNALIGN: 3154 env->lock_addr = -1; 3155 info.si_signo = TARGET_SIGBUS; 3156 info.si_errno = 0; 3157 info.si_code = TARGET_BUS_ADRALN; 3158 info._sifields._sigfault._addr = env->trap_arg0; 3159 queue_signal(env, info.si_signo, &info); 3160 break; 3161 case EXCP_OPCDEC: 3162 do_sigill: 3163 env->lock_addr = -1; 3164 info.si_signo = TARGET_SIGILL; 3165 info.si_errno = 0; 3166 info.si_code = TARGET_ILL_ILLOPC; 3167 info._sifields._sigfault._addr = env->pc; 3168 queue_signal(env, info.si_signo, &info); 3169 break; 3170 case EXCP_ARITH: 3171 env->lock_addr = -1; 3172 info.si_signo = TARGET_SIGFPE; 3173 info.si_errno = 0; 3174 info.si_code = TARGET_FPE_FLTINV; 3175 info._sifields._sigfault._addr = env->pc; 3176 queue_signal(env, info.si_signo, &info); 3177 break; 3178 case EXCP_FEN: 3179 /* No-op. Linux simply re-enables the FPU. */ 3180 break; 3181 case EXCP_CALL_PAL: 3182 env->lock_addr = -1; 3183 switch (env->error_code) { 3184 case 0x80: 3185 /* BPT */ 3186 info.si_signo = TARGET_SIGTRAP; 3187 info.si_errno = 0; 3188 info.si_code = TARGET_TRAP_BRKPT; 3189 info._sifields._sigfault._addr = env->pc; 3190 queue_signal(env, info.si_signo, &info); 3191 break; 3192 case 0x81: 3193 /* BUGCHK */ 3194 info.si_signo = TARGET_SIGTRAP; 3195 info.si_errno = 0; 3196 info.si_code = 0; 3197 info._sifields._sigfault._addr = env->pc; 3198 queue_signal(env, info.si_signo, &info); 3199 break; 3200 case 0x83: 3201 /* CALLSYS */ 3202 trapnr = env->ir[IR_V0]; 3203 sysret = do_syscall(env, trapnr, 3204 env->ir[IR_A0], env->ir[IR_A1], 3205 env->ir[IR_A2], env->ir[IR_A3], 3206 env->ir[IR_A4], env->ir[IR_A5], 3207 0, 0); 3208 if (trapnr == TARGET_NR_sigreturn 3209 || trapnr == TARGET_NR_rt_sigreturn) { 3210 break; 3211 } 3212 /* Syscall writes 0 to V0 to bypass error check, similar 3213 to how this is handled internal to Linux kernel. 3214 (Ab)use trapnr temporarily as boolean indicating error. */ 3215 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 3216 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 3217 env->ir[IR_A3] = trapnr; 3218 break; 3219 case 0x86: 3220 /* IMB */ 3221 /* ??? We can probably elide the code using page_unprotect 3222 that is checking for self-modifying code. Instead we 3223 could simply call tb_flush here. Until we work out the 3224 changes required to turn off the extra write protection, 3225 this can be a no-op. */ 3226 break; 3227 case 0x9E: 3228 /* RDUNIQUE */ 3229 /* Handled in the translator for usermode. */ 3230 abort(); 3231 case 0x9F: 3232 /* WRUNIQUE */ 3233 /* Handled in the translator for usermode. */ 3234 abort(); 3235 case 0xAA: 3236 /* GENTRAP */ 3237 info.si_signo = TARGET_SIGFPE; 3238 switch (env->ir[IR_A0]) { 3239 case TARGET_GEN_INTOVF: 3240 info.si_code = TARGET_FPE_INTOVF; 3241 break; 3242 case TARGET_GEN_INTDIV: 3243 info.si_code = TARGET_FPE_INTDIV; 3244 break; 3245 case TARGET_GEN_FLTOVF: 3246 info.si_code = TARGET_FPE_FLTOVF; 3247 break; 3248 case TARGET_GEN_FLTUND: 3249 info.si_code = TARGET_FPE_FLTUND; 3250 break; 3251 case TARGET_GEN_FLTINV: 3252 info.si_code = TARGET_FPE_FLTINV; 3253 break; 3254 case TARGET_GEN_FLTINE: 3255 info.si_code = TARGET_FPE_FLTRES; 3256 break; 3257 case TARGET_GEN_ROPRAND: 3258 info.si_code = 0; 3259 break; 3260 default: 3261 info.si_signo = TARGET_SIGTRAP; 3262 info.si_code = 0; 3263 break; 3264 } 3265 info.si_errno = 0; 3266 info._sifields._sigfault._addr = env->pc; 3267 queue_signal(env, info.si_signo, &info); 3268 break; 3269 default: 3270 goto do_sigill; 3271 } 3272 break; 3273 case EXCP_DEBUG: 3274 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); 3275 if (info.si_signo) { 3276 env->lock_addr = -1; 3277 info.si_errno = 0; 3278 info.si_code = TARGET_TRAP_BRKPT; 3279 queue_signal(env, info.si_signo, &info); 3280 } 3281 break; 3282 case EXCP_STL_C: 3283 case EXCP_STQ_C: 3284 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3285 break; 3286 case EXCP_INTERRUPT: 3287 /* Just indicate that signals should be handled asap. */ 3288 break; 3289 default: 3290 printf ("Unhandled trap: 0x%x\n", trapnr); 3291 cpu_dump_state(cs, stderr, fprintf, 0); 3292 exit (1); 3293 } 3294 process_pending_signals (env); 3295 } 3296 } 3297 #endif /* TARGET_ALPHA */ 3298 3299 #ifdef TARGET_S390X 3300 void cpu_loop(CPUS390XState *env) 3301 { 3302 CPUState *cs = CPU(s390_env_get_cpu(env)); 3303 int trapnr, n, sig; 3304 target_siginfo_t info; 3305 target_ulong addr; 3306 3307 while (1) { 3308 cpu_exec_start(cs); 3309 trapnr = cpu_s390x_exec(env); 3310 cpu_exec_end(cs); 3311 switch (trapnr) { 3312 case EXCP_INTERRUPT: 3313 /* Just indicate that signals should be handled asap. */ 3314 break; 3315 3316 case EXCP_SVC: 3317 n = env->int_svc_code; 3318 if (!n) { 3319 /* syscalls > 255 */ 3320 n = env->regs[1]; 3321 } 3322 env->psw.addr += env->int_svc_ilen; 3323 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], 3324 env->regs[4], env->regs[5], 3325 env->regs[6], env->regs[7], 0, 0); 3326 break; 3327 3328 case EXCP_DEBUG: 3329 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3330 if (sig) { 3331 n = TARGET_TRAP_BRKPT; 3332 goto do_signal_pc; 3333 } 3334 break; 3335 case EXCP_PGM: 3336 n = env->int_pgm_code; 3337 switch (n) { 3338 case PGM_OPERATION: 3339 case PGM_PRIVILEGED: 3340 sig = SIGILL; 3341 n = TARGET_ILL_ILLOPC; 3342 goto do_signal_pc; 3343 case PGM_PROTECTION: 3344 case PGM_ADDRESSING: 3345 sig = SIGSEGV; 3346 /* XXX: check env->error_code */ 3347 n = TARGET_SEGV_MAPERR; 3348 addr = env->__excp_addr; 3349 goto do_signal; 3350 case PGM_EXECUTE: 3351 case PGM_SPECIFICATION: 3352 case PGM_SPECIAL_OP: 3353 case PGM_OPERAND: 3354 do_sigill_opn: 3355 sig = SIGILL; 3356 n = TARGET_ILL_ILLOPN; 3357 goto do_signal_pc; 3358 3359 case PGM_FIXPT_OVERFLOW: 3360 sig = SIGFPE; 3361 n = TARGET_FPE_INTOVF; 3362 goto do_signal_pc; 3363 case PGM_FIXPT_DIVIDE: 3364 sig = SIGFPE; 3365 n = TARGET_FPE_INTDIV; 3366 goto do_signal_pc; 3367 3368 case PGM_DATA: 3369 n = (env->fpc >> 8) & 0xff; 3370 if (n == 0xff) { 3371 /* compare-and-trap */ 3372 goto do_sigill_opn; 3373 } else { 3374 /* An IEEE exception, simulated or otherwise. */ 3375 if (n & 0x80) { 3376 n = TARGET_FPE_FLTINV; 3377 } else if (n & 0x40) { 3378 n = TARGET_FPE_FLTDIV; 3379 } else if (n & 0x20) { 3380 n = TARGET_FPE_FLTOVF; 3381 } else if (n & 0x10) { 3382 n = TARGET_FPE_FLTUND; 3383 } else if (n & 0x08) { 3384 n = TARGET_FPE_FLTRES; 3385 } else { 3386 /* ??? Quantum exception; BFP, DFP error. */ 3387 goto do_sigill_opn; 3388 } 3389 sig = SIGFPE; 3390 goto do_signal_pc; 3391 } 3392 3393 default: 3394 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3395 cpu_dump_state(cs, stderr, fprintf, 0); 3396 exit(1); 3397 } 3398 break; 3399 3400 do_signal_pc: 3401 addr = env->psw.addr; 3402 do_signal: 3403 info.si_signo = sig; 3404 info.si_errno = 0; 3405 info.si_code = n; 3406 info._sifields._sigfault._addr = addr; 3407 queue_signal(env, info.si_signo, &info); 3408 break; 3409 3410 default: 3411 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3412 cpu_dump_state(cs, stderr, fprintf, 0); 3413 exit(1); 3414 } 3415 process_pending_signals (env); 3416 } 3417 } 3418 3419 #endif /* TARGET_S390X */ 3420 3421 THREAD CPUState *thread_cpu; 3422 3423 void task_settid(TaskState *ts) 3424 { 3425 if (ts->ts_tid == 0) { 3426 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3427 } 3428 } 3429 3430 void stop_all_tasks(void) 3431 { 3432 /* 3433 * We trust that when using NPTL, start_exclusive() 3434 * handles thread stopping correctly. 3435 */ 3436 start_exclusive(); 3437 } 3438 3439 /* Assumes contents are already zeroed. */ 3440 void init_task_state(TaskState *ts) 3441 { 3442 int i; 3443 3444 ts->used = 1; 3445 ts->first_free = ts->sigqueue_table; 3446 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 3447 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 3448 } 3449 ts->sigqueue_table[i].next = NULL; 3450 } 3451 3452 CPUArchState *cpu_copy(CPUArchState *env) 3453 { 3454 CPUState *cpu = ENV_GET_CPU(env); 3455 CPUArchState *new_env = cpu_init(cpu_model); 3456 CPUState *new_cpu = ENV_GET_CPU(new_env); 3457 CPUBreakpoint *bp; 3458 CPUWatchpoint *wp; 3459 3460 /* Reset non arch specific state */ 3461 cpu_reset(new_cpu); 3462 3463 memcpy(new_env, env, sizeof(CPUArchState)); 3464 3465 /* Clone all break/watchpoints. 3466 Note: Once we support ptrace with hw-debug register access, make sure 3467 BP_CPU break/watchpoints are handled correctly on clone. */ 3468 QTAILQ_INIT(&cpu->breakpoints); 3469 QTAILQ_INIT(&cpu->watchpoints); 3470 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 3471 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); 3472 } 3473 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { 3474 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); 3475 } 3476 3477 return new_env; 3478 } 3479 3480 static void handle_arg_help(const char *arg) 3481 { 3482 usage(); 3483 } 3484 3485 static void handle_arg_log(const char *arg) 3486 { 3487 int mask; 3488 3489 mask = qemu_str_to_log_mask(arg); 3490 if (!mask) { 3491 qemu_print_log_usage(stdout); 3492 exit(1); 3493 } 3494 qemu_set_log(mask); 3495 } 3496 3497 static void handle_arg_log_filename(const char *arg) 3498 { 3499 qemu_set_log_filename(arg); 3500 } 3501 3502 static void handle_arg_set_env(const char *arg) 3503 { 3504 char *r, *p, *token; 3505 r = p = strdup(arg); 3506 while ((token = strsep(&p, ",")) != NULL) { 3507 if (envlist_setenv(envlist, token) != 0) { 3508 usage(); 3509 } 3510 } 3511 free(r); 3512 } 3513 3514 static void handle_arg_unset_env(const char *arg) 3515 { 3516 char *r, *p, *token; 3517 r = p = strdup(arg); 3518 while ((token = strsep(&p, ",")) != NULL) { 3519 if (envlist_unsetenv(envlist, token) != 0) { 3520 usage(); 3521 } 3522 } 3523 free(r); 3524 } 3525 3526 static void handle_arg_argv0(const char *arg) 3527 { 3528 argv0 = strdup(arg); 3529 } 3530 3531 static void handle_arg_stack_size(const char *arg) 3532 { 3533 char *p; 3534 guest_stack_size = strtoul(arg, &p, 0); 3535 if (guest_stack_size == 0) { 3536 usage(); 3537 } 3538 3539 if (*p == 'M') { 3540 guest_stack_size *= 1024 * 1024; 3541 } else if (*p == 'k' || *p == 'K') { 3542 guest_stack_size *= 1024; 3543 } 3544 } 3545 3546 static void handle_arg_ld_prefix(const char *arg) 3547 { 3548 interp_prefix = strdup(arg); 3549 } 3550 3551 static void handle_arg_pagesize(const char *arg) 3552 { 3553 qemu_host_page_size = atoi(arg); 3554 if (qemu_host_page_size == 0 || 3555 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3556 fprintf(stderr, "page size must be a power of two\n"); 3557 exit(1); 3558 } 3559 } 3560 3561 static void handle_arg_randseed(const char *arg) 3562 { 3563 unsigned long long seed; 3564 3565 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) { 3566 fprintf(stderr, "Invalid seed number: %s\n", arg); 3567 exit(1); 3568 } 3569 srand(seed); 3570 } 3571 3572 static void handle_arg_gdb(const char *arg) 3573 { 3574 gdbstub_port = atoi(arg); 3575 } 3576 3577 static void handle_arg_uname(const char *arg) 3578 { 3579 qemu_uname_release = strdup(arg); 3580 } 3581 3582 static void handle_arg_cpu(const char *arg) 3583 { 3584 cpu_model = strdup(arg); 3585 if (cpu_model == NULL || is_help_option(cpu_model)) { 3586 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3587 #if defined(cpu_list) 3588 cpu_list(stdout, &fprintf); 3589 #endif 3590 exit(1); 3591 } 3592 } 3593 3594 #if defined(CONFIG_USE_GUEST_BASE) 3595 static void handle_arg_guest_base(const char *arg) 3596 { 3597 guest_base = strtol(arg, NULL, 0); 3598 have_guest_base = 1; 3599 } 3600 3601 static void handle_arg_reserved_va(const char *arg) 3602 { 3603 char *p; 3604 int shift = 0; 3605 reserved_va = strtoul(arg, &p, 0); 3606 switch (*p) { 3607 case 'k': 3608 case 'K': 3609 shift = 10; 3610 break; 3611 case 'M': 3612 shift = 20; 3613 break; 3614 case 'G': 3615 shift = 30; 3616 break; 3617 } 3618 if (shift) { 3619 unsigned long unshifted = reserved_va; 3620 p++; 3621 reserved_va <<= shift; 3622 if (((reserved_va >> shift) != unshifted) 3623 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3624 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3625 #endif 3626 ) { 3627 fprintf(stderr, "Reserved virtual address too big\n"); 3628 exit(1); 3629 } 3630 } 3631 if (*p) { 3632 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3633 exit(1); 3634 } 3635 } 3636 #endif 3637 3638 static void handle_arg_singlestep(const char *arg) 3639 { 3640 singlestep = 1; 3641 } 3642 3643 static void handle_arg_strace(const char *arg) 3644 { 3645 do_strace = 1; 3646 } 3647 3648 static void handle_arg_version(const char *arg) 3649 { 3650 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3651 ", Copyright (c) 2003-2008 Fabrice Bellard\n"); 3652 exit(0); 3653 } 3654 3655 struct qemu_argument { 3656 const char *argv; 3657 const char *env; 3658 bool has_arg; 3659 void (*handle_opt)(const char *arg); 3660 const char *example; 3661 const char *help; 3662 }; 3663 3664 static const struct qemu_argument arg_table[] = { 3665 {"h", "", false, handle_arg_help, 3666 "", "print this help"}, 3667 {"g", "QEMU_GDB", true, handle_arg_gdb, 3668 "port", "wait gdb connection to 'port'"}, 3669 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3670 "path", "set the elf interpreter prefix to 'path'"}, 3671 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3672 "size", "set the stack size to 'size' bytes"}, 3673 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3674 "model", "select CPU (-cpu help for list)"}, 3675 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3676 "var=value", "sets targets environment variable (see below)"}, 3677 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3678 "var", "unsets targets environment variable (see below)"}, 3679 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 3680 "argv0", "forces target process argv[0] to be 'argv0'"}, 3681 {"r", "QEMU_UNAME", true, handle_arg_uname, 3682 "uname", "set qemu uname release string to 'uname'"}, 3683 #if defined(CONFIG_USE_GUEST_BASE) 3684 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 3685 "address", "set guest_base address to 'address'"}, 3686 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 3687 "size", "reserve 'size' bytes for guest virtual address space"}, 3688 #endif 3689 {"d", "QEMU_LOG", true, handle_arg_log, 3690 "item[,...]", "enable logging of specified items " 3691 "(use '-d help' for a list of items)"}, 3692 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 3693 "logfile", "write logs to 'logfile' (default stderr)"}, 3694 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 3695 "pagesize", "set the host page size to 'pagesize'"}, 3696 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 3697 "", "run in singlestep mode"}, 3698 {"strace", "QEMU_STRACE", false, handle_arg_strace, 3699 "", "log system calls"}, 3700 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed, 3701 "", "Seed for pseudo-random number generator"}, 3702 {"version", "QEMU_VERSION", false, handle_arg_version, 3703 "", "display version information and exit"}, 3704 {NULL, NULL, false, NULL, NULL, NULL} 3705 }; 3706 3707 static void usage(void) 3708 { 3709 const struct qemu_argument *arginfo; 3710 int maxarglen; 3711 int maxenvlen; 3712 3713 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 3714 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 3715 "\n" 3716 "Options and associated environment variables:\n" 3717 "\n"); 3718 3719 /* Calculate column widths. We must always have at least enough space 3720 * for the column header. 3721 */ 3722 maxarglen = strlen("Argument"); 3723 maxenvlen = strlen("Env-variable"); 3724 3725 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3726 int arglen = strlen(arginfo->argv); 3727 if (arginfo->has_arg) { 3728 arglen += strlen(arginfo->example) + 1; 3729 } 3730 if (strlen(arginfo->env) > maxenvlen) { 3731 maxenvlen = strlen(arginfo->env); 3732 } 3733 if (arglen > maxarglen) { 3734 maxarglen = arglen; 3735 } 3736 } 3737 3738 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 3739 maxenvlen, "Env-variable"); 3740 3741 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3742 if (arginfo->has_arg) { 3743 printf("-%s %-*s %-*s %s\n", arginfo->argv, 3744 (int)(maxarglen - strlen(arginfo->argv) - 1), 3745 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 3746 } else { 3747 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 3748 maxenvlen, arginfo->env, 3749 arginfo->help); 3750 } 3751 } 3752 3753 printf("\n" 3754 "Defaults:\n" 3755 "QEMU_LD_PREFIX = %s\n" 3756 "QEMU_STACK_SIZE = %ld byte\n", 3757 interp_prefix, 3758 guest_stack_size); 3759 3760 printf("\n" 3761 "You can use -E and -U options or the QEMU_SET_ENV and\n" 3762 "QEMU_UNSET_ENV environment variables to set and unset\n" 3763 "environment variables for the target process.\n" 3764 "It is possible to provide several variables by separating them\n" 3765 "by commas in getsubopt(3) style. Additionally it is possible to\n" 3766 "provide the -E and -U options multiple times.\n" 3767 "The following lines are equivalent:\n" 3768 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 3769 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 3770 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 3771 "Note that if you provide several changes to a single variable\n" 3772 "the last change will stay in effect.\n"); 3773 3774 exit(1); 3775 } 3776 3777 static int parse_args(int argc, char **argv) 3778 { 3779 const char *r; 3780 int optind; 3781 const struct qemu_argument *arginfo; 3782 3783 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3784 if (arginfo->env == NULL) { 3785 continue; 3786 } 3787 3788 r = getenv(arginfo->env); 3789 if (r != NULL) { 3790 arginfo->handle_opt(r); 3791 } 3792 } 3793 3794 optind = 1; 3795 for (;;) { 3796 if (optind >= argc) { 3797 break; 3798 } 3799 r = argv[optind]; 3800 if (r[0] != '-') { 3801 break; 3802 } 3803 optind++; 3804 r++; 3805 if (!strcmp(r, "-")) { 3806 break; 3807 } 3808 3809 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3810 if (!strcmp(r, arginfo->argv)) { 3811 if (arginfo->has_arg) { 3812 if (optind >= argc) { 3813 usage(); 3814 } 3815 arginfo->handle_opt(argv[optind]); 3816 optind++; 3817 } else { 3818 arginfo->handle_opt(NULL); 3819 } 3820 break; 3821 } 3822 } 3823 3824 /* no option matched the current argv */ 3825 if (arginfo->handle_opt == NULL) { 3826 usage(); 3827 } 3828 } 3829 3830 if (optind >= argc) { 3831 usage(); 3832 } 3833 3834 filename = argv[optind]; 3835 exec_path = argv[optind]; 3836 3837 return optind; 3838 } 3839 3840 int main(int argc, char **argv, char **envp) 3841 { 3842 struct target_pt_regs regs1, *regs = ®s1; 3843 struct image_info info1, *info = &info1; 3844 struct linux_binprm bprm; 3845 TaskState *ts; 3846 CPUArchState *env; 3847 CPUState *cpu; 3848 int optind; 3849 char **target_environ, **wrk; 3850 char **target_argv; 3851 int target_argc; 3852 int i; 3853 int ret; 3854 int execfd; 3855 3856 module_call_init(MODULE_INIT_QOM); 3857 3858 if ((envlist = envlist_create()) == NULL) { 3859 (void) fprintf(stderr, "Unable to allocate envlist\n"); 3860 exit(1); 3861 } 3862 3863 /* add current environment into the list */ 3864 for (wrk = environ; *wrk != NULL; wrk++) { 3865 (void) envlist_setenv(envlist, *wrk); 3866 } 3867 3868 /* Read the stack limit from the kernel. If it's "unlimited", 3869 then we can do little else besides use the default. */ 3870 { 3871 struct rlimit lim; 3872 if (getrlimit(RLIMIT_STACK, &lim) == 0 3873 && lim.rlim_cur != RLIM_INFINITY 3874 && lim.rlim_cur == (target_long)lim.rlim_cur) { 3875 guest_stack_size = lim.rlim_cur; 3876 } 3877 } 3878 3879 cpu_model = NULL; 3880 #if defined(cpudef_setup) 3881 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ 3882 #endif 3883 3884 srand(time(NULL)); 3885 3886 optind = parse_args(argc, argv); 3887 3888 /* Zero out regs */ 3889 memset(regs, 0, sizeof(struct target_pt_regs)); 3890 3891 /* Zero out image_info */ 3892 memset(info, 0, sizeof(struct image_info)); 3893 3894 memset(&bprm, 0, sizeof (bprm)); 3895 3896 /* Scan interp_prefix dir for replacement files. */ 3897 init_paths(interp_prefix); 3898 3899 init_qemu_uname_release(); 3900 3901 if (cpu_model == NULL) { 3902 #if defined(TARGET_I386) 3903 #ifdef TARGET_X86_64 3904 cpu_model = "qemu64"; 3905 #else 3906 cpu_model = "qemu32"; 3907 #endif 3908 #elif defined(TARGET_ARM) 3909 cpu_model = "any"; 3910 #elif defined(TARGET_UNICORE32) 3911 cpu_model = "any"; 3912 #elif defined(TARGET_M68K) 3913 cpu_model = "any"; 3914 #elif defined(TARGET_SPARC) 3915 #ifdef TARGET_SPARC64 3916 cpu_model = "TI UltraSparc II"; 3917 #else 3918 cpu_model = "Fujitsu MB86904"; 3919 #endif 3920 #elif defined(TARGET_MIPS) 3921 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 3922 cpu_model = "5KEf"; 3923 #else 3924 cpu_model = "24Kf"; 3925 #endif 3926 #elif defined TARGET_OPENRISC 3927 cpu_model = "or1200"; 3928 #elif defined(TARGET_PPC) 3929 # ifdef TARGET_PPC64 3930 cpu_model = "POWER7"; 3931 # else 3932 cpu_model = "750"; 3933 # endif 3934 #else 3935 cpu_model = "any"; 3936 #endif 3937 } 3938 tcg_exec_init(0); 3939 cpu_exec_init_all(); 3940 /* NOTE: we need to init the CPU at this stage to get 3941 qemu_host_page_size */ 3942 env = cpu_init(cpu_model); 3943 if (!env) { 3944 fprintf(stderr, "Unable to find CPU definition\n"); 3945 exit(1); 3946 } 3947 cpu = ENV_GET_CPU(env); 3948 cpu_reset(cpu); 3949 3950 thread_cpu = cpu; 3951 3952 if (getenv("QEMU_STRACE")) { 3953 do_strace = 1; 3954 } 3955 3956 if (getenv("QEMU_RAND_SEED")) { 3957 handle_arg_randseed(getenv("QEMU_RAND_SEED")); 3958 } 3959 3960 target_environ = envlist_to_environ(envlist, NULL); 3961 envlist_free(envlist); 3962 3963 #if defined(CONFIG_USE_GUEST_BASE) 3964 /* 3965 * Now that page sizes are configured in cpu_init() we can do 3966 * proper page alignment for guest_base. 3967 */ 3968 guest_base = HOST_PAGE_ALIGN(guest_base); 3969 3970 if (reserved_va || have_guest_base) { 3971 guest_base = init_guest_space(guest_base, reserved_va, 0, 3972 have_guest_base); 3973 if (guest_base == (unsigned long)-1) { 3974 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 3975 "space for use as guest address space (check your virtual " 3976 "memory ulimit setting or reserve less using -R option)\n", 3977 reserved_va); 3978 exit(1); 3979 } 3980 3981 if (reserved_va) { 3982 mmap_next_start = reserved_va; 3983 } 3984 } 3985 #endif /* CONFIG_USE_GUEST_BASE */ 3986 3987 /* 3988 * Read in mmap_min_addr kernel parameter. This value is used 3989 * When loading the ELF image to determine whether guest_base 3990 * is needed. It is also used in mmap_find_vma. 3991 */ 3992 { 3993 FILE *fp; 3994 3995 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 3996 unsigned long tmp; 3997 if (fscanf(fp, "%lu", &tmp) == 1) { 3998 mmap_min_addr = tmp; 3999 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); 4000 } 4001 fclose(fp); 4002 } 4003 } 4004 4005 /* 4006 * Prepare copy of argv vector for target. 4007 */ 4008 target_argc = argc - optind; 4009 target_argv = calloc(target_argc + 1, sizeof (char *)); 4010 if (target_argv == NULL) { 4011 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 4012 exit(1); 4013 } 4014 4015 /* 4016 * If argv0 is specified (using '-0' switch) we replace 4017 * argv[0] pointer with the given one. 4018 */ 4019 i = 0; 4020 if (argv0 != NULL) { 4021 target_argv[i++] = strdup(argv0); 4022 } 4023 for (; i < target_argc; i++) { 4024 target_argv[i] = strdup(argv[optind + i]); 4025 } 4026 target_argv[target_argc] = NULL; 4027 4028 ts = g_malloc0 (sizeof(TaskState)); 4029 init_task_state(ts); 4030 /* build Task State */ 4031 ts->info = info; 4032 ts->bprm = &bprm; 4033 cpu->opaque = ts; 4034 task_settid(ts); 4035 4036 execfd = qemu_getauxval(AT_EXECFD); 4037 if (execfd == 0) { 4038 execfd = open(filename, O_RDONLY); 4039 if (execfd < 0) { 4040 printf("Error while loading %s: %s\n", filename, strerror(errno)); 4041 _exit(1); 4042 } 4043 } 4044 4045 ret = loader_exec(execfd, filename, target_argv, target_environ, regs, 4046 info, &bprm); 4047 if (ret != 0) { 4048 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 4049 _exit(1); 4050 } 4051 4052 for (wrk = target_environ; *wrk; wrk++) { 4053 free(*wrk); 4054 } 4055 4056 free(target_environ); 4057 4058 if (qemu_log_enabled()) { 4059 #if defined(CONFIG_USE_GUEST_BASE) 4060 qemu_log("guest_base 0x%lx\n", guest_base); 4061 #endif 4062 log_page_dump(); 4063 4064 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 4065 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 4066 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 4067 info->start_code); 4068 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 4069 info->start_data); 4070 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 4071 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 4072 info->start_stack); 4073 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 4074 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 4075 } 4076 4077 target_set_brk(info->brk); 4078 syscall_init(); 4079 signal_init(); 4080 4081 #if defined(CONFIG_USE_GUEST_BASE) 4082 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 4083 generating the prologue until now so that the prologue can take 4084 the real value of GUEST_BASE into account. */ 4085 tcg_prologue_init(&tcg_ctx); 4086 #endif 4087 4088 #if defined(TARGET_I386) 4089 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 4090 env->hflags |= HF_PE_MASK | HF_CPL_MASK; 4091 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4092 env->cr[4] |= CR4_OSFXSR_MASK; 4093 env->hflags |= HF_OSFXSR_MASK; 4094 } 4095 #ifndef TARGET_ABI32 4096 /* enable 64 bit mode if possible */ 4097 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 4098 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 4099 exit(1); 4100 } 4101 env->cr[4] |= CR4_PAE_MASK; 4102 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 4103 env->hflags |= HF_LMA_MASK; 4104 #endif 4105 4106 /* flags setup : we activate the IRQs by default as in user mode */ 4107 env->eflags |= IF_MASK; 4108 4109 /* linux register setup */ 4110 #ifndef TARGET_ABI32 4111 env->regs[R_EAX] = regs->rax; 4112 env->regs[R_EBX] = regs->rbx; 4113 env->regs[R_ECX] = regs->rcx; 4114 env->regs[R_EDX] = regs->rdx; 4115 env->regs[R_ESI] = regs->rsi; 4116 env->regs[R_EDI] = regs->rdi; 4117 env->regs[R_EBP] = regs->rbp; 4118 env->regs[R_ESP] = regs->rsp; 4119 env->eip = regs->rip; 4120 #else 4121 env->regs[R_EAX] = regs->eax; 4122 env->regs[R_EBX] = regs->ebx; 4123 env->regs[R_ECX] = regs->ecx; 4124 env->regs[R_EDX] = regs->edx; 4125 env->regs[R_ESI] = regs->esi; 4126 env->regs[R_EDI] = regs->edi; 4127 env->regs[R_EBP] = regs->ebp; 4128 env->regs[R_ESP] = regs->esp; 4129 env->eip = regs->eip; 4130 #endif 4131 4132 /* linux interrupt setup */ 4133 #ifndef TARGET_ABI32 4134 env->idt.limit = 511; 4135 #else 4136 env->idt.limit = 255; 4137 #endif 4138 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 4139 PROT_READ|PROT_WRITE, 4140 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4141 idt_table = g2h(env->idt.base); 4142 set_idt(0, 0); 4143 set_idt(1, 0); 4144 set_idt(2, 0); 4145 set_idt(3, 3); 4146 set_idt(4, 3); 4147 set_idt(5, 0); 4148 set_idt(6, 0); 4149 set_idt(7, 0); 4150 set_idt(8, 0); 4151 set_idt(9, 0); 4152 set_idt(10, 0); 4153 set_idt(11, 0); 4154 set_idt(12, 0); 4155 set_idt(13, 0); 4156 set_idt(14, 0); 4157 set_idt(15, 0); 4158 set_idt(16, 0); 4159 set_idt(17, 0); 4160 set_idt(18, 0); 4161 set_idt(19, 0); 4162 set_idt(0x80, 3); 4163 4164 /* linux segment setup */ 4165 { 4166 uint64_t *gdt_table; 4167 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 4168 PROT_READ|PROT_WRITE, 4169 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4170 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 4171 gdt_table = g2h(env->gdt.base); 4172 #ifdef TARGET_ABI32 4173 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4174 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4175 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4176 #else 4177 /* 64 bit code segment */ 4178 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4179 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4180 DESC_L_MASK | 4181 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4182 #endif 4183 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 4184 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4185 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 4186 } 4187 cpu_x86_load_seg(env, R_CS, __USER_CS); 4188 cpu_x86_load_seg(env, R_SS, __USER_DS); 4189 #ifdef TARGET_ABI32 4190 cpu_x86_load_seg(env, R_DS, __USER_DS); 4191 cpu_x86_load_seg(env, R_ES, __USER_DS); 4192 cpu_x86_load_seg(env, R_FS, __USER_DS); 4193 cpu_x86_load_seg(env, R_GS, __USER_DS); 4194 /* This hack makes Wine work... */ 4195 env->segs[R_FS].selector = 0; 4196 #else 4197 cpu_x86_load_seg(env, R_DS, 0); 4198 cpu_x86_load_seg(env, R_ES, 0); 4199 cpu_x86_load_seg(env, R_FS, 0); 4200 cpu_x86_load_seg(env, R_GS, 0); 4201 #endif 4202 #elif defined(TARGET_AARCH64) 4203 { 4204 int i; 4205 4206 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 4207 fprintf(stderr, 4208 "The selected ARM CPU does not support 64 bit mode\n"); 4209 exit(1); 4210 } 4211 4212 for (i = 0; i < 31; i++) { 4213 env->xregs[i] = regs->regs[i]; 4214 } 4215 env->pc = regs->pc; 4216 env->xregs[31] = regs->sp; 4217 } 4218 #elif defined(TARGET_ARM) 4219 { 4220 int i; 4221 cpsr_write(env, regs->uregs[16], 0xffffffff); 4222 for(i = 0; i < 16; i++) { 4223 env->regs[i] = regs->uregs[i]; 4224 } 4225 /* Enable BE8. */ 4226 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 4227 && (info->elf_flags & EF_ARM_BE8)) { 4228 env->bswap_code = 1; 4229 } 4230 } 4231 #elif defined(TARGET_UNICORE32) 4232 { 4233 int i; 4234 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 4235 for (i = 0; i < 32; i++) { 4236 env->regs[i] = regs->uregs[i]; 4237 } 4238 } 4239 #elif defined(TARGET_SPARC) 4240 { 4241 int i; 4242 env->pc = regs->pc; 4243 env->npc = regs->npc; 4244 env->y = regs->y; 4245 for(i = 0; i < 8; i++) 4246 env->gregs[i] = regs->u_regs[i]; 4247 for(i = 0; i < 8; i++) 4248 env->regwptr[i] = regs->u_regs[i + 8]; 4249 } 4250 #elif defined(TARGET_PPC) 4251 { 4252 int i; 4253 4254 #if defined(TARGET_PPC64) 4255 #if defined(TARGET_ABI32) 4256 env->msr &= ~((target_ulong)1 << MSR_SF); 4257 #else 4258 env->msr |= (target_ulong)1 << MSR_SF; 4259 #endif 4260 #endif 4261 env->nip = regs->nip; 4262 for(i = 0; i < 32; i++) { 4263 env->gpr[i] = regs->gpr[i]; 4264 } 4265 } 4266 #elif defined(TARGET_M68K) 4267 { 4268 env->pc = regs->pc; 4269 env->dregs[0] = regs->d0; 4270 env->dregs[1] = regs->d1; 4271 env->dregs[2] = regs->d2; 4272 env->dregs[3] = regs->d3; 4273 env->dregs[4] = regs->d4; 4274 env->dregs[5] = regs->d5; 4275 env->dregs[6] = regs->d6; 4276 env->dregs[7] = regs->d7; 4277 env->aregs[0] = regs->a0; 4278 env->aregs[1] = regs->a1; 4279 env->aregs[2] = regs->a2; 4280 env->aregs[3] = regs->a3; 4281 env->aregs[4] = regs->a4; 4282 env->aregs[5] = regs->a5; 4283 env->aregs[6] = regs->a6; 4284 env->aregs[7] = regs->usp; 4285 env->sr = regs->sr; 4286 ts->sim_syscalls = 1; 4287 } 4288 #elif defined(TARGET_MICROBLAZE) 4289 { 4290 env->regs[0] = regs->r0; 4291 env->regs[1] = regs->r1; 4292 env->regs[2] = regs->r2; 4293 env->regs[3] = regs->r3; 4294 env->regs[4] = regs->r4; 4295 env->regs[5] = regs->r5; 4296 env->regs[6] = regs->r6; 4297 env->regs[7] = regs->r7; 4298 env->regs[8] = regs->r8; 4299 env->regs[9] = regs->r9; 4300 env->regs[10] = regs->r10; 4301 env->regs[11] = regs->r11; 4302 env->regs[12] = regs->r12; 4303 env->regs[13] = regs->r13; 4304 env->regs[14] = regs->r14; 4305 env->regs[15] = regs->r15; 4306 env->regs[16] = regs->r16; 4307 env->regs[17] = regs->r17; 4308 env->regs[18] = regs->r18; 4309 env->regs[19] = regs->r19; 4310 env->regs[20] = regs->r20; 4311 env->regs[21] = regs->r21; 4312 env->regs[22] = regs->r22; 4313 env->regs[23] = regs->r23; 4314 env->regs[24] = regs->r24; 4315 env->regs[25] = regs->r25; 4316 env->regs[26] = regs->r26; 4317 env->regs[27] = regs->r27; 4318 env->regs[28] = regs->r28; 4319 env->regs[29] = regs->r29; 4320 env->regs[30] = regs->r30; 4321 env->regs[31] = regs->r31; 4322 env->sregs[SR_PC] = regs->pc; 4323 } 4324 #elif defined(TARGET_MIPS) 4325 { 4326 int i; 4327 4328 for(i = 0; i < 32; i++) { 4329 env->active_tc.gpr[i] = regs->regs[i]; 4330 } 4331 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 4332 if (regs->cp0_epc & 1) { 4333 env->hflags |= MIPS_HFLAG_M16; 4334 } 4335 } 4336 #elif defined(TARGET_OPENRISC) 4337 { 4338 int i; 4339 4340 for (i = 0; i < 32; i++) { 4341 env->gpr[i] = regs->gpr[i]; 4342 } 4343 4344 env->sr = regs->sr; 4345 env->pc = regs->pc; 4346 } 4347 #elif defined(TARGET_SH4) 4348 { 4349 int i; 4350 4351 for(i = 0; i < 16; i++) { 4352 env->gregs[i] = regs->regs[i]; 4353 } 4354 env->pc = regs->pc; 4355 } 4356 #elif defined(TARGET_ALPHA) 4357 { 4358 int i; 4359 4360 for(i = 0; i < 28; i++) { 4361 env->ir[i] = ((abi_ulong *)regs)[i]; 4362 } 4363 env->ir[IR_SP] = regs->usp; 4364 env->pc = regs->pc; 4365 } 4366 #elif defined(TARGET_CRIS) 4367 { 4368 env->regs[0] = regs->r0; 4369 env->regs[1] = regs->r1; 4370 env->regs[2] = regs->r2; 4371 env->regs[3] = regs->r3; 4372 env->regs[4] = regs->r4; 4373 env->regs[5] = regs->r5; 4374 env->regs[6] = regs->r6; 4375 env->regs[7] = regs->r7; 4376 env->regs[8] = regs->r8; 4377 env->regs[9] = regs->r9; 4378 env->regs[10] = regs->r10; 4379 env->regs[11] = regs->r11; 4380 env->regs[12] = regs->r12; 4381 env->regs[13] = regs->r13; 4382 env->regs[14] = info->start_stack; 4383 env->regs[15] = regs->acr; 4384 env->pc = regs->erp; 4385 } 4386 #elif defined(TARGET_S390X) 4387 { 4388 int i; 4389 for (i = 0; i < 16; i++) { 4390 env->regs[i] = regs->gprs[i]; 4391 } 4392 env->psw.mask = regs->psw.mask; 4393 env->psw.addr = regs->psw.addr; 4394 } 4395 #else 4396 #error unsupported target CPU 4397 #endif 4398 4399 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4400 ts->stack_base = info->start_stack; 4401 ts->heap_base = info->brk; 4402 /* This will be filled in on the first SYS_HEAPINFO call. */ 4403 ts->heap_limit = 0; 4404 #endif 4405 4406 if (gdbstub_port) { 4407 if (gdbserver_start(gdbstub_port) < 0) { 4408 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4409 gdbstub_port); 4410 exit(1); 4411 } 4412 gdb_handlesig(cpu, 0); 4413 } 4414 cpu_loop(env); 4415 /* never exits */ 4416 return 0; 4417 } 4418