1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu-version.h" 21 #include <sys/syscall.h> 22 #include <sys/resource.h> 23 24 #include "qapi/error.h" 25 #include "qemu.h" 26 #include "qemu/path.h" 27 #include "qemu/config-file.h" 28 #include "qemu/cutils.h" 29 #include "qemu/help_option.h" 30 #include "cpu.h" 31 #include "exec/exec-all.h" 32 #include "tcg.h" 33 #include "qemu/timer.h" 34 #include "qemu/envlist.h" 35 #include "elf.h" 36 #include "exec/log.h" 37 #include "trace/control.h" 38 #include "glib-compat.h" 39 40 char *exec_path; 41 42 int singlestep; 43 static const char *filename; 44 static const char *argv0; 45 static int gdbstub_port; 46 static envlist_t *envlist; 47 static const char *cpu_model; 48 unsigned long mmap_min_addr; 49 unsigned long guest_base; 50 int have_guest_base; 51 52 #define EXCP_DUMP(env, fmt, ...) \ 53 do { \ 54 CPUState *cs = ENV_GET_CPU(env); \ 55 fprintf(stderr, fmt , ## __VA_ARGS__); \ 56 cpu_dump_state(cs, stderr, fprintf, 0); \ 57 if (qemu_log_separate()) { \ 58 qemu_log(fmt, ## __VA_ARGS__); \ 59 log_cpu_state(cs, 0); \ 60 } \ 61 } while (0) 62 63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 64 /* 65 * When running 32-on-64 we should make sure we can fit all of the possible 66 * guest address space into a contiguous chunk of virtual host memory. 67 * 68 * This way we will never overlap with our own libraries or binaries or stack 69 * or anything else that QEMU maps. 70 */ 71 # ifdef TARGET_MIPS 72 /* MIPS only supports 31 bits of virtual address space for user space */ 73 unsigned long reserved_va = 0x77000000; 74 # else 75 unsigned long reserved_va = 0xf7000000; 76 # endif 77 #else 78 unsigned long reserved_va; 79 #endif 80 81 static void usage(int exitcode); 82 83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 84 const char *qemu_uname_release; 85 86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 87 we allocate a bigger stack. Need a better solution, for example 88 by remapping the process stack directly at the right place */ 89 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 90 91 void gemu_log(const char *fmt, ...) 92 { 93 va_list ap; 94 95 va_start(ap, fmt); 96 vfprintf(stderr, fmt, ap); 97 va_end(ap); 98 } 99 100 #if defined(TARGET_I386) 101 int cpu_get_pic_interrupt(CPUX86State *env) 102 { 103 return -1; 104 } 105 #endif 106 107 /***********************************************************/ 108 /* Helper routines for implementing atomic operations. */ 109 110 /* Make sure everything is in a consistent state for calling fork(). */ 111 void fork_start(void) 112 { 113 cpu_list_lock(); 114 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 115 mmap_fork_start(); 116 } 117 118 void fork_end(int child) 119 { 120 mmap_fork_end(child); 121 if (child) { 122 CPUState *cpu, *next_cpu; 123 /* Child processes created by fork() only have a single thread. 124 Discard information about the parent threads. */ 125 CPU_FOREACH_SAFE(cpu, next_cpu) { 126 if (cpu != thread_cpu) { 127 QTAILQ_REMOVE(&cpus, cpu, node); 128 } 129 } 130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); 131 qemu_init_cpu_list(); 132 gdbserver_fork(thread_cpu); 133 } else { 134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 135 cpu_list_unlock(); 136 } 137 } 138 139 #ifdef TARGET_I386 140 /***********************************************************/ 141 /* CPUX86 core interface */ 142 143 uint64_t cpu_get_tsc(CPUX86State *env) 144 { 145 return cpu_get_host_ticks(); 146 } 147 148 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 149 int flags) 150 { 151 unsigned int e1, e2; 152 uint32_t *p; 153 e1 = (addr << 16) | (limit & 0xffff); 154 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 155 e2 |= flags; 156 p = ptr; 157 p[0] = tswap32(e1); 158 p[1] = tswap32(e2); 159 } 160 161 static uint64_t *idt_table; 162 #ifdef TARGET_X86_64 163 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 164 uint64_t addr, unsigned int sel) 165 { 166 uint32_t *p, e1, e2; 167 e1 = (addr & 0xffff) | (sel << 16); 168 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 169 p = ptr; 170 p[0] = tswap32(e1); 171 p[1] = tswap32(e2); 172 p[2] = tswap32(addr >> 32); 173 p[3] = 0; 174 } 175 /* only dpl matters as we do only user space emulation */ 176 static void set_idt(int n, unsigned int dpl) 177 { 178 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 179 } 180 #else 181 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 182 uint32_t addr, unsigned int sel) 183 { 184 uint32_t *p, e1, e2; 185 e1 = (addr & 0xffff) | (sel << 16); 186 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 187 p = ptr; 188 p[0] = tswap32(e1); 189 p[1] = tswap32(e2); 190 } 191 192 /* only dpl matters as we do only user space emulation */ 193 static void set_idt(int n, unsigned int dpl) 194 { 195 set_gate(idt_table + n, 0, dpl, 0, 0); 196 } 197 #endif 198 199 void cpu_loop(CPUX86State *env) 200 { 201 CPUState *cs = CPU(x86_env_get_cpu(env)); 202 int trapnr; 203 abi_ulong pc; 204 abi_ulong ret; 205 target_siginfo_t info; 206 207 for(;;) { 208 cpu_exec_start(cs); 209 trapnr = cpu_exec(cs); 210 cpu_exec_end(cs); 211 process_queued_cpu_work(cs); 212 213 switch(trapnr) { 214 case 0x80: 215 /* linux syscall from int $0x80 */ 216 ret = do_syscall(env, 217 env->regs[R_EAX], 218 env->regs[R_EBX], 219 env->regs[R_ECX], 220 env->regs[R_EDX], 221 env->regs[R_ESI], 222 env->regs[R_EDI], 223 env->regs[R_EBP], 224 0, 0); 225 if (ret == -TARGET_ERESTARTSYS) { 226 env->eip -= 2; 227 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 228 env->regs[R_EAX] = ret; 229 } 230 break; 231 #ifndef TARGET_ABI32 232 case EXCP_SYSCALL: 233 /* linux syscall from syscall instruction */ 234 ret = do_syscall(env, 235 env->regs[R_EAX], 236 env->regs[R_EDI], 237 env->regs[R_ESI], 238 env->regs[R_EDX], 239 env->regs[10], 240 env->regs[8], 241 env->regs[9], 242 0, 0); 243 if (ret == -TARGET_ERESTARTSYS) { 244 env->eip -= 2; 245 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 246 env->regs[R_EAX] = ret; 247 } 248 break; 249 #endif 250 case EXCP0B_NOSEG: 251 case EXCP0C_STACK: 252 info.si_signo = TARGET_SIGBUS; 253 info.si_errno = 0; 254 info.si_code = TARGET_SI_KERNEL; 255 info._sifields._sigfault._addr = 0; 256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 257 break; 258 case EXCP0D_GPF: 259 /* XXX: potential problem if ABI32 */ 260 #ifndef TARGET_X86_64 261 if (env->eflags & VM_MASK) { 262 handle_vm86_fault(env); 263 } else 264 #endif 265 { 266 info.si_signo = TARGET_SIGSEGV; 267 info.si_errno = 0; 268 info.si_code = TARGET_SI_KERNEL; 269 info._sifields._sigfault._addr = 0; 270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 271 } 272 break; 273 case EXCP0E_PAGE: 274 info.si_signo = TARGET_SIGSEGV; 275 info.si_errno = 0; 276 if (!(env->error_code & 1)) 277 info.si_code = TARGET_SEGV_MAPERR; 278 else 279 info.si_code = TARGET_SEGV_ACCERR; 280 info._sifields._sigfault._addr = env->cr[2]; 281 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 282 break; 283 case EXCP00_DIVZ: 284 #ifndef TARGET_X86_64 285 if (env->eflags & VM_MASK) { 286 handle_vm86_trap(env, trapnr); 287 } else 288 #endif 289 { 290 /* division by zero */ 291 info.si_signo = TARGET_SIGFPE; 292 info.si_errno = 0; 293 info.si_code = TARGET_FPE_INTDIV; 294 info._sifields._sigfault._addr = env->eip; 295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 296 } 297 break; 298 case EXCP01_DB: 299 case EXCP03_INT3: 300 #ifndef TARGET_X86_64 301 if (env->eflags & VM_MASK) { 302 handle_vm86_trap(env, trapnr); 303 } else 304 #endif 305 { 306 info.si_signo = TARGET_SIGTRAP; 307 info.si_errno = 0; 308 if (trapnr == EXCP01_DB) { 309 info.si_code = TARGET_TRAP_BRKPT; 310 info._sifields._sigfault._addr = env->eip; 311 } else { 312 info.si_code = TARGET_SI_KERNEL; 313 info._sifields._sigfault._addr = 0; 314 } 315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 316 } 317 break; 318 case EXCP04_INTO: 319 case EXCP05_BOUND: 320 #ifndef TARGET_X86_64 321 if (env->eflags & VM_MASK) { 322 handle_vm86_trap(env, trapnr); 323 } else 324 #endif 325 { 326 info.si_signo = TARGET_SIGSEGV; 327 info.si_errno = 0; 328 info.si_code = TARGET_SI_KERNEL; 329 info._sifields._sigfault._addr = 0; 330 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 331 } 332 break; 333 case EXCP06_ILLOP: 334 info.si_signo = TARGET_SIGILL; 335 info.si_errno = 0; 336 info.si_code = TARGET_ILL_ILLOPN; 337 info._sifields._sigfault._addr = env->eip; 338 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 339 break; 340 case EXCP_INTERRUPT: 341 /* just indicate that signals should be handled asap */ 342 break; 343 case EXCP_DEBUG: 344 { 345 int sig; 346 347 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 348 if (sig) 349 { 350 info.si_signo = sig; 351 info.si_errno = 0; 352 info.si_code = TARGET_TRAP_BRKPT; 353 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 354 } 355 } 356 break; 357 default: 358 pc = env->segs[R_CS].base + env->eip; 359 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 360 (long)pc, trapnr); 361 abort(); 362 } 363 process_pending_signals(env); 364 } 365 } 366 #endif 367 368 #ifdef TARGET_ARM 369 370 #define get_user_code_u32(x, gaddr, env) \ 371 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 372 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 373 (x) = bswap32(x); \ 374 } \ 375 __r; \ 376 }) 377 378 #define get_user_code_u16(x, gaddr, env) \ 379 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 380 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 381 (x) = bswap16(x); \ 382 } \ 383 __r; \ 384 }) 385 386 #define get_user_data_u32(x, gaddr, env) \ 387 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 388 if (!__r && arm_cpu_bswap_data(env)) { \ 389 (x) = bswap32(x); \ 390 } \ 391 __r; \ 392 }) 393 394 #define get_user_data_u16(x, gaddr, env) \ 395 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 396 if (!__r && arm_cpu_bswap_data(env)) { \ 397 (x) = bswap16(x); \ 398 } \ 399 __r; \ 400 }) 401 402 #define put_user_data_u32(x, gaddr, env) \ 403 ({ typeof(x) __x = (x); \ 404 if (arm_cpu_bswap_data(env)) { \ 405 __x = bswap32(__x); \ 406 } \ 407 put_user_u32(__x, (gaddr)); \ 408 }) 409 410 #define put_user_data_u16(x, gaddr, env) \ 411 ({ typeof(x) __x = (x); \ 412 if (arm_cpu_bswap_data(env)) { \ 413 __x = bswap16(__x); \ 414 } \ 415 put_user_u16(__x, (gaddr)); \ 416 }) 417 418 #ifdef TARGET_ABI32 419 /* Commpage handling -- there is no commpage for AArch64 */ 420 421 /* 422 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 423 * Input: 424 * r0 = pointer to oldval 425 * r1 = pointer to newval 426 * r2 = pointer to target value 427 * 428 * Output: 429 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 430 * C set if *ptr was changed, clear if no exchange happened 431 * 432 * Note segv's in kernel helpers are a bit tricky, we can set the 433 * data address sensibly but the PC address is just the entry point. 434 */ 435 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 436 { 437 uint64_t oldval, newval, val; 438 uint32_t addr, cpsr; 439 target_siginfo_t info; 440 441 /* Based on the 32 bit code in do_kernel_trap */ 442 443 /* XXX: This only works between threads, not between processes. 444 It's probably possible to implement this with native host 445 operations. However things like ldrex/strex are much harder so 446 there's not much point trying. */ 447 start_exclusive(); 448 cpsr = cpsr_read(env); 449 addr = env->regs[2]; 450 451 if (get_user_u64(oldval, env->regs[0])) { 452 env->exception.vaddress = env->regs[0]; 453 goto segv; 454 }; 455 456 if (get_user_u64(newval, env->regs[1])) { 457 env->exception.vaddress = env->regs[1]; 458 goto segv; 459 }; 460 461 if (get_user_u64(val, addr)) { 462 env->exception.vaddress = addr; 463 goto segv; 464 } 465 466 if (val == oldval) { 467 val = newval; 468 469 if (put_user_u64(val, addr)) { 470 env->exception.vaddress = addr; 471 goto segv; 472 }; 473 474 env->regs[0] = 0; 475 cpsr |= CPSR_C; 476 } else { 477 env->regs[0] = -1; 478 cpsr &= ~CPSR_C; 479 } 480 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 481 end_exclusive(); 482 return; 483 484 segv: 485 end_exclusive(); 486 /* We get the PC of the entry address - which is as good as anything, 487 on a real kernel what you get depends on which mode it uses. */ 488 info.si_signo = TARGET_SIGSEGV; 489 info.si_errno = 0; 490 /* XXX: check env->error_code */ 491 info.si_code = TARGET_SEGV_MAPERR; 492 info._sifields._sigfault._addr = env->exception.vaddress; 493 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 494 } 495 496 /* Handle a jump to the kernel code page. */ 497 static int 498 do_kernel_trap(CPUARMState *env) 499 { 500 uint32_t addr; 501 uint32_t cpsr; 502 uint32_t val; 503 504 switch (env->regs[15]) { 505 case 0xffff0fa0: /* __kernel_memory_barrier */ 506 /* ??? No-op. Will need to do better for SMP. */ 507 break; 508 case 0xffff0fc0: /* __kernel_cmpxchg */ 509 /* XXX: This only works between threads, not between processes. 510 It's probably possible to implement this with native host 511 operations. However things like ldrex/strex are much harder so 512 there's not much point trying. */ 513 start_exclusive(); 514 cpsr = cpsr_read(env); 515 addr = env->regs[2]; 516 /* FIXME: This should SEGV if the access fails. */ 517 if (get_user_u32(val, addr)) 518 val = ~env->regs[0]; 519 if (val == env->regs[0]) { 520 val = env->regs[1]; 521 /* FIXME: Check for segfaults. */ 522 put_user_u32(val, addr); 523 env->regs[0] = 0; 524 cpsr |= CPSR_C; 525 } else { 526 env->regs[0] = -1; 527 cpsr &= ~CPSR_C; 528 } 529 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 530 end_exclusive(); 531 break; 532 case 0xffff0fe0: /* __kernel_get_tls */ 533 env->regs[0] = cpu_get_tls(env); 534 break; 535 case 0xffff0f60: /* __kernel_cmpxchg64 */ 536 arm_kernel_cmpxchg64_helper(env); 537 break; 538 539 default: 540 return 1; 541 } 542 /* Jump back to the caller. */ 543 addr = env->regs[14]; 544 if (addr & 1) { 545 env->thumb = 1; 546 addr &= ~1; 547 } 548 env->regs[15] = addr; 549 550 return 0; 551 } 552 553 /* Store exclusive handling for AArch32 */ 554 static int do_strex(CPUARMState *env) 555 { 556 uint64_t val; 557 int size; 558 int rc = 1; 559 int segv = 0; 560 uint32_t addr; 561 start_exclusive(); 562 if (env->exclusive_addr != env->exclusive_test) { 563 goto fail; 564 } 565 /* We know we're always AArch32 so the address is in uint32_t range 566 * unless it was the -1 exclusive-monitor-lost value (which won't 567 * match exclusive_test above). 568 */ 569 assert(extract64(env->exclusive_addr, 32, 32) == 0); 570 addr = env->exclusive_addr; 571 size = env->exclusive_info & 0xf; 572 switch (size) { 573 case 0: 574 segv = get_user_u8(val, addr); 575 break; 576 case 1: 577 segv = get_user_data_u16(val, addr, env); 578 break; 579 case 2: 580 case 3: 581 segv = get_user_data_u32(val, addr, env); 582 break; 583 default: 584 abort(); 585 } 586 if (segv) { 587 env->exception.vaddress = addr; 588 goto done; 589 } 590 if (size == 3) { 591 uint32_t valhi; 592 segv = get_user_data_u32(valhi, addr + 4, env); 593 if (segv) { 594 env->exception.vaddress = addr + 4; 595 goto done; 596 } 597 if (arm_cpu_bswap_data(env)) { 598 val = deposit64((uint64_t)valhi, 32, 32, val); 599 } else { 600 val = deposit64(val, 32, 32, valhi); 601 } 602 } 603 if (val != env->exclusive_val) { 604 goto fail; 605 } 606 607 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 608 switch (size) { 609 case 0: 610 segv = put_user_u8(val, addr); 611 break; 612 case 1: 613 segv = put_user_data_u16(val, addr, env); 614 break; 615 case 2: 616 case 3: 617 segv = put_user_data_u32(val, addr, env); 618 break; 619 } 620 if (segv) { 621 env->exception.vaddress = addr; 622 goto done; 623 } 624 if (size == 3) { 625 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 626 segv = put_user_data_u32(val, addr + 4, env); 627 if (segv) { 628 env->exception.vaddress = addr + 4; 629 goto done; 630 } 631 } 632 rc = 0; 633 fail: 634 env->regs[15] += 4; 635 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 636 done: 637 end_exclusive(); 638 return segv; 639 } 640 641 void cpu_loop(CPUARMState *env) 642 { 643 CPUState *cs = CPU(arm_env_get_cpu(env)); 644 int trapnr; 645 unsigned int n, insn; 646 target_siginfo_t info; 647 uint32_t addr; 648 abi_ulong ret; 649 650 for(;;) { 651 cpu_exec_start(cs); 652 trapnr = cpu_exec(cs); 653 cpu_exec_end(cs); 654 process_queued_cpu_work(cs); 655 656 switch(trapnr) { 657 case EXCP_UDEF: 658 { 659 TaskState *ts = cs->opaque; 660 uint32_t opcode; 661 int rc; 662 663 /* we handle the FPU emulation here, as Linux */ 664 /* we get the opcode */ 665 /* FIXME - what to do if get_user() fails? */ 666 get_user_code_u32(opcode, env->regs[15], env); 667 668 rc = EmulateAll(opcode, &ts->fpa, env); 669 if (rc == 0) { /* illegal instruction */ 670 info.si_signo = TARGET_SIGILL; 671 info.si_errno = 0; 672 info.si_code = TARGET_ILL_ILLOPN; 673 info._sifields._sigfault._addr = env->regs[15]; 674 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 675 } else if (rc < 0) { /* FP exception */ 676 int arm_fpe=0; 677 678 /* translate softfloat flags to FPSR flags */ 679 if (-rc & float_flag_invalid) 680 arm_fpe |= BIT_IOC; 681 if (-rc & float_flag_divbyzero) 682 arm_fpe |= BIT_DZC; 683 if (-rc & float_flag_overflow) 684 arm_fpe |= BIT_OFC; 685 if (-rc & float_flag_underflow) 686 arm_fpe |= BIT_UFC; 687 if (-rc & float_flag_inexact) 688 arm_fpe |= BIT_IXC; 689 690 FPSR fpsr = ts->fpa.fpsr; 691 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 692 693 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 694 info.si_signo = TARGET_SIGFPE; 695 info.si_errno = 0; 696 697 /* ordered by priority, least first */ 698 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 699 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 700 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 701 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 702 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 703 704 info._sifields._sigfault._addr = env->regs[15]; 705 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 706 } else { 707 env->regs[15] += 4; 708 } 709 710 /* accumulate unenabled exceptions */ 711 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 712 fpsr |= BIT_IXC; 713 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 714 fpsr |= BIT_UFC; 715 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 716 fpsr |= BIT_OFC; 717 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 718 fpsr |= BIT_DZC; 719 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 720 fpsr |= BIT_IOC; 721 ts->fpa.fpsr=fpsr; 722 } else { /* everything OK */ 723 /* increment PC */ 724 env->regs[15] += 4; 725 } 726 } 727 break; 728 case EXCP_SWI: 729 case EXCP_BKPT: 730 { 731 env->eabi = 1; 732 /* system call */ 733 if (trapnr == EXCP_BKPT) { 734 if (env->thumb) { 735 /* FIXME - what to do if get_user() fails? */ 736 get_user_code_u16(insn, env->regs[15], env); 737 n = insn & 0xff; 738 env->regs[15] += 2; 739 } else { 740 /* FIXME - what to do if get_user() fails? */ 741 get_user_code_u32(insn, env->regs[15], env); 742 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 743 env->regs[15] += 4; 744 } 745 } else { 746 if (env->thumb) { 747 /* FIXME - what to do if get_user() fails? */ 748 get_user_code_u16(insn, env->regs[15] - 2, env); 749 n = insn & 0xff; 750 } else { 751 /* FIXME - what to do if get_user() fails? */ 752 get_user_code_u32(insn, env->regs[15] - 4, env); 753 n = insn & 0xffffff; 754 } 755 } 756 757 if (n == ARM_NR_cacheflush) { 758 /* nop */ 759 } else if (n == ARM_NR_semihosting 760 || n == ARM_NR_thumb_semihosting) { 761 env->regs[0] = do_arm_semihosting (env); 762 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 763 /* linux syscall */ 764 if (env->thumb || n == 0) { 765 n = env->regs[7]; 766 } else { 767 n -= ARM_SYSCALL_BASE; 768 env->eabi = 0; 769 } 770 if ( n > ARM_NR_BASE) { 771 switch (n) { 772 case ARM_NR_cacheflush: 773 /* nop */ 774 break; 775 case ARM_NR_set_tls: 776 cpu_set_tls(env, env->regs[0]); 777 env->regs[0] = 0; 778 break; 779 case ARM_NR_breakpoint: 780 env->regs[15] -= env->thumb ? 2 : 4; 781 goto excp_debug; 782 default: 783 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 784 n); 785 env->regs[0] = -TARGET_ENOSYS; 786 break; 787 } 788 } else { 789 ret = do_syscall(env, 790 n, 791 env->regs[0], 792 env->regs[1], 793 env->regs[2], 794 env->regs[3], 795 env->regs[4], 796 env->regs[5], 797 0, 0); 798 if (ret == -TARGET_ERESTARTSYS) { 799 env->regs[15] -= env->thumb ? 2 : 4; 800 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 801 env->regs[0] = ret; 802 } 803 } 804 } else { 805 goto error; 806 } 807 } 808 break; 809 case EXCP_INTERRUPT: 810 /* just indicate that signals should be handled asap */ 811 break; 812 case EXCP_STREX: 813 if (!do_strex(env)) { 814 break; 815 } 816 /* fall through for segv */ 817 case EXCP_PREFETCH_ABORT: 818 case EXCP_DATA_ABORT: 819 addr = env->exception.vaddress; 820 { 821 info.si_signo = TARGET_SIGSEGV; 822 info.si_errno = 0; 823 /* XXX: check env->error_code */ 824 info.si_code = TARGET_SEGV_MAPERR; 825 info._sifields._sigfault._addr = addr; 826 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 827 } 828 break; 829 case EXCP_DEBUG: 830 excp_debug: 831 { 832 int sig; 833 834 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 835 if (sig) 836 { 837 info.si_signo = sig; 838 info.si_errno = 0; 839 info.si_code = TARGET_TRAP_BRKPT; 840 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 841 } 842 } 843 break; 844 case EXCP_KERNEL_TRAP: 845 if (do_kernel_trap(env)) 846 goto error; 847 break; 848 case EXCP_YIELD: 849 /* nothing to do here for user-mode, just resume guest code */ 850 break; 851 default: 852 error: 853 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 854 abort(); 855 } 856 process_pending_signals(env); 857 } 858 } 859 860 #else 861 862 /* 863 * Handle AArch64 store-release exclusive 864 * 865 * rs = gets the status result of store exclusive 866 * rt = is the register that is stored 867 * rt2 = is the second register store (in STP) 868 * 869 */ 870 static int do_strex_a64(CPUARMState *env) 871 { 872 uint64_t val; 873 int size; 874 bool is_pair; 875 int rc = 1; 876 int segv = 0; 877 uint64_t addr; 878 int rs, rt, rt2; 879 880 start_exclusive(); 881 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ 882 size = extract32(env->exclusive_info, 0, 2); 883 is_pair = extract32(env->exclusive_info, 2, 1); 884 rs = extract32(env->exclusive_info, 4, 5); 885 rt = extract32(env->exclusive_info, 9, 5); 886 rt2 = extract32(env->exclusive_info, 14, 5); 887 888 addr = env->exclusive_addr; 889 890 if (addr != env->exclusive_test) { 891 goto finish; 892 } 893 894 switch (size) { 895 case 0: 896 segv = get_user_u8(val, addr); 897 break; 898 case 1: 899 segv = get_user_u16(val, addr); 900 break; 901 case 2: 902 segv = get_user_u32(val, addr); 903 break; 904 case 3: 905 segv = get_user_u64(val, addr); 906 break; 907 default: 908 abort(); 909 } 910 if (segv) { 911 env->exception.vaddress = addr; 912 goto error; 913 } 914 if (val != env->exclusive_val) { 915 goto finish; 916 } 917 if (is_pair) { 918 if (size == 2) { 919 segv = get_user_u32(val, addr + 4); 920 } else { 921 segv = get_user_u64(val, addr + 8); 922 } 923 if (segv) { 924 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 925 goto error; 926 } 927 if (val != env->exclusive_high) { 928 goto finish; 929 } 930 } 931 /* handle the zero register */ 932 val = rt == 31 ? 0 : env->xregs[rt]; 933 switch (size) { 934 case 0: 935 segv = put_user_u8(val, addr); 936 break; 937 case 1: 938 segv = put_user_u16(val, addr); 939 break; 940 case 2: 941 segv = put_user_u32(val, addr); 942 break; 943 case 3: 944 segv = put_user_u64(val, addr); 945 break; 946 } 947 if (segv) { 948 goto error; 949 } 950 if (is_pair) { 951 /* handle the zero register */ 952 val = rt2 == 31 ? 0 : env->xregs[rt2]; 953 if (size == 2) { 954 segv = put_user_u32(val, addr + 4); 955 } else { 956 segv = put_user_u64(val, addr + 8); 957 } 958 if (segv) { 959 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 960 goto error; 961 } 962 } 963 rc = 0; 964 finish: 965 env->pc += 4; 966 /* rs == 31 encodes a write to the ZR, thus throwing away 967 * the status return. This is rather silly but valid. 968 */ 969 if (rs < 31) { 970 env->xregs[rs] = rc; 971 } 972 error: 973 /* instruction faulted, PC does not advance */ 974 /* either way a strex releases any exclusive lock we have */ 975 env->exclusive_addr = -1; 976 end_exclusive(); 977 return segv; 978 } 979 980 /* AArch64 main loop */ 981 void cpu_loop(CPUARMState *env) 982 { 983 CPUState *cs = CPU(arm_env_get_cpu(env)); 984 int trapnr, sig; 985 abi_long ret; 986 target_siginfo_t info; 987 988 for (;;) { 989 cpu_exec_start(cs); 990 trapnr = cpu_exec(cs); 991 cpu_exec_end(cs); 992 process_queued_cpu_work(cs); 993 994 switch (trapnr) { 995 case EXCP_SWI: 996 ret = do_syscall(env, 997 env->xregs[8], 998 env->xregs[0], 999 env->xregs[1], 1000 env->xregs[2], 1001 env->xregs[3], 1002 env->xregs[4], 1003 env->xregs[5], 1004 0, 0); 1005 if (ret == -TARGET_ERESTARTSYS) { 1006 env->pc -= 4; 1007 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 1008 env->xregs[0] = ret; 1009 } 1010 break; 1011 case EXCP_INTERRUPT: 1012 /* just indicate that signals should be handled asap */ 1013 break; 1014 case EXCP_UDEF: 1015 info.si_signo = TARGET_SIGILL; 1016 info.si_errno = 0; 1017 info.si_code = TARGET_ILL_ILLOPN; 1018 info._sifields._sigfault._addr = env->pc; 1019 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1020 break; 1021 case EXCP_STREX: 1022 if (!do_strex_a64(env)) { 1023 break; 1024 } 1025 /* fall through for segv */ 1026 case EXCP_PREFETCH_ABORT: 1027 case EXCP_DATA_ABORT: 1028 info.si_signo = TARGET_SIGSEGV; 1029 info.si_errno = 0; 1030 /* XXX: check env->error_code */ 1031 info.si_code = TARGET_SEGV_MAPERR; 1032 info._sifields._sigfault._addr = env->exception.vaddress; 1033 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1034 break; 1035 case EXCP_DEBUG: 1036 case EXCP_BKPT: 1037 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1038 if (sig) { 1039 info.si_signo = sig; 1040 info.si_errno = 0; 1041 info.si_code = TARGET_TRAP_BRKPT; 1042 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1043 } 1044 break; 1045 case EXCP_SEMIHOST: 1046 env->xregs[0] = do_arm_semihosting(env); 1047 break; 1048 case EXCP_YIELD: 1049 /* nothing to do here for user-mode, just resume guest code */ 1050 break; 1051 default: 1052 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1053 abort(); 1054 } 1055 process_pending_signals(env); 1056 /* Exception return on AArch64 always clears the exclusive monitor, 1057 * so any return to running guest code implies this. 1058 * A strex (successful or otherwise) also clears the monitor, so 1059 * we don't need to specialcase EXCP_STREX. 1060 */ 1061 env->exclusive_addr = -1; 1062 } 1063 } 1064 #endif /* ndef TARGET_ABI32 */ 1065 1066 #endif 1067 1068 #ifdef TARGET_UNICORE32 1069 1070 void cpu_loop(CPUUniCore32State *env) 1071 { 1072 CPUState *cs = CPU(uc32_env_get_cpu(env)); 1073 int trapnr; 1074 unsigned int n, insn; 1075 target_siginfo_t info; 1076 1077 for (;;) { 1078 cpu_exec_start(cs); 1079 trapnr = cpu_exec(cs); 1080 cpu_exec_end(cs); 1081 process_queued_cpu_work(cs); 1082 1083 switch (trapnr) { 1084 case UC32_EXCP_PRIV: 1085 { 1086 /* system call */ 1087 get_user_u32(insn, env->regs[31] - 4); 1088 n = insn & 0xffffff; 1089 1090 if (n >= UC32_SYSCALL_BASE) { 1091 /* linux syscall */ 1092 n -= UC32_SYSCALL_BASE; 1093 if (n == UC32_SYSCALL_NR_set_tls) { 1094 cpu_set_tls(env, env->regs[0]); 1095 env->regs[0] = 0; 1096 } else { 1097 abi_long ret = do_syscall(env, 1098 n, 1099 env->regs[0], 1100 env->regs[1], 1101 env->regs[2], 1102 env->regs[3], 1103 env->regs[4], 1104 env->regs[5], 1105 0, 0); 1106 if (ret == -TARGET_ERESTARTSYS) { 1107 env->regs[31] -= 4; 1108 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 1109 env->regs[0] = ret; 1110 } 1111 } 1112 } else { 1113 goto error; 1114 } 1115 } 1116 break; 1117 case UC32_EXCP_DTRAP: 1118 case UC32_EXCP_ITRAP: 1119 info.si_signo = TARGET_SIGSEGV; 1120 info.si_errno = 0; 1121 /* XXX: check env->error_code */ 1122 info.si_code = TARGET_SEGV_MAPERR; 1123 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 1124 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1125 break; 1126 case EXCP_INTERRUPT: 1127 /* just indicate that signals should be handled asap */ 1128 break; 1129 case EXCP_DEBUG: 1130 { 1131 int sig; 1132 1133 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1134 if (sig) { 1135 info.si_signo = sig; 1136 info.si_errno = 0; 1137 info.si_code = TARGET_TRAP_BRKPT; 1138 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1139 } 1140 } 1141 break; 1142 default: 1143 goto error; 1144 } 1145 process_pending_signals(env); 1146 } 1147 1148 error: 1149 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1150 abort(); 1151 } 1152 #endif 1153 1154 #ifdef TARGET_SPARC 1155 #define SPARC64_STACK_BIAS 2047 1156 1157 //#define DEBUG_WIN 1158 1159 /* WARNING: dealing with register windows _is_ complicated. More info 1160 can be found at http://www.sics.se/~psm/sparcstack.html */ 1161 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 1162 { 1163 index = (index + cwp * 16) % (16 * env->nwindows); 1164 /* wrap handling : if cwp is on the last window, then we use the 1165 registers 'after' the end */ 1166 if (index < 8 && env->cwp == env->nwindows - 1) 1167 index += 16 * env->nwindows; 1168 return index; 1169 } 1170 1171 /* save the register window 'cwp1' */ 1172 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1173 { 1174 unsigned int i; 1175 abi_ulong sp_ptr; 1176 1177 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1178 #ifdef TARGET_SPARC64 1179 if (sp_ptr & 3) 1180 sp_ptr += SPARC64_STACK_BIAS; 1181 #endif 1182 #if defined(DEBUG_WIN) 1183 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1184 sp_ptr, cwp1); 1185 #endif 1186 for(i = 0; i < 16; i++) { 1187 /* FIXME - what to do if put_user() fails? */ 1188 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1189 sp_ptr += sizeof(abi_ulong); 1190 } 1191 } 1192 1193 static void save_window(CPUSPARCState *env) 1194 { 1195 #ifndef TARGET_SPARC64 1196 unsigned int new_wim; 1197 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1198 ((1LL << env->nwindows) - 1); 1199 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1200 env->wim = new_wim; 1201 #else 1202 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1203 env->cansave++; 1204 env->canrestore--; 1205 #endif 1206 } 1207 1208 static void restore_window(CPUSPARCState *env) 1209 { 1210 #ifndef TARGET_SPARC64 1211 unsigned int new_wim; 1212 #endif 1213 unsigned int i, cwp1; 1214 abi_ulong sp_ptr; 1215 1216 #ifndef TARGET_SPARC64 1217 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1218 ((1LL << env->nwindows) - 1); 1219 #endif 1220 1221 /* restore the invalid window */ 1222 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1223 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1224 #ifdef TARGET_SPARC64 1225 if (sp_ptr & 3) 1226 sp_ptr += SPARC64_STACK_BIAS; 1227 #endif 1228 #if defined(DEBUG_WIN) 1229 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1230 sp_ptr, cwp1); 1231 #endif 1232 for(i = 0; i < 16; i++) { 1233 /* FIXME - what to do if get_user() fails? */ 1234 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1235 sp_ptr += sizeof(abi_ulong); 1236 } 1237 #ifdef TARGET_SPARC64 1238 env->canrestore++; 1239 if (env->cleanwin < env->nwindows - 1) 1240 env->cleanwin++; 1241 env->cansave--; 1242 #else 1243 env->wim = new_wim; 1244 #endif 1245 } 1246 1247 static void flush_windows(CPUSPARCState *env) 1248 { 1249 int offset, cwp1; 1250 1251 offset = 1; 1252 for(;;) { 1253 /* if restore would invoke restore_window(), then we can stop */ 1254 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1255 #ifndef TARGET_SPARC64 1256 if (env->wim & (1 << cwp1)) 1257 break; 1258 #else 1259 if (env->canrestore == 0) 1260 break; 1261 env->cansave++; 1262 env->canrestore--; 1263 #endif 1264 save_window_offset(env, cwp1); 1265 offset++; 1266 } 1267 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1268 #ifndef TARGET_SPARC64 1269 /* set wim so that restore will reload the registers */ 1270 env->wim = 1 << cwp1; 1271 #endif 1272 #if defined(DEBUG_WIN) 1273 printf("flush_windows: nb=%d\n", offset - 1); 1274 #endif 1275 } 1276 1277 void cpu_loop (CPUSPARCState *env) 1278 { 1279 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1280 int trapnr; 1281 abi_long ret; 1282 target_siginfo_t info; 1283 1284 while (1) { 1285 cpu_exec_start(cs); 1286 trapnr = cpu_exec(cs); 1287 cpu_exec_end(cs); 1288 process_queued_cpu_work(cs); 1289 1290 /* Compute PSR before exposing state. */ 1291 if (env->cc_op != CC_OP_FLAGS) { 1292 cpu_get_psr(env); 1293 } 1294 1295 switch (trapnr) { 1296 #ifndef TARGET_SPARC64 1297 case 0x88: 1298 case 0x90: 1299 #else 1300 case 0x110: 1301 case 0x16d: 1302 #endif 1303 ret = do_syscall (env, env->gregs[1], 1304 env->regwptr[0], env->regwptr[1], 1305 env->regwptr[2], env->regwptr[3], 1306 env->regwptr[4], env->regwptr[5], 1307 0, 0); 1308 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { 1309 break; 1310 } 1311 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1312 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1313 env->xcc |= PSR_CARRY; 1314 #else 1315 env->psr |= PSR_CARRY; 1316 #endif 1317 ret = -ret; 1318 } else { 1319 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1320 env->xcc &= ~PSR_CARRY; 1321 #else 1322 env->psr &= ~PSR_CARRY; 1323 #endif 1324 } 1325 env->regwptr[0] = ret; 1326 /* next instruction */ 1327 env->pc = env->npc; 1328 env->npc = env->npc + 4; 1329 break; 1330 case 0x83: /* flush windows */ 1331 #ifdef TARGET_ABI32 1332 case 0x103: 1333 #endif 1334 flush_windows(env); 1335 /* next instruction */ 1336 env->pc = env->npc; 1337 env->npc = env->npc + 4; 1338 break; 1339 #ifndef TARGET_SPARC64 1340 case TT_WIN_OVF: /* window overflow */ 1341 save_window(env); 1342 break; 1343 case TT_WIN_UNF: /* window underflow */ 1344 restore_window(env); 1345 break; 1346 case TT_TFAULT: 1347 case TT_DFAULT: 1348 { 1349 info.si_signo = TARGET_SIGSEGV; 1350 info.si_errno = 0; 1351 /* XXX: check env->error_code */ 1352 info.si_code = TARGET_SEGV_MAPERR; 1353 info._sifields._sigfault._addr = env->mmuregs[4]; 1354 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1355 } 1356 break; 1357 #else 1358 case TT_SPILL: /* window overflow */ 1359 save_window(env); 1360 break; 1361 case TT_FILL: /* window underflow */ 1362 restore_window(env); 1363 break; 1364 case TT_TFAULT: 1365 case TT_DFAULT: 1366 { 1367 info.si_signo = TARGET_SIGSEGV; 1368 info.si_errno = 0; 1369 /* XXX: check env->error_code */ 1370 info.si_code = TARGET_SEGV_MAPERR; 1371 if (trapnr == TT_DFAULT) 1372 info._sifields._sigfault._addr = env->dmmuregs[4]; 1373 else 1374 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1375 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1376 } 1377 break; 1378 #ifndef TARGET_ABI32 1379 case 0x16e: 1380 flush_windows(env); 1381 sparc64_get_context(env); 1382 break; 1383 case 0x16f: 1384 flush_windows(env); 1385 sparc64_set_context(env); 1386 break; 1387 #endif 1388 #endif 1389 case EXCP_INTERRUPT: 1390 /* just indicate that signals should be handled asap */ 1391 break; 1392 case TT_ILL_INSN: 1393 { 1394 info.si_signo = TARGET_SIGILL; 1395 info.si_errno = 0; 1396 info.si_code = TARGET_ILL_ILLOPC; 1397 info._sifields._sigfault._addr = env->pc; 1398 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1399 } 1400 break; 1401 case EXCP_DEBUG: 1402 { 1403 int sig; 1404 1405 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1406 if (sig) 1407 { 1408 info.si_signo = sig; 1409 info.si_errno = 0; 1410 info.si_code = TARGET_TRAP_BRKPT; 1411 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1412 } 1413 } 1414 break; 1415 default: 1416 printf ("Unhandled trap: 0x%x\n", trapnr); 1417 cpu_dump_state(cs, stderr, fprintf, 0); 1418 exit(EXIT_FAILURE); 1419 } 1420 process_pending_signals (env); 1421 } 1422 } 1423 1424 #endif 1425 1426 #ifdef TARGET_PPC 1427 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1428 { 1429 return cpu_get_host_ticks(); 1430 } 1431 1432 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1433 { 1434 return cpu_ppc_get_tb(env); 1435 } 1436 1437 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1438 { 1439 return cpu_ppc_get_tb(env) >> 32; 1440 } 1441 1442 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1443 { 1444 return cpu_ppc_get_tb(env); 1445 } 1446 1447 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1448 { 1449 return cpu_ppc_get_tb(env) >> 32; 1450 } 1451 1452 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1453 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1454 1455 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1456 { 1457 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1458 } 1459 1460 /* XXX: to be fixed */ 1461 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1462 { 1463 return -1; 1464 } 1465 1466 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1467 { 1468 return -1; 1469 } 1470 1471 static int do_store_exclusive(CPUPPCState *env) 1472 { 1473 target_ulong addr; 1474 target_ulong page_addr; 1475 target_ulong val, val2 __attribute__((unused)) = 0; 1476 int flags; 1477 int segv = 0; 1478 1479 addr = env->reserve_ea; 1480 page_addr = addr & TARGET_PAGE_MASK; 1481 start_exclusive(); 1482 mmap_lock(); 1483 flags = page_get_flags(page_addr); 1484 if ((flags & PAGE_READ) == 0) { 1485 segv = 1; 1486 } else { 1487 int reg = env->reserve_info & 0x1f; 1488 int size = env->reserve_info >> 5; 1489 int stored = 0; 1490 1491 if (addr == env->reserve_addr) { 1492 switch (size) { 1493 case 1: segv = get_user_u8(val, addr); break; 1494 case 2: segv = get_user_u16(val, addr); break; 1495 case 4: segv = get_user_u32(val, addr); break; 1496 #if defined(TARGET_PPC64) 1497 case 8: segv = get_user_u64(val, addr); break; 1498 case 16: { 1499 segv = get_user_u64(val, addr); 1500 if (!segv) { 1501 segv = get_user_u64(val2, addr + 8); 1502 } 1503 break; 1504 } 1505 #endif 1506 default: abort(); 1507 } 1508 if (!segv && val == env->reserve_val) { 1509 val = env->gpr[reg]; 1510 switch (size) { 1511 case 1: segv = put_user_u8(val, addr); break; 1512 case 2: segv = put_user_u16(val, addr); break; 1513 case 4: segv = put_user_u32(val, addr); break; 1514 #if defined(TARGET_PPC64) 1515 case 8: segv = put_user_u64(val, addr); break; 1516 case 16: { 1517 if (val2 == env->reserve_val2) { 1518 if (msr_le) { 1519 val2 = val; 1520 val = env->gpr[reg+1]; 1521 } else { 1522 val2 = env->gpr[reg+1]; 1523 } 1524 segv = put_user_u64(val, addr); 1525 if (!segv) { 1526 segv = put_user_u64(val2, addr + 8); 1527 } 1528 } 1529 break; 1530 } 1531 #endif 1532 default: abort(); 1533 } 1534 if (!segv) { 1535 stored = 1; 1536 } 1537 } 1538 } 1539 env->crf[0] = (stored << 1) | xer_so; 1540 env->reserve_addr = (target_ulong)-1; 1541 } 1542 if (!segv) { 1543 env->nip += 4; 1544 } 1545 mmap_unlock(); 1546 end_exclusive(); 1547 return segv; 1548 } 1549 1550 void cpu_loop(CPUPPCState *env) 1551 { 1552 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1553 target_siginfo_t info; 1554 int trapnr; 1555 target_ulong ret; 1556 1557 for(;;) { 1558 cpu_exec_start(cs); 1559 trapnr = cpu_exec(cs); 1560 cpu_exec_end(cs); 1561 process_queued_cpu_work(cs); 1562 1563 switch(trapnr) { 1564 case POWERPC_EXCP_NONE: 1565 /* Just go on */ 1566 break; 1567 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1568 cpu_abort(cs, "Critical interrupt while in user mode. " 1569 "Aborting\n"); 1570 break; 1571 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1572 cpu_abort(cs, "Machine check exception while in user mode. " 1573 "Aborting\n"); 1574 break; 1575 case POWERPC_EXCP_DSI: /* Data storage exception */ 1576 /* XXX: check this. Seems bugged */ 1577 switch (env->error_code & 0xFF000000) { 1578 case 0x40000000: 1579 case 0x42000000: 1580 info.si_signo = TARGET_SIGSEGV; 1581 info.si_errno = 0; 1582 info.si_code = TARGET_SEGV_MAPERR; 1583 break; 1584 case 0x04000000: 1585 info.si_signo = TARGET_SIGILL; 1586 info.si_errno = 0; 1587 info.si_code = TARGET_ILL_ILLADR; 1588 break; 1589 case 0x08000000: 1590 info.si_signo = TARGET_SIGSEGV; 1591 info.si_errno = 0; 1592 info.si_code = TARGET_SEGV_ACCERR; 1593 break; 1594 default: 1595 /* Let's send a regular segfault... */ 1596 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1597 env->error_code); 1598 info.si_signo = TARGET_SIGSEGV; 1599 info.si_errno = 0; 1600 info.si_code = TARGET_SEGV_MAPERR; 1601 break; 1602 } 1603 info._sifields._sigfault._addr = env->nip; 1604 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1605 break; 1606 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1607 /* XXX: check this */ 1608 switch (env->error_code & 0xFF000000) { 1609 case 0x40000000: 1610 info.si_signo = TARGET_SIGSEGV; 1611 info.si_errno = 0; 1612 info.si_code = TARGET_SEGV_MAPERR; 1613 break; 1614 case 0x10000000: 1615 case 0x08000000: 1616 info.si_signo = TARGET_SIGSEGV; 1617 info.si_errno = 0; 1618 info.si_code = TARGET_SEGV_ACCERR; 1619 break; 1620 default: 1621 /* Let's send a regular segfault... */ 1622 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1623 env->error_code); 1624 info.si_signo = TARGET_SIGSEGV; 1625 info.si_errno = 0; 1626 info.si_code = TARGET_SEGV_MAPERR; 1627 break; 1628 } 1629 info._sifields._sigfault._addr = env->nip - 4; 1630 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1631 break; 1632 case POWERPC_EXCP_EXTERNAL: /* External input */ 1633 cpu_abort(cs, "External interrupt while in user mode. " 1634 "Aborting\n"); 1635 break; 1636 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1637 /* XXX: check this */ 1638 info.si_signo = TARGET_SIGBUS; 1639 info.si_errno = 0; 1640 info.si_code = TARGET_BUS_ADRALN; 1641 info._sifields._sigfault._addr = env->nip; 1642 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1643 break; 1644 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1645 case POWERPC_EXCP_HV_EMU: /* HV emulation */ 1646 /* XXX: check this */ 1647 switch (env->error_code & ~0xF) { 1648 case POWERPC_EXCP_FP: 1649 info.si_signo = TARGET_SIGFPE; 1650 info.si_errno = 0; 1651 switch (env->error_code & 0xF) { 1652 case POWERPC_EXCP_FP_OX: 1653 info.si_code = TARGET_FPE_FLTOVF; 1654 break; 1655 case POWERPC_EXCP_FP_UX: 1656 info.si_code = TARGET_FPE_FLTUND; 1657 break; 1658 case POWERPC_EXCP_FP_ZX: 1659 case POWERPC_EXCP_FP_VXZDZ: 1660 info.si_code = TARGET_FPE_FLTDIV; 1661 break; 1662 case POWERPC_EXCP_FP_XX: 1663 info.si_code = TARGET_FPE_FLTRES; 1664 break; 1665 case POWERPC_EXCP_FP_VXSOFT: 1666 info.si_code = TARGET_FPE_FLTINV; 1667 break; 1668 case POWERPC_EXCP_FP_VXSNAN: 1669 case POWERPC_EXCP_FP_VXISI: 1670 case POWERPC_EXCP_FP_VXIDI: 1671 case POWERPC_EXCP_FP_VXIMZ: 1672 case POWERPC_EXCP_FP_VXVC: 1673 case POWERPC_EXCP_FP_VXSQRT: 1674 case POWERPC_EXCP_FP_VXCVI: 1675 info.si_code = TARGET_FPE_FLTSUB; 1676 break; 1677 default: 1678 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1679 env->error_code); 1680 break; 1681 } 1682 break; 1683 case POWERPC_EXCP_INVAL: 1684 info.si_signo = TARGET_SIGILL; 1685 info.si_errno = 0; 1686 switch (env->error_code & 0xF) { 1687 case POWERPC_EXCP_INVAL_INVAL: 1688 info.si_code = TARGET_ILL_ILLOPC; 1689 break; 1690 case POWERPC_EXCP_INVAL_LSWX: 1691 info.si_code = TARGET_ILL_ILLOPN; 1692 break; 1693 case POWERPC_EXCP_INVAL_SPR: 1694 info.si_code = TARGET_ILL_PRVREG; 1695 break; 1696 case POWERPC_EXCP_INVAL_FP: 1697 info.si_code = TARGET_ILL_COPROC; 1698 break; 1699 default: 1700 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1701 env->error_code & 0xF); 1702 info.si_code = TARGET_ILL_ILLADR; 1703 break; 1704 } 1705 break; 1706 case POWERPC_EXCP_PRIV: 1707 info.si_signo = TARGET_SIGILL; 1708 info.si_errno = 0; 1709 switch (env->error_code & 0xF) { 1710 case POWERPC_EXCP_PRIV_OPC: 1711 info.si_code = TARGET_ILL_PRVOPC; 1712 break; 1713 case POWERPC_EXCP_PRIV_REG: 1714 info.si_code = TARGET_ILL_PRVREG; 1715 break; 1716 default: 1717 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1718 env->error_code & 0xF); 1719 info.si_code = TARGET_ILL_PRVOPC; 1720 break; 1721 } 1722 break; 1723 case POWERPC_EXCP_TRAP: 1724 cpu_abort(cs, "Tried to call a TRAP\n"); 1725 break; 1726 default: 1727 /* Should not happen ! */ 1728 cpu_abort(cs, "Unknown program exception (%02x)\n", 1729 env->error_code); 1730 break; 1731 } 1732 info._sifields._sigfault._addr = env->nip; 1733 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1734 break; 1735 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1736 info.si_signo = TARGET_SIGILL; 1737 info.si_errno = 0; 1738 info.si_code = TARGET_ILL_COPROC; 1739 info._sifields._sigfault._addr = env->nip; 1740 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1741 break; 1742 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1743 cpu_abort(cs, "Syscall exception while in user mode. " 1744 "Aborting\n"); 1745 break; 1746 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1747 info.si_signo = TARGET_SIGILL; 1748 info.si_errno = 0; 1749 info.si_code = TARGET_ILL_COPROC; 1750 info._sifields._sigfault._addr = env->nip; 1751 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1752 break; 1753 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1754 cpu_abort(cs, "Decrementer interrupt while in user mode. " 1755 "Aborting\n"); 1756 break; 1757 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1758 cpu_abort(cs, "Fix interval timer interrupt while in user mode. " 1759 "Aborting\n"); 1760 break; 1761 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1762 cpu_abort(cs, "Watchdog timer interrupt while in user mode. " 1763 "Aborting\n"); 1764 break; 1765 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1766 cpu_abort(cs, "Data TLB exception while in user mode. " 1767 "Aborting\n"); 1768 break; 1769 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1770 cpu_abort(cs, "Instruction TLB exception while in user mode. " 1771 "Aborting\n"); 1772 break; 1773 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1774 info.si_signo = TARGET_SIGILL; 1775 info.si_errno = 0; 1776 info.si_code = TARGET_ILL_COPROC; 1777 info._sifields._sigfault._addr = env->nip; 1778 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1779 break; 1780 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1781 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); 1782 break; 1783 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1784 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); 1785 break; 1786 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1787 cpu_abort(cs, "Performance monitor exception not handled\n"); 1788 break; 1789 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1790 cpu_abort(cs, "Doorbell interrupt while in user mode. " 1791 "Aborting\n"); 1792 break; 1793 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1794 cpu_abort(cs, "Doorbell critical interrupt while in user mode. " 1795 "Aborting\n"); 1796 break; 1797 case POWERPC_EXCP_RESET: /* System reset exception */ 1798 cpu_abort(cs, "Reset interrupt while in user mode. " 1799 "Aborting\n"); 1800 break; 1801 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1802 cpu_abort(cs, "Data segment exception while in user mode. " 1803 "Aborting\n"); 1804 break; 1805 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1806 cpu_abort(cs, "Instruction segment exception " 1807 "while in user mode. Aborting\n"); 1808 break; 1809 /* PowerPC 64 with hypervisor mode support */ 1810 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1811 cpu_abort(cs, "Hypervisor decrementer interrupt " 1812 "while in user mode. Aborting\n"); 1813 break; 1814 case POWERPC_EXCP_TRACE: /* Trace exception */ 1815 /* Nothing to do: 1816 * we use this exception to emulate step-by-step execution mode. 1817 */ 1818 break; 1819 /* PowerPC 64 with hypervisor mode support */ 1820 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1821 cpu_abort(cs, "Hypervisor data storage exception " 1822 "while in user mode. Aborting\n"); 1823 break; 1824 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1825 cpu_abort(cs, "Hypervisor instruction storage exception " 1826 "while in user mode. Aborting\n"); 1827 break; 1828 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1829 cpu_abort(cs, "Hypervisor data segment exception " 1830 "while in user mode. Aborting\n"); 1831 break; 1832 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1833 cpu_abort(cs, "Hypervisor instruction segment exception " 1834 "while in user mode. Aborting\n"); 1835 break; 1836 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1837 info.si_signo = TARGET_SIGILL; 1838 info.si_errno = 0; 1839 info.si_code = TARGET_ILL_COPROC; 1840 info._sifields._sigfault._addr = env->nip; 1841 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1842 break; 1843 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1844 cpu_abort(cs, "Programmable interval timer interrupt " 1845 "while in user mode. Aborting\n"); 1846 break; 1847 case POWERPC_EXCP_IO: /* IO error exception */ 1848 cpu_abort(cs, "IO error exception while in user mode. " 1849 "Aborting\n"); 1850 break; 1851 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1852 cpu_abort(cs, "Run mode exception while in user mode. " 1853 "Aborting\n"); 1854 break; 1855 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1856 cpu_abort(cs, "Emulation trap exception not handled\n"); 1857 break; 1858 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1859 cpu_abort(cs, "Instruction fetch TLB exception " 1860 "while in user-mode. Aborting"); 1861 break; 1862 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1863 cpu_abort(cs, "Data load TLB exception while in user-mode. " 1864 "Aborting"); 1865 break; 1866 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1867 cpu_abort(cs, "Data store TLB exception while in user-mode. " 1868 "Aborting"); 1869 break; 1870 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1871 cpu_abort(cs, "Floating-point assist exception not handled\n"); 1872 break; 1873 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1874 cpu_abort(cs, "Instruction address breakpoint exception " 1875 "not handled\n"); 1876 break; 1877 case POWERPC_EXCP_SMI: /* System management interrupt */ 1878 cpu_abort(cs, "System management interrupt while in user mode. " 1879 "Aborting\n"); 1880 break; 1881 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1882 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " 1883 "Aborting\n"); 1884 break; 1885 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1886 cpu_abort(cs, "Performance monitor exception not handled\n"); 1887 break; 1888 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1889 cpu_abort(cs, "Vector assist exception not handled\n"); 1890 break; 1891 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1892 cpu_abort(cs, "Soft patch exception not handled\n"); 1893 break; 1894 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1895 cpu_abort(cs, "Maintenance exception while in user mode. " 1896 "Aborting\n"); 1897 break; 1898 case POWERPC_EXCP_STOP: /* stop translation */ 1899 /* We did invalidate the instruction cache. Go on */ 1900 break; 1901 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1902 /* We just stopped because of a branch. Go on */ 1903 break; 1904 case POWERPC_EXCP_SYSCALL_USER: 1905 /* system call in user-mode emulation */ 1906 /* WARNING: 1907 * PPC ABI uses overflow flag in cr0 to signal an error 1908 * in syscalls. 1909 */ 1910 env->crf[0] &= ~0x1; 1911 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1912 env->gpr[5], env->gpr[6], env->gpr[7], 1913 env->gpr[8], 0, 0); 1914 if (ret == -TARGET_ERESTARTSYS) { 1915 break; 1916 } 1917 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1918 /* Returning from a successful sigreturn syscall. 1919 Avoid corrupting register state. */ 1920 break; 1921 } 1922 env->nip += 4; 1923 if (ret > (target_ulong)(-515)) { 1924 env->crf[0] |= 0x1; 1925 ret = -ret; 1926 } 1927 env->gpr[3] = ret; 1928 break; 1929 case POWERPC_EXCP_STCX: 1930 if (do_store_exclusive(env)) { 1931 info.si_signo = TARGET_SIGSEGV; 1932 info.si_errno = 0; 1933 info.si_code = TARGET_SEGV_MAPERR; 1934 info._sifields._sigfault._addr = env->nip; 1935 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1936 } 1937 break; 1938 case EXCP_DEBUG: 1939 { 1940 int sig; 1941 1942 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1943 if (sig) { 1944 info.si_signo = sig; 1945 info.si_errno = 0; 1946 info.si_code = TARGET_TRAP_BRKPT; 1947 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1948 } 1949 } 1950 break; 1951 case EXCP_INTERRUPT: 1952 /* just indicate that signals should be handled asap */ 1953 break; 1954 default: 1955 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); 1956 break; 1957 } 1958 process_pending_signals(env); 1959 } 1960 } 1961 #endif 1962 1963 #ifdef TARGET_MIPS 1964 1965 # ifdef TARGET_ABI_MIPSO32 1966 # define MIPS_SYS(name, args) args, 1967 static const uint8_t mips_syscall_args[] = { 1968 MIPS_SYS(sys_syscall , 8) /* 4000 */ 1969 MIPS_SYS(sys_exit , 1) 1970 MIPS_SYS(sys_fork , 0) 1971 MIPS_SYS(sys_read , 3) 1972 MIPS_SYS(sys_write , 3) 1973 MIPS_SYS(sys_open , 3) /* 4005 */ 1974 MIPS_SYS(sys_close , 1) 1975 MIPS_SYS(sys_waitpid , 3) 1976 MIPS_SYS(sys_creat , 2) 1977 MIPS_SYS(sys_link , 2) 1978 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1979 MIPS_SYS(sys_execve , 0) 1980 MIPS_SYS(sys_chdir , 1) 1981 MIPS_SYS(sys_time , 1) 1982 MIPS_SYS(sys_mknod , 3) 1983 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1984 MIPS_SYS(sys_lchown , 3) 1985 MIPS_SYS(sys_ni_syscall , 0) 1986 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1987 MIPS_SYS(sys_lseek , 3) 1988 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1989 MIPS_SYS(sys_mount , 5) 1990 MIPS_SYS(sys_umount , 1) 1991 MIPS_SYS(sys_setuid , 1) 1992 MIPS_SYS(sys_getuid , 0) 1993 MIPS_SYS(sys_stime , 1) /* 4025 */ 1994 MIPS_SYS(sys_ptrace , 4) 1995 MIPS_SYS(sys_alarm , 1) 1996 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1997 MIPS_SYS(sys_pause , 0) 1998 MIPS_SYS(sys_utime , 2) /* 4030 */ 1999 MIPS_SYS(sys_ni_syscall , 0) 2000 MIPS_SYS(sys_ni_syscall , 0) 2001 MIPS_SYS(sys_access , 2) 2002 MIPS_SYS(sys_nice , 1) 2003 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 2004 MIPS_SYS(sys_sync , 0) 2005 MIPS_SYS(sys_kill , 2) 2006 MIPS_SYS(sys_rename , 2) 2007 MIPS_SYS(sys_mkdir , 2) 2008 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 2009 MIPS_SYS(sys_dup , 1) 2010 MIPS_SYS(sys_pipe , 0) 2011 MIPS_SYS(sys_times , 1) 2012 MIPS_SYS(sys_ni_syscall , 0) 2013 MIPS_SYS(sys_brk , 1) /* 4045 */ 2014 MIPS_SYS(sys_setgid , 1) 2015 MIPS_SYS(sys_getgid , 0) 2016 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 2017 MIPS_SYS(sys_geteuid , 0) 2018 MIPS_SYS(sys_getegid , 0) /* 4050 */ 2019 MIPS_SYS(sys_acct , 0) 2020 MIPS_SYS(sys_umount2 , 2) 2021 MIPS_SYS(sys_ni_syscall , 0) 2022 MIPS_SYS(sys_ioctl , 3) 2023 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 2024 MIPS_SYS(sys_ni_syscall , 2) 2025 MIPS_SYS(sys_setpgid , 2) 2026 MIPS_SYS(sys_ni_syscall , 0) 2027 MIPS_SYS(sys_olduname , 1) 2028 MIPS_SYS(sys_umask , 1) /* 4060 */ 2029 MIPS_SYS(sys_chroot , 1) 2030 MIPS_SYS(sys_ustat , 2) 2031 MIPS_SYS(sys_dup2 , 2) 2032 MIPS_SYS(sys_getppid , 0) 2033 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 2034 MIPS_SYS(sys_setsid , 0) 2035 MIPS_SYS(sys_sigaction , 3) 2036 MIPS_SYS(sys_sgetmask , 0) 2037 MIPS_SYS(sys_ssetmask , 1) 2038 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 2039 MIPS_SYS(sys_setregid , 2) 2040 MIPS_SYS(sys_sigsuspend , 0) 2041 MIPS_SYS(sys_sigpending , 1) 2042 MIPS_SYS(sys_sethostname , 2) 2043 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 2044 MIPS_SYS(sys_getrlimit , 2) 2045 MIPS_SYS(sys_getrusage , 2) 2046 MIPS_SYS(sys_gettimeofday, 2) 2047 MIPS_SYS(sys_settimeofday, 2) 2048 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 2049 MIPS_SYS(sys_setgroups , 2) 2050 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 2051 MIPS_SYS(sys_symlink , 2) 2052 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 2053 MIPS_SYS(sys_readlink , 3) /* 4085 */ 2054 MIPS_SYS(sys_uselib , 1) 2055 MIPS_SYS(sys_swapon , 2) 2056 MIPS_SYS(sys_reboot , 3) 2057 MIPS_SYS(old_readdir , 3) 2058 MIPS_SYS(old_mmap , 6) /* 4090 */ 2059 MIPS_SYS(sys_munmap , 2) 2060 MIPS_SYS(sys_truncate , 2) 2061 MIPS_SYS(sys_ftruncate , 2) 2062 MIPS_SYS(sys_fchmod , 2) 2063 MIPS_SYS(sys_fchown , 3) /* 4095 */ 2064 MIPS_SYS(sys_getpriority , 2) 2065 MIPS_SYS(sys_setpriority , 3) 2066 MIPS_SYS(sys_ni_syscall , 0) 2067 MIPS_SYS(sys_statfs , 2) 2068 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 2069 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 2070 MIPS_SYS(sys_socketcall , 2) 2071 MIPS_SYS(sys_syslog , 3) 2072 MIPS_SYS(sys_setitimer , 3) 2073 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 2074 MIPS_SYS(sys_newstat , 2) 2075 MIPS_SYS(sys_newlstat , 2) 2076 MIPS_SYS(sys_newfstat , 2) 2077 MIPS_SYS(sys_uname , 1) 2078 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 2079 MIPS_SYS(sys_vhangup , 0) 2080 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 2081 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 2082 MIPS_SYS(sys_wait4 , 4) 2083 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 2084 MIPS_SYS(sys_sysinfo , 1) 2085 MIPS_SYS(sys_ipc , 6) 2086 MIPS_SYS(sys_fsync , 1) 2087 MIPS_SYS(sys_sigreturn , 0) 2088 MIPS_SYS(sys_clone , 6) /* 4120 */ 2089 MIPS_SYS(sys_setdomainname, 2) 2090 MIPS_SYS(sys_newuname , 1) 2091 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 2092 MIPS_SYS(sys_adjtimex , 1) 2093 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 2094 MIPS_SYS(sys_sigprocmask , 3) 2095 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 2096 MIPS_SYS(sys_init_module , 5) 2097 MIPS_SYS(sys_delete_module, 1) 2098 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 2099 MIPS_SYS(sys_quotactl , 0) 2100 MIPS_SYS(sys_getpgid , 1) 2101 MIPS_SYS(sys_fchdir , 1) 2102 MIPS_SYS(sys_bdflush , 2) 2103 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 2104 MIPS_SYS(sys_personality , 1) 2105 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 2106 MIPS_SYS(sys_setfsuid , 1) 2107 MIPS_SYS(sys_setfsgid , 1) 2108 MIPS_SYS(sys_llseek , 5) /* 4140 */ 2109 MIPS_SYS(sys_getdents , 3) 2110 MIPS_SYS(sys_select , 5) 2111 MIPS_SYS(sys_flock , 2) 2112 MIPS_SYS(sys_msync , 3) 2113 MIPS_SYS(sys_readv , 3) /* 4145 */ 2114 MIPS_SYS(sys_writev , 3) 2115 MIPS_SYS(sys_cacheflush , 3) 2116 MIPS_SYS(sys_cachectl , 3) 2117 MIPS_SYS(sys_sysmips , 4) 2118 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 2119 MIPS_SYS(sys_getsid , 1) 2120 MIPS_SYS(sys_fdatasync , 0) 2121 MIPS_SYS(sys_sysctl , 1) 2122 MIPS_SYS(sys_mlock , 2) 2123 MIPS_SYS(sys_munlock , 2) /* 4155 */ 2124 MIPS_SYS(sys_mlockall , 1) 2125 MIPS_SYS(sys_munlockall , 0) 2126 MIPS_SYS(sys_sched_setparam, 2) 2127 MIPS_SYS(sys_sched_getparam, 2) 2128 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 2129 MIPS_SYS(sys_sched_getscheduler, 1) 2130 MIPS_SYS(sys_sched_yield , 0) 2131 MIPS_SYS(sys_sched_get_priority_max, 1) 2132 MIPS_SYS(sys_sched_get_priority_min, 1) 2133 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 2134 MIPS_SYS(sys_nanosleep, 2) 2135 MIPS_SYS(sys_mremap , 5) 2136 MIPS_SYS(sys_accept , 3) 2137 MIPS_SYS(sys_bind , 3) 2138 MIPS_SYS(sys_connect , 3) /* 4170 */ 2139 MIPS_SYS(sys_getpeername , 3) 2140 MIPS_SYS(sys_getsockname , 3) 2141 MIPS_SYS(sys_getsockopt , 5) 2142 MIPS_SYS(sys_listen , 2) 2143 MIPS_SYS(sys_recv , 4) /* 4175 */ 2144 MIPS_SYS(sys_recvfrom , 6) 2145 MIPS_SYS(sys_recvmsg , 3) 2146 MIPS_SYS(sys_send , 4) 2147 MIPS_SYS(sys_sendmsg , 3) 2148 MIPS_SYS(sys_sendto , 6) /* 4180 */ 2149 MIPS_SYS(sys_setsockopt , 5) 2150 MIPS_SYS(sys_shutdown , 2) 2151 MIPS_SYS(sys_socket , 3) 2152 MIPS_SYS(sys_socketpair , 4) 2153 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 2154 MIPS_SYS(sys_getresuid , 3) 2155 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 2156 MIPS_SYS(sys_poll , 3) 2157 MIPS_SYS(sys_nfsservctl , 3) 2158 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 2159 MIPS_SYS(sys_getresgid , 3) 2160 MIPS_SYS(sys_prctl , 5) 2161 MIPS_SYS(sys_rt_sigreturn, 0) 2162 MIPS_SYS(sys_rt_sigaction, 4) 2163 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 2164 MIPS_SYS(sys_rt_sigpending, 2) 2165 MIPS_SYS(sys_rt_sigtimedwait, 4) 2166 MIPS_SYS(sys_rt_sigqueueinfo, 3) 2167 MIPS_SYS(sys_rt_sigsuspend, 0) 2168 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 2169 MIPS_SYS(sys_pwrite64 , 6) 2170 MIPS_SYS(sys_chown , 3) 2171 MIPS_SYS(sys_getcwd , 2) 2172 MIPS_SYS(sys_capget , 2) 2173 MIPS_SYS(sys_capset , 2) /* 4205 */ 2174 MIPS_SYS(sys_sigaltstack , 2) 2175 MIPS_SYS(sys_sendfile , 4) 2176 MIPS_SYS(sys_ni_syscall , 0) 2177 MIPS_SYS(sys_ni_syscall , 0) 2178 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2179 MIPS_SYS(sys_truncate64 , 4) 2180 MIPS_SYS(sys_ftruncate64 , 4) 2181 MIPS_SYS(sys_stat64 , 2) 2182 MIPS_SYS(sys_lstat64 , 2) 2183 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2184 MIPS_SYS(sys_pivot_root , 2) 2185 MIPS_SYS(sys_mincore , 3) 2186 MIPS_SYS(sys_madvise , 3) 2187 MIPS_SYS(sys_getdents64 , 3) 2188 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2189 MIPS_SYS(sys_ni_syscall , 0) 2190 MIPS_SYS(sys_gettid , 0) 2191 MIPS_SYS(sys_readahead , 5) 2192 MIPS_SYS(sys_setxattr , 5) 2193 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2194 MIPS_SYS(sys_fsetxattr , 5) 2195 MIPS_SYS(sys_getxattr , 4) 2196 MIPS_SYS(sys_lgetxattr , 4) 2197 MIPS_SYS(sys_fgetxattr , 4) 2198 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2199 MIPS_SYS(sys_llistxattr , 3) 2200 MIPS_SYS(sys_flistxattr , 3) 2201 MIPS_SYS(sys_removexattr , 2) 2202 MIPS_SYS(sys_lremovexattr, 2) 2203 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2204 MIPS_SYS(sys_tkill , 2) 2205 MIPS_SYS(sys_sendfile64 , 5) 2206 MIPS_SYS(sys_futex , 6) 2207 MIPS_SYS(sys_sched_setaffinity, 3) 2208 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2209 MIPS_SYS(sys_io_setup , 2) 2210 MIPS_SYS(sys_io_destroy , 1) 2211 MIPS_SYS(sys_io_getevents, 5) 2212 MIPS_SYS(sys_io_submit , 3) 2213 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2214 MIPS_SYS(sys_exit_group , 1) 2215 MIPS_SYS(sys_lookup_dcookie, 3) 2216 MIPS_SYS(sys_epoll_create, 1) 2217 MIPS_SYS(sys_epoll_ctl , 4) 2218 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2219 MIPS_SYS(sys_remap_file_pages, 5) 2220 MIPS_SYS(sys_set_tid_address, 1) 2221 MIPS_SYS(sys_restart_syscall, 0) 2222 MIPS_SYS(sys_fadvise64_64, 7) 2223 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2224 MIPS_SYS(sys_fstatfs64 , 2) 2225 MIPS_SYS(sys_timer_create, 3) 2226 MIPS_SYS(sys_timer_settime, 4) 2227 MIPS_SYS(sys_timer_gettime, 2) 2228 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2229 MIPS_SYS(sys_timer_delete, 1) 2230 MIPS_SYS(sys_clock_settime, 2) 2231 MIPS_SYS(sys_clock_gettime, 2) 2232 MIPS_SYS(sys_clock_getres, 2) 2233 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2234 MIPS_SYS(sys_tgkill , 3) 2235 MIPS_SYS(sys_utimes , 2) 2236 MIPS_SYS(sys_mbind , 4) 2237 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2238 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2239 MIPS_SYS(sys_mq_open , 4) 2240 MIPS_SYS(sys_mq_unlink , 1) 2241 MIPS_SYS(sys_mq_timedsend, 5) 2242 MIPS_SYS(sys_mq_timedreceive, 5) 2243 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2244 MIPS_SYS(sys_mq_getsetattr, 3) 2245 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2246 MIPS_SYS(sys_waitid , 4) 2247 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2248 MIPS_SYS(sys_add_key , 5) 2249 MIPS_SYS(sys_request_key, 4) 2250 MIPS_SYS(sys_keyctl , 5) 2251 MIPS_SYS(sys_set_thread_area, 1) 2252 MIPS_SYS(sys_inotify_init, 0) 2253 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2254 MIPS_SYS(sys_inotify_rm_watch, 2) 2255 MIPS_SYS(sys_migrate_pages, 4) 2256 MIPS_SYS(sys_openat, 4) 2257 MIPS_SYS(sys_mkdirat, 3) 2258 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2259 MIPS_SYS(sys_fchownat, 5) 2260 MIPS_SYS(sys_futimesat, 3) 2261 MIPS_SYS(sys_fstatat64, 4) 2262 MIPS_SYS(sys_unlinkat, 3) 2263 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2264 MIPS_SYS(sys_linkat, 5) 2265 MIPS_SYS(sys_symlinkat, 3) 2266 MIPS_SYS(sys_readlinkat, 4) 2267 MIPS_SYS(sys_fchmodat, 3) 2268 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2269 MIPS_SYS(sys_pselect6, 6) 2270 MIPS_SYS(sys_ppoll, 5) 2271 MIPS_SYS(sys_unshare, 1) 2272 MIPS_SYS(sys_splice, 6) 2273 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2274 MIPS_SYS(sys_tee, 4) 2275 MIPS_SYS(sys_vmsplice, 4) 2276 MIPS_SYS(sys_move_pages, 6) 2277 MIPS_SYS(sys_set_robust_list, 2) 2278 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2279 MIPS_SYS(sys_kexec_load, 4) 2280 MIPS_SYS(sys_getcpu, 3) 2281 MIPS_SYS(sys_epoll_pwait, 6) 2282 MIPS_SYS(sys_ioprio_set, 3) 2283 MIPS_SYS(sys_ioprio_get, 2) 2284 MIPS_SYS(sys_utimensat, 4) 2285 MIPS_SYS(sys_signalfd, 3) 2286 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2287 MIPS_SYS(sys_eventfd, 1) 2288 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2289 MIPS_SYS(sys_timerfd_create, 2) 2290 MIPS_SYS(sys_timerfd_gettime, 2) 2291 MIPS_SYS(sys_timerfd_settime, 4) 2292 MIPS_SYS(sys_signalfd4, 4) 2293 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2294 MIPS_SYS(sys_epoll_create1, 1) 2295 MIPS_SYS(sys_dup3, 3) 2296 MIPS_SYS(sys_pipe2, 2) 2297 MIPS_SYS(sys_inotify_init1, 1) 2298 MIPS_SYS(sys_preadv, 6) /* 4330 */ 2299 MIPS_SYS(sys_pwritev, 6) 2300 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2301 MIPS_SYS(sys_perf_event_open, 5) 2302 MIPS_SYS(sys_accept4, 4) 2303 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2304 MIPS_SYS(sys_fanotify_init, 2) 2305 MIPS_SYS(sys_fanotify_mark, 6) 2306 MIPS_SYS(sys_prlimit64, 4) 2307 MIPS_SYS(sys_name_to_handle_at, 5) 2308 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2309 MIPS_SYS(sys_clock_adjtime, 2) 2310 MIPS_SYS(sys_syncfs, 1) 2311 }; 2312 # undef MIPS_SYS 2313 # endif /* O32 */ 2314 2315 static int do_store_exclusive(CPUMIPSState *env) 2316 { 2317 target_ulong addr; 2318 target_ulong page_addr; 2319 target_ulong val; 2320 int flags; 2321 int segv = 0; 2322 int reg; 2323 int d; 2324 2325 addr = env->lladdr; 2326 page_addr = addr & TARGET_PAGE_MASK; 2327 start_exclusive(); 2328 mmap_lock(); 2329 flags = page_get_flags(page_addr); 2330 if ((flags & PAGE_READ) == 0) { 2331 segv = 1; 2332 } else { 2333 reg = env->llreg & 0x1f; 2334 d = (env->llreg & 0x20) != 0; 2335 if (d) { 2336 segv = get_user_s64(val, addr); 2337 } else { 2338 segv = get_user_s32(val, addr); 2339 } 2340 if (!segv) { 2341 if (val != env->llval) { 2342 env->active_tc.gpr[reg] = 0; 2343 } else { 2344 if (d) { 2345 segv = put_user_u64(env->llnewval, addr); 2346 } else { 2347 segv = put_user_u32(env->llnewval, addr); 2348 } 2349 if (!segv) { 2350 env->active_tc.gpr[reg] = 1; 2351 } 2352 } 2353 } 2354 } 2355 env->lladdr = -1; 2356 if (!segv) { 2357 env->active_tc.PC += 4; 2358 } 2359 mmap_unlock(); 2360 end_exclusive(); 2361 return segv; 2362 } 2363 2364 /* Break codes */ 2365 enum { 2366 BRK_OVERFLOW = 6, 2367 BRK_DIVZERO = 7 2368 }; 2369 2370 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2371 unsigned int code) 2372 { 2373 int ret = -1; 2374 2375 switch (code) { 2376 case BRK_OVERFLOW: 2377 case BRK_DIVZERO: 2378 info->si_signo = TARGET_SIGFPE; 2379 info->si_errno = 0; 2380 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2381 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 2382 ret = 0; 2383 break; 2384 default: 2385 info->si_signo = TARGET_SIGTRAP; 2386 info->si_errno = 0; 2387 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 2388 ret = 0; 2389 break; 2390 } 2391 2392 return ret; 2393 } 2394 2395 void cpu_loop(CPUMIPSState *env) 2396 { 2397 CPUState *cs = CPU(mips_env_get_cpu(env)); 2398 target_siginfo_t info; 2399 int trapnr; 2400 abi_long ret; 2401 # ifdef TARGET_ABI_MIPSO32 2402 unsigned int syscall_num; 2403 # endif 2404 2405 for(;;) { 2406 cpu_exec_start(cs); 2407 trapnr = cpu_exec(cs); 2408 cpu_exec_end(cs); 2409 process_queued_cpu_work(cs); 2410 2411 switch(trapnr) { 2412 case EXCP_SYSCALL: 2413 env->active_tc.PC += 4; 2414 # ifdef TARGET_ABI_MIPSO32 2415 syscall_num = env->active_tc.gpr[2] - 4000; 2416 if (syscall_num >= sizeof(mips_syscall_args)) { 2417 ret = -TARGET_ENOSYS; 2418 } else { 2419 int nb_args; 2420 abi_ulong sp_reg; 2421 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2422 2423 nb_args = mips_syscall_args[syscall_num]; 2424 sp_reg = env->active_tc.gpr[29]; 2425 switch (nb_args) { 2426 /* these arguments are taken from the stack */ 2427 case 8: 2428 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2429 goto done_syscall; 2430 } 2431 case 7: 2432 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2433 goto done_syscall; 2434 } 2435 case 6: 2436 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2437 goto done_syscall; 2438 } 2439 case 5: 2440 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2441 goto done_syscall; 2442 } 2443 default: 2444 break; 2445 } 2446 ret = do_syscall(env, env->active_tc.gpr[2], 2447 env->active_tc.gpr[4], 2448 env->active_tc.gpr[5], 2449 env->active_tc.gpr[6], 2450 env->active_tc.gpr[7], 2451 arg5, arg6, arg7, arg8); 2452 } 2453 done_syscall: 2454 # else 2455 ret = do_syscall(env, env->active_tc.gpr[2], 2456 env->active_tc.gpr[4], env->active_tc.gpr[5], 2457 env->active_tc.gpr[6], env->active_tc.gpr[7], 2458 env->active_tc.gpr[8], env->active_tc.gpr[9], 2459 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2460 # endif /* O32 */ 2461 if (ret == -TARGET_ERESTARTSYS) { 2462 env->active_tc.PC -= 4; 2463 break; 2464 } 2465 if (ret == -TARGET_QEMU_ESIGRETURN) { 2466 /* Returning from a successful sigreturn syscall. 2467 Avoid clobbering register state. */ 2468 break; 2469 } 2470 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2471 env->active_tc.gpr[7] = 1; /* error flag */ 2472 ret = -ret; 2473 } else { 2474 env->active_tc.gpr[7] = 0; /* error flag */ 2475 } 2476 env->active_tc.gpr[2] = ret; 2477 break; 2478 case EXCP_TLBL: 2479 case EXCP_TLBS: 2480 case EXCP_AdEL: 2481 case EXCP_AdES: 2482 info.si_signo = TARGET_SIGSEGV; 2483 info.si_errno = 0; 2484 /* XXX: check env->error_code */ 2485 info.si_code = TARGET_SEGV_MAPERR; 2486 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2487 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2488 break; 2489 case EXCP_CpU: 2490 case EXCP_RI: 2491 info.si_signo = TARGET_SIGILL; 2492 info.si_errno = 0; 2493 info.si_code = 0; 2494 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2495 break; 2496 case EXCP_INTERRUPT: 2497 /* just indicate that signals should be handled asap */ 2498 break; 2499 case EXCP_DEBUG: 2500 { 2501 int sig; 2502 2503 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2504 if (sig) 2505 { 2506 info.si_signo = sig; 2507 info.si_errno = 0; 2508 info.si_code = TARGET_TRAP_BRKPT; 2509 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2510 } 2511 } 2512 break; 2513 case EXCP_SC: 2514 if (do_store_exclusive(env)) { 2515 info.si_signo = TARGET_SIGSEGV; 2516 info.si_errno = 0; 2517 info.si_code = TARGET_SEGV_MAPERR; 2518 info._sifields._sigfault._addr = env->active_tc.PC; 2519 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2520 } 2521 break; 2522 case EXCP_DSPDIS: 2523 info.si_signo = TARGET_SIGILL; 2524 info.si_errno = 0; 2525 info.si_code = TARGET_ILL_ILLOPC; 2526 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2527 break; 2528 /* The code below was inspired by the MIPS Linux kernel trap 2529 * handling code in arch/mips/kernel/traps.c. 2530 */ 2531 case EXCP_BREAK: 2532 { 2533 abi_ulong trap_instr; 2534 unsigned int code; 2535 2536 if (env->hflags & MIPS_HFLAG_M16) { 2537 if (env->insn_flags & ASE_MICROMIPS) { 2538 /* microMIPS mode */ 2539 ret = get_user_u16(trap_instr, env->active_tc.PC); 2540 if (ret != 0) { 2541 goto error; 2542 } 2543 2544 if ((trap_instr >> 10) == 0x11) { 2545 /* 16-bit instruction */ 2546 code = trap_instr & 0xf; 2547 } else { 2548 /* 32-bit instruction */ 2549 abi_ulong instr_lo; 2550 2551 ret = get_user_u16(instr_lo, 2552 env->active_tc.PC + 2); 2553 if (ret != 0) { 2554 goto error; 2555 } 2556 trap_instr = (trap_instr << 16) | instr_lo; 2557 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2558 /* Unfortunately, microMIPS also suffers from 2559 the old assembler bug... */ 2560 if (code >= (1 << 10)) { 2561 code >>= 10; 2562 } 2563 } 2564 } else { 2565 /* MIPS16e mode */ 2566 ret = get_user_u16(trap_instr, env->active_tc.PC); 2567 if (ret != 0) { 2568 goto error; 2569 } 2570 code = (trap_instr >> 6) & 0x3f; 2571 } 2572 } else { 2573 ret = get_user_u32(trap_instr, env->active_tc.PC); 2574 if (ret != 0) { 2575 goto error; 2576 } 2577 2578 /* As described in the original Linux kernel code, the 2579 * below checks on 'code' are to work around an old 2580 * assembly bug. 2581 */ 2582 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2583 if (code >= (1 << 10)) { 2584 code >>= 10; 2585 } 2586 } 2587 2588 if (do_break(env, &info, code) != 0) { 2589 goto error; 2590 } 2591 } 2592 break; 2593 case EXCP_TRAP: 2594 { 2595 abi_ulong trap_instr; 2596 unsigned int code = 0; 2597 2598 if (env->hflags & MIPS_HFLAG_M16) { 2599 /* microMIPS mode */ 2600 abi_ulong instr[2]; 2601 2602 ret = get_user_u16(instr[0], env->active_tc.PC) || 2603 get_user_u16(instr[1], env->active_tc.PC + 2); 2604 2605 trap_instr = (instr[0] << 16) | instr[1]; 2606 } else { 2607 ret = get_user_u32(trap_instr, env->active_tc.PC); 2608 } 2609 2610 if (ret != 0) { 2611 goto error; 2612 } 2613 2614 /* The immediate versions don't provide a code. */ 2615 if (!(trap_instr & 0xFC000000)) { 2616 if (env->hflags & MIPS_HFLAG_M16) { 2617 /* microMIPS mode */ 2618 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 2619 } else { 2620 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2621 } 2622 } 2623 2624 if (do_break(env, &info, code) != 0) { 2625 goto error; 2626 } 2627 } 2628 break; 2629 default: 2630 error: 2631 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 2632 abort(); 2633 } 2634 process_pending_signals(env); 2635 } 2636 } 2637 #endif 2638 2639 #ifdef TARGET_OPENRISC 2640 2641 void cpu_loop(CPUOpenRISCState *env) 2642 { 2643 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2644 int trapnr, gdbsig; 2645 abi_long ret; 2646 2647 for (;;) { 2648 cpu_exec_start(cs); 2649 trapnr = cpu_exec(cs); 2650 cpu_exec_end(cs); 2651 process_queued_cpu_work(cs); 2652 gdbsig = 0; 2653 2654 switch (trapnr) { 2655 case EXCP_RESET: 2656 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc); 2657 exit(EXIT_FAILURE); 2658 break; 2659 case EXCP_BUSERR: 2660 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc); 2661 gdbsig = TARGET_SIGBUS; 2662 break; 2663 case EXCP_DPF: 2664 case EXCP_IPF: 2665 cpu_dump_state(cs, stderr, fprintf, 0); 2666 gdbsig = TARGET_SIGSEGV; 2667 break; 2668 case EXCP_TICK: 2669 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc); 2670 break; 2671 case EXCP_ALIGN: 2672 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc); 2673 gdbsig = TARGET_SIGBUS; 2674 break; 2675 case EXCP_ILLEGAL: 2676 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc); 2677 gdbsig = TARGET_SIGILL; 2678 break; 2679 case EXCP_INT: 2680 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc); 2681 break; 2682 case EXCP_DTLBMISS: 2683 case EXCP_ITLBMISS: 2684 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n"); 2685 break; 2686 case EXCP_RANGE: 2687 qemu_log_mask(CPU_LOG_INT, "\nRange\n"); 2688 gdbsig = TARGET_SIGSEGV; 2689 break; 2690 case EXCP_SYSCALL: 2691 env->pc += 4; /* 0xc00; */ 2692 ret = do_syscall(env, 2693 env->gpr[11], /* return value */ 2694 env->gpr[3], /* r3 - r7 are params */ 2695 env->gpr[4], 2696 env->gpr[5], 2697 env->gpr[6], 2698 env->gpr[7], 2699 env->gpr[8], 0, 0); 2700 if (ret == -TARGET_ERESTARTSYS) { 2701 env->pc -= 4; 2702 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2703 env->gpr[11] = ret; 2704 } 2705 break; 2706 case EXCP_FPE: 2707 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n"); 2708 break; 2709 case EXCP_TRAP: 2710 qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); 2711 gdbsig = TARGET_SIGTRAP; 2712 break; 2713 case EXCP_NR: 2714 qemu_log_mask(CPU_LOG_INT, "\nNR\n"); 2715 break; 2716 default: 2717 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 2718 trapnr); 2719 gdbsig = TARGET_SIGILL; 2720 break; 2721 } 2722 if (gdbsig) { 2723 gdb_handlesig(cs, gdbsig); 2724 if (gdbsig != TARGET_SIGTRAP) { 2725 exit(EXIT_FAILURE); 2726 } 2727 } 2728 2729 process_pending_signals(env); 2730 } 2731 } 2732 2733 #endif /* TARGET_OPENRISC */ 2734 2735 #ifdef TARGET_SH4 2736 void cpu_loop(CPUSH4State *env) 2737 { 2738 CPUState *cs = CPU(sh_env_get_cpu(env)); 2739 int trapnr, ret; 2740 target_siginfo_t info; 2741 2742 while (1) { 2743 cpu_exec_start(cs); 2744 trapnr = cpu_exec(cs); 2745 cpu_exec_end(cs); 2746 process_queued_cpu_work(cs); 2747 2748 switch (trapnr) { 2749 case 0x160: 2750 env->pc += 2; 2751 ret = do_syscall(env, 2752 env->gregs[3], 2753 env->gregs[4], 2754 env->gregs[5], 2755 env->gregs[6], 2756 env->gregs[7], 2757 env->gregs[0], 2758 env->gregs[1], 2759 0, 0); 2760 if (ret == -TARGET_ERESTARTSYS) { 2761 env->pc -= 2; 2762 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2763 env->gregs[0] = ret; 2764 } 2765 break; 2766 case EXCP_INTERRUPT: 2767 /* just indicate that signals should be handled asap */ 2768 break; 2769 case EXCP_DEBUG: 2770 { 2771 int sig; 2772 2773 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2774 if (sig) 2775 { 2776 info.si_signo = sig; 2777 info.si_errno = 0; 2778 info.si_code = TARGET_TRAP_BRKPT; 2779 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2780 } 2781 } 2782 break; 2783 case 0xa0: 2784 case 0xc0: 2785 info.si_signo = TARGET_SIGSEGV; 2786 info.si_errno = 0; 2787 info.si_code = TARGET_SEGV_MAPERR; 2788 info._sifields._sigfault._addr = env->tea; 2789 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2790 break; 2791 2792 default: 2793 printf ("Unhandled trap: 0x%x\n", trapnr); 2794 cpu_dump_state(cs, stderr, fprintf, 0); 2795 exit(EXIT_FAILURE); 2796 } 2797 process_pending_signals (env); 2798 } 2799 } 2800 #endif 2801 2802 #ifdef TARGET_CRIS 2803 void cpu_loop(CPUCRISState *env) 2804 { 2805 CPUState *cs = CPU(cris_env_get_cpu(env)); 2806 int trapnr, ret; 2807 target_siginfo_t info; 2808 2809 while (1) { 2810 cpu_exec_start(cs); 2811 trapnr = cpu_exec(cs); 2812 cpu_exec_end(cs); 2813 process_queued_cpu_work(cs); 2814 2815 switch (trapnr) { 2816 case 0xaa: 2817 { 2818 info.si_signo = TARGET_SIGSEGV; 2819 info.si_errno = 0; 2820 /* XXX: check env->error_code */ 2821 info.si_code = TARGET_SEGV_MAPERR; 2822 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2823 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2824 } 2825 break; 2826 case EXCP_INTERRUPT: 2827 /* just indicate that signals should be handled asap */ 2828 break; 2829 case EXCP_BREAK: 2830 ret = do_syscall(env, 2831 env->regs[9], 2832 env->regs[10], 2833 env->regs[11], 2834 env->regs[12], 2835 env->regs[13], 2836 env->pregs[7], 2837 env->pregs[11], 2838 0, 0); 2839 if (ret == -TARGET_ERESTARTSYS) { 2840 env->pc -= 2; 2841 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2842 env->regs[10] = ret; 2843 } 2844 break; 2845 case EXCP_DEBUG: 2846 { 2847 int sig; 2848 2849 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2850 if (sig) 2851 { 2852 info.si_signo = sig; 2853 info.si_errno = 0; 2854 info.si_code = TARGET_TRAP_BRKPT; 2855 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2856 } 2857 } 2858 break; 2859 default: 2860 printf ("Unhandled trap: 0x%x\n", trapnr); 2861 cpu_dump_state(cs, stderr, fprintf, 0); 2862 exit(EXIT_FAILURE); 2863 } 2864 process_pending_signals (env); 2865 } 2866 } 2867 #endif 2868 2869 #ifdef TARGET_MICROBLAZE 2870 void cpu_loop(CPUMBState *env) 2871 { 2872 CPUState *cs = CPU(mb_env_get_cpu(env)); 2873 int trapnr, ret; 2874 target_siginfo_t info; 2875 2876 while (1) { 2877 cpu_exec_start(cs); 2878 trapnr = cpu_exec(cs); 2879 cpu_exec_end(cs); 2880 process_queued_cpu_work(cs); 2881 2882 switch (trapnr) { 2883 case 0xaa: 2884 { 2885 info.si_signo = TARGET_SIGSEGV; 2886 info.si_errno = 0; 2887 /* XXX: check env->error_code */ 2888 info.si_code = TARGET_SEGV_MAPERR; 2889 info._sifields._sigfault._addr = 0; 2890 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2891 } 2892 break; 2893 case EXCP_INTERRUPT: 2894 /* just indicate that signals should be handled asap */ 2895 break; 2896 case EXCP_BREAK: 2897 /* Return address is 4 bytes after the call. */ 2898 env->regs[14] += 4; 2899 env->sregs[SR_PC] = env->regs[14]; 2900 ret = do_syscall(env, 2901 env->regs[12], 2902 env->regs[5], 2903 env->regs[6], 2904 env->regs[7], 2905 env->regs[8], 2906 env->regs[9], 2907 env->regs[10], 2908 0, 0); 2909 if (ret == -TARGET_ERESTARTSYS) { 2910 /* Wind back to before the syscall. */ 2911 env->sregs[SR_PC] -= 4; 2912 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2913 env->regs[3] = ret; 2914 } 2915 /* All syscall exits result in guest r14 being equal to the 2916 * PC we return to, because the kernel syscall exit "rtbd" does 2917 * this. (This is true even for sigreturn(); note that r14 is 2918 * not a userspace-usable register, as the kernel may clobber it 2919 * at any point.) 2920 */ 2921 env->regs[14] = env->sregs[SR_PC]; 2922 break; 2923 case EXCP_HW_EXCP: 2924 env->regs[17] = env->sregs[SR_PC] + 4; 2925 if (env->iflags & D_FLAG) { 2926 env->sregs[SR_ESR] |= 1 << 12; 2927 env->sregs[SR_PC] -= 4; 2928 /* FIXME: if branch was immed, replay the imm as well. */ 2929 } 2930 2931 env->iflags &= ~(IMM_FLAG | D_FLAG); 2932 2933 switch (env->sregs[SR_ESR] & 31) { 2934 case ESR_EC_DIVZERO: 2935 info.si_signo = TARGET_SIGFPE; 2936 info.si_errno = 0; 2937 info.si_code = TARGET_FPE_FLTDIV; 2938 info._sifields._sigfault._addr = 0; 2939 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2940 break; 2941 case ESR_EC_FPU: 2942 info.si_signo = TARGET_SIGFPE; 2943 info.si_errno = 0; 2944 if (env->sregs[SR_FSR] & FSR_IO) { 2945 info.si_code = TARGET_FPE_FLTINV; 2946 } 2947 if (env->sregs[SR_FSR] & FSR_DZ) { 2948 info.si_code = TARGET_FPE_FLTDIV; 2949 } 2950 info._sifields._sigfault._addr = 0; 2951 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2952 break; 2953 default: 2954 printf ("Unhandled hw-exception: 0x%x\n", 2955 env->sregs[SR_ESR] & ESR_EC_MASK); 2956 cpu_dump_state(cs, stderr, fprintf, 0); 2957 exit(EXIT_FAILURE); 2958 break; 2959 } 2960 break; 2961 case EXCP_DEBUG: 2962 { 2963 int sig; 2964 2965 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2966 if (sig) 2967 { 2968 info.si_signo = sig; 2969 info.si_errno = 0; 2970 info.si_code = TARGET_TRAP_BRKPT; 2971 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2972 } 2973 } 2974 break; 2975 default: 2976 printf ("Unhandled trap: 0x%x\n", trapnr); 2977 cpu_dump_state(cs, stderr, fprintf, 0); 2978 exit(EXIT_FAILURE); 2979 } 2980 process_pending_signals (env); 2981 } 2982 } 2983 #endif 2984 2985 #ifdef TARGET_M68K 2986 2987 void cpu_loop(CPUM68KState *env) 2988 { 2989 CPUState *cs = CPU(m68k_env_get_cpu(env)); 2990 int trapnr; 2991 unsigned int n; 2992 target_siginfo_t info; 2993 TaskState *ts = cs->opaque; 2994 2995 for(;;) { 2996 cpu_exec_start(cs); 2997 trapnr = cpu_exec(cs); 2998 cpu_exec_end(cs); 2999 process_queued_cpu_work(cs); 3000 3001 switch(trapnr) { 3002 case EXCP_ILLEGAL: 3003 { 3004 if (ts->sim_syscalls) { 3005 uint16_t nr; 3006 get_user_u16(nr, env->pc + 2); 3007 env->pc += 4; 3008 do_m68k_simcall(env, nr); 3009 } else { 3010 goto do_sigill; 3011 } 3012 } 3013 break; 3014 case EXCP_HALT_INSN: 3015 /* Semihosing syscall. */ 3016 env->pc += 4; 3017 do_m68k_semihosting(env, env->dregs[0]); 3018 break; 3019 case EXCP_LINEA: 3020 case EXCP_LINEF: 3021 case EXCP_UNSUPPORTED: 3022 do_sigill: 3023 info.si_signo = TARGET_SIGILL; 3024 info.si_errno = 0; 3025 info.si_code = TARGET_ILL_ILLOPN; 3026 info._sifields._sigfault._addr = env->pc; 3027 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3028 break; 3029 case EXCP_TRAP0: 3030 { 3031 abi_long ret; 3032 ts->sim_syscalls = 0; 3033 n = env->dregs[0]; 3034 env->pc += 2; 3035 ret = do_syscall(env, 3036 n, 3037 env->dregs[1], 3038 env->dregs[2], 3039 env->dregs[3], 3040 env->dregs[4], 3041 env->dregs[5], 3042 env->aregs[0], 3043 0, 0); 3044 if (ret == -TARGET_ERESTARTSYS) { 3045 env->pc -= 2; 3046 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3047 env->dregs[0] = ret; 3048 } 3049 } 3050 break; 3051 case EXCP_INTERRUPT: 3052 /* just indicate that signals should be handled asap */ 3053 break; 3054 case EXCP_ACCESS: 3055 { 3056 info.si_signo = TARGET_SIGSEGV; 3057 info.si_errno = 0; 3058 /* XXX: check env->error_code */ 3059 info.si_code = TARGET_SEGV_MAPERR; 3060 info._sifields._sigfault._addr = env->mmu.ar; 3061 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3062 } 3063 break; 3064 case EXCP_DEBUG: 3065 { 3066 int sig; 3067 3068 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3069 if (sig) 3070 { 3071 info.si_signo = sig; 3072 info.si_errno = 0; 3073 info.si_code = TARGET_TRAP_BRKPT; 3074 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3075 } 3076 } 3077 break; 3078 default: 3079 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 3080 abort(); 3081 } 3082 process_pending_signals(env); 3083 } 3084 } 3085 #endif /* TARGET_M68K */ 3086 3087 #ifdef TARGET_ALPHA 3088 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 3089 { 3090 target_ulong addr, val, tmp; 3091 target_siginfo_t info; 3092 int ret = 0; 3093 3094 addr = env->lock_addr; 3095 tmp = env->lock_st_addr; 3096 env->lock_addr = -1; 3097 env->lock_st_addr = 0; 3098 3099 start_exclusive(); 3100 mmap_lock(); 3101 3102 if (addr == tmp) { 3103 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3104 goto do_sigsegv; 3105 } 3106 3107 if (val == env->lock_value) { 3108 tmp = env->ir[reg]; 3109 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 3110 goto do_sigsegv; 3111 } 3112 ret = 1; 3113 } 3114 } 3115 env->ir[reg] = ret; 3116 env->pc += 4; 3117 3118 mmap_unlock(); 3119 end_exclusive(); 3120 return; 3121 3122 do_sigsegv: 3123 mmap_unlock(); 3124 end_exclusive(); 3125 3126 info.si_signo = TARGET_SIGSEGV; 3127 info.si_errno = 0; 3128 info.si_code = TARGET_SEGV_MAPERR; 3129 info._sifields._sigfault._addr = addr; 3130 queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info); 3131 } 3132 3133 void cpu_loop(CPUAlphaState *env) 3134 { 3135 CPUState *cs = CPU(alpha_env_get_cpu(env)); 3136 int trapnr; 3137 target_siginfo_t info; 3138 abi_long sysret; 3139 3140 while (1) { 3141 cpu_exec_start(cs); 3142 trapnr = cpu_exec(cs); 3143 cpu_exec_end(cs); 3144 process_queued_cpu_work(cs); 3145 3146 /* All of the traps imply a transition through PALcode, which 3147 implies an REI instruction has been executed. Which means 3148 that the intr_flag should be cleared. */ 3149 env->intr_flag = 0; 3150 3151 switch (trapnr) { 3152 case EXCP_RESET: 3153 fprintf(stderr, "Reset requested. Exit\n"); 3154 exit(EXIT_FAILURE); 3155 break; 3156 case EXCP_MCHK: 3157 fprintf(stderr, "Machine check exception. Exit\n"); 3158 exit(EXIT_FAILURE); 3159 break; 3160 case EXCP_SMP_INTERRUPT: 3161 case EXCP_CLK_INTERRUPT: 3162 case EXCP_DEV_INTERRUPT: 3163 fprintf(stderr, "External interrupt. Exit\n"); 3164 exit(EXIT_FAILURE); 3165 break; 3166 case EXCP_MMFAULT: 3167 env->lock_addr = -1; 3168 info.si_signo = TARGET_SIGSEGV; 3169 info.si_errno = 0; 3170 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 3171 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 3172 info._sifields._sigfault._addr = env->trap_arg0; 3173 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3174 break; 3175 case EXCP_UNALIGN: 3176 env->lock_addr = -1; 3177 info.si_signo = TARGET_SIGBUS; 3178 info.si_errno = 0; 3179 info.si_code = TARGET_BUS_ADRALN; 3180 info._sifields._sigfault._addr = env->trap_arg0; 3181 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3182 break; 3183 case EXCP_OPCDEC: 3184 do_sigill: 3185 env->lock_addr = -1; 3186 info.si_signo = TARGET_SIGILL; 3187 info.si_errno = 0; 3188 info.si_code = TARGET_ILL_ILLOPC; 3189 info._sifields._sigfault._addr = env->pc; 3190 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3191 break; 3192 case EXCP_ARITH: 3193 env->lock_addr = -1; 3194 info.si_signo = TARGET_SIGFPE; 3195 info.si_errno = 0; 3196 info.si_code = TARGET_FPE_FLTINV; 3197 info._sifields._sigfault._addr = env->pc; 3198 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3199 break; 3200 case EXCP_FEN: 3201 /* No-op. Linux simply re-enables the FPU. */ 3202 break; 3203 case EXCP_CALL_PAL: 3204 env->lock_addr = -1; 3205 switch (env->error_code) { 3206 case 0x80: 3207 /* BPT */ 3208 info.si_signo = TARGET_SIGTRAP; 3209 info.si_errno = 0; 3210 info.si_code = TARGET_TRAP_BRKPT; 3211 info._sifields._sigfault._addr = env->pc; 3212 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3213 break; 3214 case 0x81: 3215 /* BUGCHK */ 3216 info.si_signo = TARGET_SIGTRAP; 3217 info.si_errno = 0; 3218 info.si_code = 0; 3219 info._sifields._sigfault._addr = env->pc; 3220 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3221 break; 3222 case 0x83: 3223 /* CALLSYS */ 3224 trapnr = env->ir[IR_V0]; 3225 sysret = do_syscall(env, trapnr, 3226 env->ir[IR_A0], env->ir[IR_A1], 3227 env->ir[IR_A2], env->ir[IR_A3], 3228 env->ir[IR_A4], env->ir[IR_A5], 3229 0, 0); 3230 if (sysret == -TARGET_ERESTARTSYS) { 3231 env->pc -= 4; 3232 break; 3233 } 3234 if (sysret == -TARGET_QEMU_ESIGRETURN) { 3235 break; 3236 } 3237 /* Syscall writes 0 to V0 to bypass error check, similar 3238 to how this is handled internal to Linux kernel. 3239 (Ab)use trapnr temporarily as boolean indicating error. */ 3240 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 3241 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 3242 env->ir[IR_A3] = trapnr; 3243 break; 3244 case 0x86: 3245 /* IMB */ 3246 /* ??? We can probably elide the code using page_unprotect 3247 that is checking for self-modifying code. Instead we 3248 could simply call tb_flush here. Until we work out the 3249 changes required to turn off the extra write protection, 3250 this can be a no-op. */ 3251 break; 3252 case 0x9E: 3253 /* RDUNIQUE */ 3254 /* Handled in the translator for usermode. */ 3255 abort(); 3256 case 0x9F: 3257 /* WRUNIQUE */ 3258 /* Handled in the translator for usermode. */ 3259 abort(); 3260 case 0xAA: 3261 /* GENTRAP */ 3262 info.si_signo = TARGET_SIGFPE; 3263 switch (env->ir[IR_A0]) { 3264 case TARGET_GEN_INTOVF: 3265 info.si_code = TARGET_FPE_INTOVF; 3266 break; 3267 case TARGET_GEN_INTDIV: 3268 info.si_code = TARGET_FPE_INTDIV; 3269 break; 3270 case TARGET_GEN_FLTOVF: 3271 info.si_code = TARGET_FPE_FLTOVF; 3272 break; 3273 case TARGET_GEN_FLTUND: 3274 info.si_code = TARGET_FPE_FLTUND; 3275 break; 3276 case TARGET_GEN_FLTINV: 3277 info.si_code = TARGET_FPE_FLTINV; 3278 break; 3279 case TARGET_GEN_FLTINE: 3280 info.si_code = TARGET_FPE_FLTRES; 3281 break; 3282 case TARGET_GEN_ROPRAND: 3283 info.si_code = 0; 3284 break; 3285 default: 3286 info.si_signo = TARGET_SIGTRAP; 3287 info.si_code = 0; 3288 break; 3289 } 3290 info.si_errno = 0; 3291 info._sifields._sigfault._addr = env->pc; 3292 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3293 break; 3294 default: 3295 goto do_sigill; 3296 } 3297 break; 3298 case EXCP_DEBUG: 3299 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); 3300 if (info.si_signo) { 3301 env->lock_addr = -1; 3302 info.si_errno = 0; 3303 info.si_code = TARGET_TRAP_BRKPT; 3304 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3305 } 3306 break; 3307 case EXCP_STL_C: 3308 case EXCP_STQ_C: 3309 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3310 break; 3311 case EXCP_INTERRUPT: 3312 /* Just indicate that signals should be handled asap. */ 3313 break; 3314 default: 3315 printf ("Unhandled trap: 0x%x\n", trapnr); 3316 cpu_dump_state(cs, stderr, fprintf, 0); 3317 exit(EXIT_FAILURE); 3318 } 3319 process_pending_signals (env); 3320 } 3321 } 3322 #endif /* TARGET_ALPHA */ 3323 3324 #ifdef TARGET_S390X 3325 void cpu_loop(CPUS390XState *env) 3326 { 3327 CPUState *cs = CPU(s390_env_get_cpu(env)); 3328 int trapnr, n, sig; 3329 target_siginfo_t info; 3330 target_ulong addr; 3331 abi_long ret; 3332 3333 while (1) { 3334 cpu_exec_start(cs); 3335 trapnr = cpu_exec(cs); 3336 cpu_exec_end(cs); 3337 process_queued_cpu_work(cs); 3338 3339 switch (trapnr) { 3340 case EXCP_INTERRUPT: 3341 /* Just indicate that signals should be handled asap. */ 3342 break; 3343 3344 case EXCP_SVC: 3345 n = env->int_svc_code; 3346 if (!n) { 3347 /* syscalls > 255 */ 3348 n = env->regs[1]; 3349 } 3350 env->psw.addr += env->int_svc_ilen; 3351 ret = do_syscall(env, n, env->regs[2], env->regs[3], 3352 env->regs[4], env->regs[5], 3353 env->regs[6], env->regs[7], 0, 0); 3354 if (ret == -TARGET_ERESTARTSYS) { 3355 env->psw.addr -= env->int_svc_ilen; 3356 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3357 env->regs[2] = ret; 3358 } 3359 break; 3360 3361 case EXCP_DEBUG: 3362 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3363 if (sig) { 3364 n = TARGET_TRAP_BRKPT; 3365 goto do_signal_pc; 3366 } 3367 break; 3368 case EXCP_PGM: 3369 n = env->int_pgm_code; 3370 switch (n) { 3371 case PGM_OPERATION: 3372 case PGM_PRIVILEGED: 3373 sig = TARGET_SIGILL; 3374 n = TARGET_ILL_ILLOPC; 3375 goto do_signal_pc; 3376 case PGM_PROTECTION: 3377 case PGM_ADDRESSING: 3378 sig = TARGET_SIGSEGV; 3379 /* XXX: check env->error_code */ 3380 n = TARGET_SEGV_MAPERR; 3381 addr = env->__excp_addr; 3382 goto do_signal; 3383 case PGM_EXECUTE: 3384 case PGM_SPECIFICATION: 3385 case PGM_SPECIAL_OP: 3386 case PGM_OPERAND: 3387 do_sigill_opn: 3388 sig = TARGET_SIGILL; 3389 n = TARGET_ILL_ILLOPN; 3390 goto do_signal_pc; 3391 3392 case PGM_FIXPT_OVERFLOW: 3393 sig = TARGET_SIGFPE; 3394 n = TARGET_FPE_INTOVF; 3395 goto do_signal_pc; 3396 case PGM_FIXPT_DIVIDE: 3397 sig = TARGET_SIGFPE; 3398 n = TARGET_FPE_INTDIV; 3399 goto do_signal_pc; 3400 3401 case PGM_DATA: 3402 n = (env->fpc >> 8) & 0xff; 3403 if (n == 0xff) { 3404 /* compare-and-trap */ 3405 goto do_sigill_opn; 3406 } else { 3407 /* An IEEE exception, simulated or otherwise. */ 3408 if (n & 0x80) { 3409 n = TARGET_FPE_FLTINV; 3410 } else if (n & 0x40) { 3411 n = TARGET_FPE_FLTDIV; 3412 } else if (n & 0x20) { 3413 n = TARGET_FPE_FLTOVF; 3414 } else if (n & 0x10) { 3415 n = TARGET_FPE_FLTUND; 3416 } else if (n & 0x08) { 3417 n = TARGET_FPE_FLTRES; 3418 } else { 3419 /* ??? Quantum exception; BFP, DFP error. */ 3420 goto do_sigill_opn; 3421 } 3422 sig = TARGET_SIGFPE; 3423 goto do_signal_pc; 3424 } 3425 3426 default: 3427 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3428 cpu_dump_state(cs, stderr, fprintf, 0); 3429 exit(EXIT_FAILURE); 3430 } 3431 break; 3432 3433 do_signal_pc: 3434 addr = env->psw.addr; 3435 do_signal: 3436 info.si_signo = sig; 3437 info.si_errno = 0; 3438 info.si_code = n; 3439 info._sifields._sigfault._addr = addr; 3440 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3441 break; 3442 3443 default: 3444 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3445 cpu_dump_state(cs, stderr, fprintf, 0); 3446 exit(EXIT_FAILURE); 3447 } 3448 process_pending_signals (env); 3449 } 3450 } 3451 3452 #endif /* TARGET_S390X */ 3453 3454 #ifdef TARGET_TILEGX 3455 3456 static void gen_sigill_reg(CPUTLGState *env) 3457 { 3458 target_siginfo_t info; 3459 3460 info.si_signo = TARGET_SIGILL; 3461 info.si_errno = 0; 3462 info.si_code = TARGET_ILL_PRVREG; 3463 info._sifields._sigfault._addr = env->pc; 3464 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3465 } 3466 3467 static void do_signal(CPUTLGState *env, int signo, int sigcode) 3468 { 3469 target_siginfo_t info; 3470 3471 info.si_signo = signo; 3472 info.si_errno = 0; 3473 info._sifields._sigfault._addr = env->pc; 3474 3475 if (signo == TARGET_SIGSEGV) { 3476 /* The passed in sigcode is a dummy; check for a page mapping 3477 and pass either MAPERR or ACCERR. */ 3478 target_ulong addr = env->excaddr; 3479 info._sifields._sigfault._addr = addr; 3480 if (page_check_range(addr, 1, PAGE_VALID) < 0) { 3481 sigcode = TARGET_SEGV_MAPERR; 3482 } else { 3483 sigcode = TARGET_SEGV_ACCERR; 3484 } 3485 } 3486 info.si_code = sigcode; 3487 3488 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3489 } 3490 3491 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) 3492 { 3493 env->excaddr = addr; 3494 do_signal(env, TARGET_SIGSEGV, 0); 3495 } 3496 3497 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) 3498 { 3499 if (unlikely(reg >= TILEGX_R_COUNT)) { 3500 switch (reg) { 3501 case TILEGX_R_SN: 3502 case TILEGX_R_ZERO: 3503 return; 3504 case TILEGX_R_IDN0: 3505 case TILEGX_R_IDN1: 3506 case TILEGX_R_UDN0: 3507 case TILEGX_R_UDN1: 3508 case TILEGX_R_UDN2: 3509 case TILEGX_R_UDN3: 3510 gen_sigill_reg(env); 3511 return; 3512 default: 3513 g_assert_not_reached(); 3514 } 3515 } 3516 env->regs[reg] = val; 3517 } 3518 3519 /* 3520 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in 3521 * memory at the address held in the first source register. If the values are 3522 * not equal, then no memory operation is performed. If the values are equal, 3523 * the 8-byte quantity from the second source register is written into memory 3524 * at the address held in the first source register. In either case, the result 3525 * of the instruction is the value read from memory. The compare and write to 3526 * memory are atomic and thus can be used for synchronization purposes. This 3527 * instruction only operates for addresses aligned to a 8-byte boundary. 3528 * Unaligned memory access causes an Unaligned Data Reference interrupt. 3529 * 3530 * Functional Description (64-bit) 3531 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); 3532 * rf[Dest] = memVal; 3533 * if (memVal == SPR[CmpValueSPR]) 3534 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); 3535 * 3536 * Functional Description (32-bit) 3537 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); 3538 * rf[Dest] = memVal; 3539 * if (memVal == signExtend32 (SPR[CmpValueSPR])) 3540 * memoryWriteWord (rf[SrcA], rf[SrcB]); 3541 * 3542 * 3543 * This function also processes exch and exch4 which need not process SPR. 3544 */ 3545 static void do_exch(CPUTLGState *env, bool quad, bool cmp) 3546 { 3547 target_ulong addr; 3548 target_long val, sprval; 3549 3550 start_exclusive(); 3551 3552 addr = env->atomic_srca; 3553 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3554 goto sigsegv_maperr; 3555 } 3556 3557 if (cmp) { 3558 if (quad) { 3559 sprval = env->spregs[TILEGX_SPR_CMPEXCH]; 3560 } else { 3561 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); 3562 } 3563 } 3564 3565 if (!cmp || val == sprval) { 3566 target_long valb = env->atomic_srcb; 3567 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3568 goto sigsegv_maperr; 3569 } 3570 } 3571 3572 set_regval(env, env->atomic_dstr, val); 3573 end_exclusive(); 3574 return; 3575 3576 sigsegv_maperr: 3577 end_exclusive(); 3578 gen_sigsegv_maperr(env, addr); 3579 } 3580 3581 static void do_fetch(CPUTLGState *env, int trapnr, bool quad) 3582 { 3583 int8_t write = 1; 3584 target_ulong addr; 3585 target_long val, valb; 3586 3587 start_exclusive(); 3588 3589 addr = env->atomic_srca; 3590 valb = env->atomic_srcb; 3591 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3592 goto sigsegv_maperr; 3593 } 3594 3595 switch (trapnr) { 3596 case TILEGX_EXCP_OPCODE_FETCHADD: 3597 case TILEGX_EXCP_OPCODE_FETCHADD4: 3598 valb += val; 3599 break; 3600 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3601 valb += val; 3602 if (valb < 0) { 3603 write = 0; 3604 } 3605 break; 3606 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3607 valb += val; 3608 if ((int32_t)valb < 0) { 3609 write = 0; 3610 } 3611 break; 3612 case TILEGX_EXCP_OPCODE_FETCHAND: 3613 case TILEGX_EXCP_OPCODE_FETCHAND4: 3614 valb &= val; 3615 break; 3616 case TILEGX_EXCP_OPCODE_FETCHOR: 3617 case TILEGX_EXCP_OPCODE_FETCHOR4: 3618 valb |= val; 3619 break; 3620 default: 3621 g_assert_not_reached(); 3622 } 3623 3624 if (write) { 3625 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3626 goto sigsegv_maperr; 3627 } 3628 } 3629 3630 set_regval(env, env->atomic_dstr, val); 3631 end_exclusive(); 3632 return; 3633 3634 sigsegv_maperr: 3635 end_exclusive(); 3636 gen_sigsegv_maperr(env, addr); 3637 } 3638 3639 void cpu_loop(CPUTLGState *env) 3640 { 3641 CPUState *cs = CPU(tilegx_env_get_cpu(env)); 3642 int trapnr; 3643 3644 while (1) { 3645 cpu_exec_start(cs); 3646 trapnr = cpu_exec(cs); 3647 cpu_exec_end(cs); 3648 process_queued_cpu_work(cs); 3649 3650 switch (trapnr) { 3651 case TILEGX_EXCP_SYSCALL: 3652 { 3653 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR], 3654 env->regs[0], env->regs[1], 3655 env->regs[2], env->regs[3], 3656 env->regs[4], env->regs[5], 3657 env->regs[6], env->regs[7]); 3658 if (ret == -TARGET_ERESTARTSYS) { 3659 env->pc -= 8; 3660 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3661 env->regs[TILEGX_R_RE] = ret; 3662 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0; 3663 } 3664 break; 3665 } 3666 case TILEGX_EXCP_OPCODE_EXCH: 3667 do_exch(env, true, false); 3668 break; 3669 case TILEGX_EXCP_OPCODE_EXCH4: 3670 do_exch(env, false, false); 3671 break; 3672 case TILEGX_EXCP_OPCODE_CMPEXCH: 3673 do_exch(env, true, true); 3674 break; 3675 case TILEGX_EXCP_OPCODE_CMPEXCH4: 3676 do_exch(env, false, true); 3677 break; 3678 case TILEGX_EXCP_OPCODE_FETCHADD: 3679 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3680 case TILEGX_EXCP_OPCODE_FETCHAND: 3681 case TILEGX_EXCP_OPCODE_FETCHOR: 3682 do_fetch(env, trapnr, true); 3683 break; 3684 case TILEGX_EXCP_OPCODE_FETCHADD4: 3685 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3686 case TILEGX_EXCP_OPCODE_FETCHAND4: 3687 case TILEGX_EXCP_OPCODE_FETCHOR4: 3688 do_fetch(env, trapnr, false); 3689 break; 3690 case TILEGX_EXCP_SIGNAL: 3691 do_signal(env, env->signo, env->sigcode); 3692 break; 3693 case TILEGX_EXCP_REG_IDN_ACCESS: 3694 case TILEGX_EXCP_REG_UDN_ACCESS: 3695 gen_sigill_reg(env); 3696 break; 3697 default: 3698 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); 3699 g_assert_not_reached(); 3700 } 3701 process_pending_signals(env); 3702 } 3703 } 3704 3705 #endif 3706 3707 THREAD CPUState *thread_cpu; 3708 3709 bool qemu_cpu_is_self(CPUState *cpu) 3710 { 3711 return thread_cpu == cpu; 3712 } 3713 3714 void qemu_cpu_kick(CPUState *cpu) 3715 { 3716 cpu_exit(cpu); 3717 } 3718 3719 void task_settid(TaskState *ts) 3720 { 3721 if (ts->ts_tid == 0) { 3722 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3723 } 3724 } 3725 3726 void stop_all_tasks(void) 3727 { 3728 /* 3729 * We trust that when using NPTL, start_exclusive() 3730 * handles thread stopping correctly. 3731 */ 3732 start_exclusive(); 3733 } 3734 3735 /* Assumes contents are already zeroed. */ 3736 void init_task_state(TaskState *ts) 3737 { 3738 ts->used = 1; 3739 } 3740 3741 CPUArchState *cpu_copy(CPUArchState *env) 3742 { 3743 CPUState *cpu = ENV_GET_CPU(env); 3744 CPUState *new_cpu = cpu_init(cpu_model); 3745 CPUArchState *new_env = new_cpu->env_ptr; 3746 CPUBreakpoint *bp; 3747 CPUWatchpoint *wp; 3748 3749 /* Reset non arch specific state */ 3750 cpu_reset(new_cpu); 3751 3752 memcpy(new_env, env, sizeof(CPUArchState)); 3753 3754 /* Clone all break/watchpoints. 3755 Note: Once we support ptrace with hw-debug register access, make sure 3756 BP_CPU break/watchpoints are handled correctly on clone. */ 3757 QTAILQ_INIT(&new_cpu->breakpoints); 3758 QTAILQ_INIT(&new_cpu->watchpoints); 3759 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 3760 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); 3761 } 3762 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { 3763 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); 3764 } 3765 3766 return new_env; 3767 } 3768 3769 static void handle_arg_help(const char *arg) 3770 { 3771 usage(EXIT_SUCCESS); 3772 } 3773 3774 static void handle_arg_log(const char *arg) 3775 { 3776 int mask; 3777 3778 mask = qemu_str_to_log_mask(arg); 3779 if (!mask) { 3780 qemu_print_log_usage(stdout); 3781 exit(EXIT_FAILURE); 3782 } 3783 qemu_log_needs_buffers(); 3784 qemu_set_log(mask); 3785 } 3786 3787 static void handle_arg_log_filename(const char *arg) 3788 { 3789 qemu_set_log_filename(arg, &error_fatal); 3790 } 3791 3792 static void handle_arg_set_env(const char *arg) 3793 { 3794 char *r, *p, *token; 3795 r = p = strdup(arg); 3796 while ((token = strsep(&p, ",")) != NULL) { 3797 if (envlist_setenv(envlist, token) != 0) { 3798 usage(EXIT_FAILURE); 3799 } 3800 } 3801 free(r); 3802 } 3803 3804 static void handle_arg_unset_env(const char *arg) 3805 { 3806 char *r, *p, *token; 3807 r = p = strdup(arg); 3808 while ((token = strsep(&p, ",")) != NULL) { 3809 if (envlist_unsetenv(envlist, token) != 0) { 3810 usage(EXIT_FAILURE); 3811 } 3812 } 3813 free(r); 3814 } 3815 3816 static void handle_arg_argv0(const char *arg) 3817 { 3818 argv0 = strdup(arg); 3819 } 3820 3821 static void handle_arg_stack_size(const char *arg) 3822 { 3823 char *p; 3824 guest_stack_size = strtoul(arg, &p, 0); 3825 if (guest_stack_size == 0) { 3826 usage(EXIT_FAILURE); 3827 } 3828 3829 if (*p == 'M') { 3830 guest_stack_size *= 1024 * 1024; 3831 } else if (*p == 'k' || *p == 'K') { 3832 guest_stack_size *= 1024; 3833 } 3834 } 3835 3836 static void handle_arg_ld_prefix(const char *arg) 3837 { 3838 interp_prefix = strdup(arg); 3839 } 3840 3841 static void handle_arg_pagesize(const char *arg) 3842 { 3843 qemu_host_page_size = atoi(arg); 3844 if (qemu_host_page_size == 0 || 3845 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3846 fprintf(stderr, "page size must be a power of two\n"); 3847 exit(EXIT_FAILURE); 3848 } 3849 } 3850 3851 static void handle_arg_randseed(const char *arg) 3852 { 3853 unsigned long long seed; 3854 3855 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) { 3856 fprintf(stderr, "Invalid seed number: %s\n", arg); 3857 exit(EXIT_FAILURE); 3858 } 3859 srand(seed); 3860 } 3861 3862 static void handle_arg_gdb(const char *arg) 3863 { 3864 gdbstub_port = atoi(arg); 3865 } 3866 3867 static void handle_arg_uname(const char *arg) 3868 { 3869 qemu_uname_release = strdup(arg); 3870 } 3871 3872 static void handle_arg_cpu(const char *arg) 3873 { 3874 cpu_model = strdup(arg); 3875 if (cpu_model == NULL || is_help_option(cpu_model)) { 3876 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3877 #if defined(cpu_list) 3878 cpu_list(stdout, &fprintf); 3879 #endif 3880 exit(EXIT_FAILURE); 3881 } 3882 } 3883 3884 static void handle_arg_guest_base(const char *arg) 3885 { 3886 guest_base = strtol(arg, NULL, 0); 3887 have_guest_base = 1; 3888 } 3889 3890 static void handle_arg_reserved_va(const char *arg) 3891 { 3892 char *p; 3893 int shift = 0; 3894 reserved_va = strtoul(arg, &p, 0); 3895 switch (*p) { 3896 case 'k': 3897 case 'K': 3898 shift = 10; 3899 break; 3900 case 'M': 3901 shift = 20; 3902 break; 3903 case 'G': 3904 shift = 30; 3905 break; 3906 } 3907 if (shift) { 3908 unsigned long unshifted = reserved_va; 3909 p++; 3910 reserved_va <<= shift; 3911 if (((reserved_va >> shift) != unshifted) 3912 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3913 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3914 #endif 3915 ) { 3916 fprintf(stderr, "Reserved virtual address too big\n"); 3917 exit(EXIT_FAILURE); 3918 } 3919 } 3920 if (*p) { 3921 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3922 exit(EXIT_FAILURE); 3923 } 3924 } 3925 3926 static void handle_arg_singlestep(const char *arg) 3927 { 3928 singlestep = 1; 3929 } 3930 3931 static void handle_arg_strace(const char *arg) 3932 { 3933 do_strace = 1; 3934 } 3935 3936 static void handle_arg_version(const char *arg) 3937 { 3938 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3939 ", " QEMU_COPYRIGHT "\n"); 3940 exit(EXIT_SUCCESS); 3941 } 3942 3943 static char *trace_file; 3944 static void handle_arg_trace(const char *arg) 3945 { 3946 g_free(trace_file); 3947 trace_file = trace_opt_parse(arg); 3948 } 3949 3950 struct qemu_argument { 3951 const char *argv; 3952 const char *env; 3953 bool has_arg; 3954 void (*handle_opt)(const char *arg); 3955 const char *example; 3956 const char *help; 3957 }; 3958 3959 static const struct qemu_argument arg_table[] = { 3960 {"h", "", false, handle_arg_help, 3961 "", "print this help"}, 3962 {"help", "", false, handle_arg_help, 3963 "", ""}, 3964 {"g", "QEMU_GDB", true, handle_arg_gdb, 3965 "port", "wait gdb connection to 'port'"}, 3966 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3967 "path", "set the elf interpreter prefix to 'path'"}, 3968 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3969 "size", "set the stack size to 'size' bytes"}, 3970 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3971 "model", "select CPU (-cpu help for list)"}, 3972 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3973 "var=value", "sets targets environment variable (see below)"}, 3974 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3975 "var", "unsets targets environment variable (see below)"}, 3976 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 3977 "argv0", "forces target process argv[0] to be 'argv0'"}, 3978 {"r", "QEMU_UNAME", true, handle_arg_uname, 3979 "uname", "set qemu uname release string to 'uname'"}, 3980 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 3981 "address", "set guest_base address to 'address'"}, 3982 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 3983 "size", "reserve 'size' bytes for guest virtual address space"}, 3984 {"d", "QEMU_LOG", true, handle_arg_log, 3985 "item[,...]", "enable logging of specified items " 3986 "(use '-d help' for a list of items)"}, 3987 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 3988 "logfile", "write logs to 'logfile' (default stderr)"}, 3989 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 3990 "pagesize", "set the host page size to 'pagesize'"}, 3991 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 3992 "", "run in singlestep mode"}, 3993 {"strace", "QEMU_STRACE", false, handle_arg_strace, 3994 "", "log system calls"}, 3995 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed, 3996 "", "Seed for pseudo-random number generator"}, 3997 {"trace", "QEMU_TRACE", true, handle_arg_trace, 3998 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"}, 3999 {"version", "QEMU_VERSION", false, handle_arg_version, 4000 "", "display version information and exit"}, 4001 {NULL, NULL, false, NULL, NULL, NULL} 4002 }; 4003 4004 static void usage(int exitcode) 4005 { 4006 const struct qemu_argument *arginfo; 4007 int maxarglen; 4008 int maxenvlen; 4009 4010 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 4011 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 4012 "\n" 4013 "Options and associated environment variables:\n" 4014 "\n"); 4015 4016 /* Calculate column widths. We must always have at least enough space 4017 * for the column header. 4018 */ 4019 maxarglen = strlen("Argument"); 4020 maxenvlen = strlen("Env-variable"); 4021 4022 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4023 int arglen = strlen(arginfo->argv); 4024 if (arginfo->has_arg) { 4025 arglen += strlen(arginfo->example) + 1; 4026 } 4027 if (strlen(arginfo->env) > maxenvlen) { 4028 maxenvlen = strlen(arginfo->env); 4029 } 4030 if (arglen > maxarglen) { 4031 maxarglen = arglen; 4032 } 4033 } 4034 4035 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 4036 maxenvlen, "Env-variable"); 4037 4038 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4039 if (arginfo->has_arg) { 4040 printf("-%s %-*s %-*s %s\n", arginfo->argv, 4041 (int)(maxarglen - strlen(arginfo->argv) - 1), 4042 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 4043 } else { 4044 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 4045 maxenvlen, arginfo->env, 4046 arginfo->help); 4047 } 4048 } 4049 4050 printf("\n" 4051 "Defaults:\n" 4052 "QEMU_LD_PREFIX = %s\n" 4053 "QEMU_STACK_SIZE = %ld byte\n", 4054 interp_prefix, 4055 guest_stack_size); 4056 4057 printf("\n" 4058 "You can use -E and -U options or the QEMU_SET_ENV and\n" 4059 "QEMU_UNSET_ENV environment variables to set and unset\n" 4060 "environment variables for the target process.\n" 4061 "It is possible to provide several variables by separating them\n" 4062 "by commas in getsubopt(3) style. Additionally it is possible to\n" 4063 "provide the -E and -U options multiple times.\n" 4064 "The following lines are equivalent:\n" 4065 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 4066 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 4067 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 4068 "Note that if you provide several changes to a single variable\n" 4069 "the last change will stay in effect.\n"); 4070 4071 exit(exitcode); 4072 } 4073 4074 static int parse_args(int argc, char **argv) 4075 { 4076 const char *r; 4077 int optind; 4078 const struct qemu_argument *arginfo; 4079 4080 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4081 if (arginfo->env == NULL) { 4082 continue; 4083 } 4084 4085 r = getenv(arginfo->env); 4086 if (r != NULL) { 4087 arginfo->handle_opt(r); 4088 } 4089 } 4090 4091 optind = 1; 4092 for (;;) { 4093 if (optind >= argc) { 4094 break; 4095 } 4096 r = argv[optind]; 4097 if (r[0] != '-') { 4098 break; 4099 } 4100 optind++; 4101 r++; 4102 if (!strcmp(r, "-")) { 4103 break; 4104 } 4105 /* Treat --foo the same as -foo. */ 4106 if (r[0] == '-') { 4107 r++; 4108 } 4109 4110 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4111 if (!strcmp(r, arginfo->argv)) { 4112 if (arginfo->has_arg) { 4113 if (optind >= argc) { 4114 (void) fprintf(stderr, 4115 "qemu: missing argument for option '%s'\n", r); 4116 exit(EXIT_FAILURE); 4117 } 4118 arginfo->handle_opt(argv[optind]); 4119 optind++; 4120 } else { 4121 arginfo->handle_opt(NULL); 4122 } 4123 break; 4124 } 4125 } 4126 4127 /* no option matched the current argv */ 4128 if (arginfo->handle_opt == NULL) { 4129 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r); 4130 exit(EXIT_FAILURE); 4131 } 4132 } 4133 4134 if (optind >= argc) { 4135 (void) fprintf(stderr, "qemu: no user program specified\n"); 4136 exit(EXIT_FAILURE); 4137 } 4138 4139 filename = argv[optind]; 4140 exec_path = argv[optind]; 4141 4142 return optind; 4143 } 4144 4145 int main(int argc, char **argv, char **envp) 4146 { 4147 struct target_pt_regs regs1, *regs = ®s1; 4148 struct image_info info1, *info = &info1; 4149 struct linux_binprm bprm; 4150 TaskState *ts; 4151 CPUArchState *env; 4152 CPUState *cpu; 4153 int optind; 4154 char **target_environ, **wrk; 4155 char **target_argv; 4156 int target_argc; 4157 int i; 4158 int ret; 4159 int execfd; 4160 4161 qemu_init_cpu_list(); 4162 module_call_init(MODULE_INIT_QOM); 4163 4164 if ((envlist = envlist_create()) == NULL) { 4165 (void) fprintf(stderr, "Unable to allocate envlist\n"); 4166 exit(EXIT_FAILURE); 4167 } 4168 4169 /* add current environment into the list */ 4170 for (wrk = environ; *wrk != NULL; wrk++) { 4171 (void) envlist_setenv(envlist, *wrk); 4172 } 4173 4174 /* Read the stack limit from the kernel. If it's "unlimited", 4175 then we can do little else besides use the default. */ 4176 { 4177 struct rlimit lim; 4178 if (getrlimit(RLIMIT_STACK, &lim) == 0 4179 && lim.rlim_cur != RLIM_INFINITY 4180 && lim.rlim_cur == (target_long)lim.rlim_cur) { 4181 guest_stack_size = lim.rlim_cur; 4182 } 4183 } 4184 4185 cpu_model = NULL; 4186 4187 srand(time(NULL)); 4188 4189 qemu_add_opts(&qemu_trace_opts); 4190 4191 optind = parse_args(argc, argv); 4192 4193 if (!trace_init_backends()) { 4194 exit(1); 4195 } 4196 trace_init_file(trace_file); 4197 4198 /* Zero out regs */ 4199 memset(regs, 0, sizeof(struct target_pt_regs)); 4200 4201 /* Zero out image_info */ 4202 memset(info, 0, sizeof(struct image_info)); 4203 4204 memset(&bprm, 0, sizeof (bprm)); 4205 4206 /* Scan interp_prefix dir for replacement files. */ 4207 init_paths(interp_prefix); 4208 4209 init_qemu_uname_release(); 4210 4211 if (cpu_model == NULL) { 4212 #if defined(TARGET_I386) 4213 #ifdef TARGET_X86_64 4214 cpu_model = "qemu64"; 4215 #else 4216 cpu_model = "qemu32"; 4217 #endif 4218 #elif defined(TARGET_ARM) 4219 cpu_model = "any"; 4220 #elif defined(TARGET_UNICORE32) 4221 cpu_model = "any"; 4222 #elif defined(TARGET_M68K) 4223 cpu_model = "any"; 4224 #elif defined(TARGET_SPARC) 4225 #ifdef TARGET_SPARC64 4226 cpu_model = "TI UltraSparc II"; 4227 #else 4228 cpu_model = "Fujitsu MB86904"; 4229 #endif 4230 #elif defined(TARGET_MIPS) 4231 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 4232 cpu_model = "5KEf"; 4233 #else 4234 cpu_model = "24Kf"; 4235 #endif 4236 #elif defined TARGET_OPENRISC 4237 cpu_model = "or1200"; 4238 #elif defined(TARGET_PPC) 4239 # ifdef TARGET_PPC64 4240 cpu_model = "POWER8"; 4241 # else 4242 cpu_model = "750"; 4243 # endif 4244 #elif defined TARGET_SH4 4245 cpu_model = TYPE_SH7785_CPU; 4246 #else 4247 cpu_model = "any"; 4248 #endif 4249 } 4250 tcg_exec_init(0); 4251 /* NOTE: we need to init the CPU at this stage to get 4252 qemu_host_page_size */ 4253 cpu = cpu_init(cpu_model); 4254 if (!cpu) { 4255 fprintf(stderr, "Unable to find CPU definition\n"); 4256 exit(EXIT_FAILURE); 4257 } 4258 env = cpu->env_ptr; 4259 cpu_reset(cpu); 4260 4261 thread_cpu = cpu; 4262 4263 if (getenv("QEMU_STRACE")) { 4264 do_strace = 1; 4265 } 4266 4267 if (getenv("QEMU_RAND_SEED")) { 4268 handle_arg_randseed(getenv("QEMU_RAND_SEED")); 4269 } 4270 4271 target_environ = envlist_to_environ(envlist, NULL); 4272 envlist_free(envlist); 4273 4274 /* 4275 * Now that page sizes are configured in cpu_init() we can do 4276 * proper page alignment for guest_base. 4277 */ 4278 guest_base = HOST_PAGE_ALIGN(guest_base); 4279 4280 if (reserved_va || have_guest_base) { 4281 guest_base = init_guest_space(guest_base, reserved_va, 0, 4282 have_guest_base); 4283 if (guest_base == (unsigned long)-1) { 4284 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 4285 "space for use as guest address space (check your virtual " 4286 "memory ulimit setting or reserve less using -R option)\n", 4287 reserved_va); 4288 exit(EXIT_FAILURE); 4289 } 4290 4291 if (reserved_va) { 4292 mmap_next_start = reserved_va; 4293 } 4294 } 4295 4296 /* 4297 * Read in mmap_min_addr kernel parameter. This value is used 4298 * When loading the ELF image to determine whether guest_base 4299 * is needed. It is also used in mmap_find_vma. 4300 */ 4301 { 4302 FILE *fp; 4303 4304 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 4305 unsigned long tmp; 4306 if (fscanf(fp, "%lu", &tmp) == 1) { 4307 mmap_min_addr = tmp; 4308 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr); 4309 } 4310 fclose(fp); 4311 } 4312 } 4313 4314 /* 4315 * Prepare copy of argv vector for target. 4316 */ 4317 target_argc = argc - optind; 4318 target_argv = calloc(target_argc + 1, sizeof (char *)); 4319 if (target_argv == NULL) { 4320 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 4321 exit(EXIT_FAILURE); 4322 } 4323 4324 /* 4325 * If argv0 is specified (using '-0' switch) we replace 4326 * argv[0] pointer with the given one. 4327 */ 4328 i = 0; 4329 if (argv0 != NULL) { 4330 target_argv[i++] = strdup(argv0); 4331 } 4332 for (; i < target_argc; i++) { 4333 target_argv[i] = strdup(argv[optind + i]); 4334 } 4335 target_argv[target_argc] = NULL; 4336 4337 ts = g_new0(TaskState, 1); 4338 init_task_state(ts); 4339 /* build Task State */ 4340 ts->info = info; 4341 ts->bprm = &bprm; 4342 cpu->opaque = ts; 4343 task_settid(ts); 4344 4345 execfd = qemu_getauxval(AT_EXECFD); 4346 if (execfd == 0) { 4347 execfd = open(filename, O_RDONLY); 4348 if (execfd < 0) { 4349 printf("Error while loading %s: %s\n", filename, strerror(errno)); 4350 _exit(EXIT_FAILURE); 4351 } 4352 } 4353 4354 ret = loader_exec(execfd, filename, target_argv, target_environ, regs, 4355 info, &bprm); 4356 if (ret != 0) { 4357 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 4358 _exit(EXIT_FAILURE); 4359 } 4360 4361 for (wrk = target_environ; *wrk; wrk++) { 4362 free(*wrk); 4363 } 4364 4365 free(target_environ); 4366 4367 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { 4368 qemu_log("guest_base 0x%lx\n", guest_base); 4369 log_page_dump(); 4370 4371 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 4372 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 4373 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 4374 info->start_code); 4375 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 4376 info->start_data); 4377 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 4378 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 4379 info->start_stack); 4380 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 4381 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 4382 } 4383 4384 target_set_brk(info->brk); 4385 syscall_init(); 4386 signal_init(); 4387 4388 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 4389 generating the prologue until now so that the prologue can take 4390 the real value of GUEST_BASE into account. */ 4391 tcg_prologue_init(&tcg_ctx); 4392 4393 #if defined(TARGET_I386) 4394 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 4395 env->hflags |= HF_PE_MASK | HF_CPL_MASK; 4396 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4397 env->cr[4] |= CR4_OSFXSR_MASK; 4398 env->hflags |= HF_OSFXSR_MASK; 4399 } 4400 #ifndef TARGET_ABI32 4401 /* enable 64 bit mode if possible */ 4402 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 4403 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 4404 exit(EXIT_FAILURE); 4405 } 4406 env->cr[4] |= CR4_PAE_MASK; 4407 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 4408 env->hflags |= HF_LMA_MASK; 4409 #endif 4410 4411 /* flags setup : we activate the IRQs by default as in user mode */ 4412 env->eflags |= IF_MASK; 4413 4414 /* linux register setup */ 4415 #ifndef TARGET_ABI32 4416 env->regs[R_EAX] = regs->rax; 4417 env->regs[R_EBX] = regs->rbx; 4418 env->regs[R_ECX] = regs->rcx; 4419 env->regs[R_EDX] = regs->rdx; 4420 env->regs[R_ESI] = regs->rsi; 4421 env->regs[R_EDI] = regs->rdi; 4422 env->regs[R_EBP] = regs->rbp; 4423 env->regs[R_ESP] = regs->rsp; 4424 env->eip = regs->rip; 4425 #else 4426 env->regs[R_EAX] = regs->eax; 4427 env->regs[R_EBX] = regs->ebx; 4428 env->regs[R_ECX] = regs->ecx; 4429 env->regs[R_EDX] = regs->edx; 4430 env->regs[R_ESI] = regs->esi; 4431 env->regs[R_EDI] = regs->edi; 4432 env->regs[R_EBP] = regs->ebp; 4433 env->regs[R_ESP] = regs->esp; 4434 env->eip = regs->eip; 4435 #endif 4436 4437 /* linux interrupt setup */ 4438 #ifndef TARGET_ABI32 4439 env->idt.limit = 511; 4440 #else 4441 env->idt.limit = 255; 4442 #endif 4443 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 4444 PROT_READ|PROT_WRITE, 4445 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4446 idt_table = g2h(env->idt.base); 4447 set_idt(0, 0); 4448 set_idt(1, 0); 4449 set_idt(2, 0); 4450 set_idt(3, 3); 4451 set_idt(4, 3); 4452 set_idt(5, 0); 4453 set_idt(6, 0); 4454 set_idt(7, 0); 4455 set_idt(8, 0); 4456 set_idt(9, 0); 4457 set_idt(10, 0); 4458 set_idt(11, 0); 4459 set_idt(12, 0); 4460 set_idt(13, 0); 4461 set_idt(14, 0); 4462 set_idt(15, 0); 4463 set_idt(16, 0); 4464 set_idt(17, 0); 4465 set_idt(18, 0); 4466 set_idt(19, 0); 4467 set_idt(0x80, 3); 4468 4469 /* linux segment setup */ 4470 { 4471 uint64_t *gdt_table; 4472 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 4473 PROT_READ|PROT_WRITE, 4474 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4475 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 4476 gdt_table = g2h(env->gdt.base); 4477 #ifdef TARGET_ABI32 4478 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4479 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4480 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4481 #else 4482 /* 64 bit code segment */ 4483 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4484 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4485 DESC_L_MASK | 4486 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4487 #endif 4488 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 4489 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4490 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 4491 } 4492 cpu_x86_load_seg(env, R_CS, __USER_CS); 4493 cpu_x86_load_seg(env, R_SS, __USER_DS); 4494 #ifdef TARGET_ABI32 4495 cpu_x86_load_seg(env, R_DS, __USER_DS); 4496 cpu_x86_load_seg(env, R_ES, __USER_DS); 4497 cpu_x86_load_seg(env, R_FS, __USER_DS); 4498 cpu_x86_load_seg(env, R_GS, __USER_DS); 4499 /* This hack makes Wine work... */ 4500 env->segs[R_FS].selector = 0; 4501 #else 4502 cpu_x86_load_seg(env, R_DS, 0); 4503 cpu_x86_load_seg(env, R_ES, 0); 4504 cpu_x86_load_seg(env, R_FS, 0); 4505 cpu_x86_load_seg(env, R_GS, 0); 4506 #endif 4507 #elif defined(TARGET_AARCH64) 4508 { 4509 int i; 4510 4511 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 4512 fprintf(stderr, 4513 "The selected ARM CPU does not support 64 bit mode\n"); 4514 exit(EXIT_FAILURE); 4515 } 4516 4517 for (i = 0; i < 31; i++) { 4518 env->xregs[i] = regs->regs[i]; 4519 } 4520 env->pc = regs->pc; 4521 env->xregs[31] = regs->sp; 4522 } 4523 #elif defined(TARGET_ARM) 4524 { 4525 int i; 4526 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, 4527 CPSRWriteByInstr); 4528 for(i = 0; i < 16; i++) { 4529 env->regs[i] = regs->uregs[i]; 4530 } 4531 #ifdef TARGET_WORDS_BIGENDIAN 4532 /* Enable BE8. */ 4533 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 4534 && (info->elf_flags & EF_ARM_BE8)) { 4535 env->uncached_cpsr |= CPSR_E; 4536 env->cp15.sctlr_el[1] |= SCTLR_E0E; 4537 } else { 4538 env->cp15.sctlr_el[1] |= SCTLR_B; 4539 } 4540 #endif 4541 } 4542 #elif defined(TARGET_UNICORE32) 4543 { 4544 int i; 4545 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 4546 for (i = 0; i < 32; i++) { 4547 env->regs[i] = regs->uregs[i]; 4548 } 4549 } 4550 #elif defined(TARGET_SPARC) 4551 { 4552 int i; 4553 env->pc = regs->pc; 4554 env->npc = regs->npc; 4555 env->y = regs->y; 4556 for(i = 0; i < 8; i++) 4557 env->gregs[i] = regs->u_regs[i]; 4558 for(i = 0; i < 8; i++) 4559 env->regwptr[i] = regs->u_regs[i + 8]; 4560 } 4561 #elif defined(TARGET_PPC) 4562 { 4563 int i; 4564 4565 #if defined(TARGET_PPC64) 4566 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; 4567 #if defined(TARGET_ABI32) 4568 env->msr &= ~((target_ulong)1 << flag); 4569 #else 4570 env->msr |= (target_ulong)1 << flag; 4571 #endif 4572 #endif 4573 env->nip = regs->nip; 4574 for(i = 0; i < 32; i++) { 4575 env->gpr[i] = regs->gpr[i]; 4576 } 4577 } 4578 #elif defined(TARGET_M68K) 4579 { 4580 env->pc = regs->pc; 4581 env->dregs[0] = regs->d0; 4582 env->dregs[1] = regs->d1; 4583 env->dregs[2] = regs->d2; 4584 env->dregs[3] = regs->d3; 4585 env->dregs[4] = regs->d4; 4586 env->dregs[5] = regs->d5; 4587 env->dregs[6] = regs->d6; 4588 env->dregs[7] = regs->d7; 4589 env->aregs[0] = regs->a0; 4590 env->aregs[1] = regs->a1; 4591 env->aregs[2] = regs->a2; 4592 env->aregs[3] = regs->a3; 4593 env->aregs[4] = regs->a4; 4594 env->aregs[5] = regs->a5; 4595 env->aregs[6] = regs->a6; 4596 env->aregs[7] = regs->usp; 4597 env->sr = regs->sr; 4598 ts->sim_syscalls = 1; 4599 } 4600 #elif defined(TARGET_MICROBLAZE) 4601 { 4602 env->regs[0] = regs->r0; 4603 env->regs[1] = regs->r1; 4604 env->regs[2] = regs->r2; 4605 env->regs[3] = regs->r3; 4606 env->regs[4] = regs->r4; 4607 env->regs[5] = regs->r5; 4608 env->regs[6] = regs->r6; 4609 env->regs[7] = regs->r7; 4610 env->regs[8] = regs->r8; 4611 env->regs[9] = regs->r9; 4612 env->regs[10] = regs->r10; 4613 env->regs[11] = regs->r11; 4614 env->regs[12] = regs->r12; 4615 env->regs[13] = regs->r13; 4616 env->regs[14] = regs->r14; 4617 env->regs[15] = regs->r15; 4618 env->regs[16] = regs->r16; 4619 env->regs[17] = regs->r17; 4620 env->regs[18] = regs->r18; 4621 env->regs[19] = regs->r19; 4622 env->regs[20] = regs->r20; 4623 env->regs[21] = regs->r21; 4624 env->regs[22] = regs->r22; 4625 env->regs[23] = regs->r23; 4626 env->regs[24] = regs->r24; 4627 env->regs[25] = regs->r25; 4628 env->regs[26] = regs->r26; 4629 env->regs[27] = regs->r27; 4630 env->regs[28] = regs->r28; 4631 env->regs[29] = regs->r29; 4632 env->regs[30] = regs->r30; 4633 env->regs[31] = regs->r31; 4634 env->sregs[SR_PC] = regs->pc; 4635 } 4636 #elif defined(TARGET_MIPS) 4637 { 4638 int i; 4639 4640 for(i = 0; i < 32; i++) { 4641 env->active_tc.gpr[i] = regs->regs[i]; 4642 } 4643 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 4644 if (regs->cp0_epc & 1) { 4645 env->hflags |= MIPS_HFLAG_M16; 4646 } 4647 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != 4648 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { 4649 if ((env->active_fpu.fcr31_rw_bitmask & 4650 (1 << FCR31_NAN2008)) == 0) { 4651 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); 4652 exit(1); 4653 } 4654 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { 4655 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); 4656 } else { 4657 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); 4658 } 4659 restore_snan_bit_mode(env); 4660 } 4661 } 4662 #elif defined(TARGET_OPENRISC) 4663 { 4664 int i; 4665 4666 for (i = 0; i < 32; i++) { 4667 env->gpr[i] = regs->gpr[i]; 4668 } 4669 4670 env->sr = regs->sr; 4671 env->pc = regs->pc; 4672 } 4673 #elif defined(TARGET_SH4) 4674 { 4675 int i; 4676 4677 for(i = 0; i < 16; i++) { 4678 env->gregs[i] = regs->regs[i]; 4679 } 4680 env->pc = regs->pc; 4681 } 4682 #elif defined(TARGET_ALPHA) 4683 { 4684 int i; 4685 4686 for(i = 0; i < 28; i++) { 4687 env->ir[i] = ((abi_ulong *)regs)[i]; 4688 } 4689 env->ir[IR_SP] = regs->usp; 4690 env->pc = regs->pc; 4691 } 4692 #elif defined(TARGET_CRIS) 4693 { 4694 env->regs[0] = regs->r0; 4695 env->regs[1] = regs->r1; 4696 env->regs[2] = regs->r2; 4697 env->regs[3] = regs->r3; 4698 env->regs[4] = regs->r4; 4699 env->regs[5] = regs->r5; 4700 env->regs[6] = regs->r6; 4701 env->regs[7] = regs->r7; 4702 env->regs[8] = regs->r8; 4703 env->regs[9] = regs->r9; 4704 env->regs[10] = regs->r10; 4705 env->regs[11] = regs->r11; 4706 env->regs[12] = regs->r12; 4707 env->regs[13] = regs->r13; 4708 env->regs[14] = info->start_stack; 4709 env->regs[15] = regs->acr; 4710 env->pc = regs->erp; 4711 } 4712 #elif defined(TARGET_S390X) 4713 { 4714 int i; 4715 for (i = 0; i < 16; i++) { 4716 env->regs[i] = regs->gprs[i]; 4717 } 4718 env->psw.mask = regs->psw.mask; 4719 env->psw.addr = regs->psw.addr; 4720 } 4721 #elif defined(TARGET_TILEGX) 4722 { 4723 int i; 4724 for (i = 0; i < TILEGX_R_COUNT; i++) { 4725 env->regs[i] = regs->regs[i]; 4726 } 4727 for (i = 0; i < TILEGX_SPR_COUNT; i++) { 4728 env->spregs[i] = 0; 4729 } 4730 env->pc = regs->pc; 4731 } 4732 #else 4733 #error unsupported target CPU 4734 #endif 4735 4736 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4737 ts->stack_base = info->start_stack; 4738 ts->heap_base = info->brk; 4739 /* This will be filled in on the first SYS_HEAPINFO call. */ 4740 ts->heap_limit = 0; 4741 #endif 4742 4743 if (gdbstub_port) { 4744 if (gdbserver_start(gdbstub_port) < 0) { 4745 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4746 gdbstub_port); 4747 exit(EXIT_FAILURE); 4748 } 4749 gdb_handlesig(cpu, 0); 4750 } 4751 cpu_loop(env); 4752 /* never exits */ 4753 return 0; 4754 } 4755