1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <stdlib.h> 20 #include <stdio.h> 21 #include <stdarg.h> 22 #include <string.h> 23 #include <errno.h> 24 #include <unistd.h> 25 #include <sys/mman.h> 26 #include <sys/syscall.h> 27 #include <sys/resource.h> 28 29 #include "qemu.h" 30 #include "qemu-common.h" 31 #include "qemu/cache-utils.h" 32 #include "cpu.h" 33 #include "tcg.h" 34 #include "qemu/timer.h" 35 #include "qemu/envlist.h" 36 #include "elf.h" 37 38 char *exec_path; 39 40 int singlestep; 41 const char *filename; 42 const char *argv0; 43 int gdbstub_port; 44 envlist_t *envlist; 45 const char *cpu_model; 46 unsigned long mmap_min_addr; 47 #if defined(CONFIG_USE_GUEST_BASE) 48 unsigned long guest_base; 49 int have_guest_base; 50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 51 /* 52 * When running 32-on-64 we should make sure we can fit all of the possible 53 * guest address space into a contiguous chunk of virtual host memory. 54 * 55 * This way we will never overlap with our own libraries or binaries or stack 56 * or anything else that QEMU maps. 57 */ 58 # ifdef TARGET_MIPS 59 /* MIPS only supports 31 bits of virtual address space for user space */ 60 unsigned long reserved_va = 0x77000000; 61 # else 62 unsigned long reserved_va = 0xf7000000; 63 # endif 64 #else 65 unsigned long reserved_va; 66 #endif 67 #endif 68 69 static void usage(void); 70 71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE; 73 74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 75 we allocate a bigger stack. Need a better solution, for example 76 by remapping the process stack directly at the right place */ 77 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 78 79 void gemu_log(const char *fmt, ...) 80 { 81 va_list ap; 82 83 va_start(ap, fmt); 84 vfprintf(stderr, fmt, ap); 85 va_end(ap); 86 } 87 88 #if defined(TARGET_I386) 89 int cpu_get_pic_interrupt(CPUX86State *env) 90 { 91 return -1; 92 } 93 #endif 94 95 #if defined(CONFIG_USE_NPTL) 96 /***********************************************************/ 97 /* Helper routines for implementing atomic operations. */ 98 99 /* To implement exclusive operations we force all cpus to syncronise. 100 We don't require a full sync, only that no cpus are executing guest code. 101 The alternative is to map target atomic ops onto host equivalents, 102 which requires quite a lot of per host/target work. */ 103 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; 104 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; 105 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; 106 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; 107 static int pending_cpus; 108 109 /* Make sure everything is in a consistent state for calling fork(). */ 110 void fork_start(void) 111 { 112 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 113 pthread_mutex_lock(&exclusive_lock); 114 mmap_fork_start(); 115 } 116 117 void fork_end(int child) 118 { 119 mmap_fork_end(child); 120 if (child) { 121 /* Child processes created by fork() only have a single thread. 122 Discard information about the parent threads. */ 123 first_cpu = thread_cpu; 124 first_cpu->next_cpu = NULL; 125 pending_cpus = 0; 126 pthread_mutex_init(&exclusive_lock, NULL); 127 pthread_mutex_init(&cpu_list_mutex, NULL); 128 pthread_cond_init(&exclusive_cond, NULL); 129 pthread_cond_init(&exclusive_resume, NULL); 130 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL); 131 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); 132 } else { 133 pthread_mutex_unlock(&exclusive_lock); 134 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 135 } 136 } 137 138 /* Wait for pending exclusive operations to complete. The exclusive lock 139 must be held. */ 140 static inline void exclusive_idle(void) 141 { 142 while (pending_cpus) { 143 pthread_cond_wait(&exclusive_resume, &exclusive_lock); 144 } 145 } 146 147 /* Start an exclusive operation. 148 Must only be called from outside cpu_arm_exec. */ 149 static inline void start_exclusive(void) 150 { 151 CPUState *other_cpu; 152 153 pthread_mutex_lock(&exclusive_lock); 154 exclusive_idle(); 155 156 pending_cpus = 1; 157 /* Make all other cpus stop executing. */ 158 for (other_cpu = first_cpu; other_cpu; other_cpu = other_cpu->next_cpu) { 159 if (other_cpu->running) { 160 pending_cpus++; 161 cpu_exit(other_cpu); 162 } 163 } 164 if (pending_cpus > 1) { 165 pthread_cond_wait(&exclusive_cond, &exclusive_lock); 166 } 167 } 168 169 /* Finish an exclusive operation. */ 170 static inline void end_exclusive(void) 171 { 172 pending_cpus = 0; 173 pthread_cond_broadcast(&exclusive_resume); 174 pthread_mutex_unlock(&exclusive_lock); 175 } 176 177 /* Wait for exclusive ops to finish, and begin cpu execution. */ 178 static inline void cpu_exec_start(CPUState *cpu) 179 { 180 pthread_mutex_lock(&exclusive_lock); 181 exclusive_idle(); 182 cpu->running = true; 183 pthread_mutex_unlock(&exclusive_lock); 184 } 185 186 /* Mark cpu as not executing, and release pending exclusive ops. */ 187 static inline void cpu_exec_end(CPUState *cpu) 188 { 189 pthread_mutex_lock(&exclusive_lock); 190 cpu->running = false; 191 if (pending_cpus > 1) { 192 pending_cpus--; 193 if (pending_cpus == 1) { 194 pthread_cond_signal(&exclusive_cond); 195 } 196 } 197 exclusive_idle(); 198 pthread_mutex_unlock(&exclusive_lock); 199 } 200 201 void cpu_list_lock(void) 202 { 203 pthread_mutex_lock(&cpu_list_mutex); 204 } 205 206 void cpu_list_unlock(void) 207 { 208 pthread_mutex_unlock(&cpu_list_mutex); 209 } 210 #else /* if !CONFIG_USE_NPTL */ 211 /* These are no-ops because we are not threadsafe. */ 212 static inline void cpu_exec_start(CPUState *cpu) 213 { 214 } 215 216 static inline void cpu_exec_end(CPUState *cpu) 217 { 218 } 219 220 static inline void start_exclusive(void) 221 { 222 } 223 224 static inline void end_exclusive(void) 225 { 226 } 227 228 void fork_start(void) 229 { 230 } 231 232 void fork_end(int child) 233 { 234 if (child) { 235 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr); 236 } 237 } 238 239 void cpu_list_lock(void) 240 { 241 } 242 243 void cpu_list_unlock(void) 244 { 245 } 246 #endif 247 248 249 #ifdef TARGET_I386 250 /***********************************************************/ 251 /* CPUX86 core interface */ 252 253 void cpu_smm_update(CPUX86State *env) 254 { 255 } 256 257 uint64_t cpu_get_tsc(CPUX86State *env) 258 { 259 return cpu_get_real_ticks(); 260 } 261 262 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 263 int flags) 264 { 265 unsigned int e1, e2; 266 uint32_t *p; 267 e1 = (addr << 16) | (limit & 0xffff); 268 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 269 e2 |= flags; 270 p = ptr; 271 p[0] = tswap32(e1); 272 p[1] = tswap32(e2); 273 } 274 275 static uint64_t *idt_table; 276 #ifdef TARGET_X86_64 277 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 278 uint64_t addr, unsigned int sel) 279 { 280 uint32_t *p, e1, e2; 281 e1 = (addr & 0xffff) | (sel << 16); 282 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 283 p = ptr; 284 p[0] = tswap32(e1); 285 p[1] = tswap32(e2); 286 p[2] = tswap32(addr >> 32); 287 p[3] = 0; 288 } 289 /* only dpl matters as we do only user space emulation */ 290 static void set_idt(int n, unsigned int dpl) 291 { 292 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 293 } 294 #else 295 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 296 uint32_t addr, unsigned int sel) 297 { 298 uint32_t *p, e1, e2; 299 e1 = (addr & 0xffff) | (sel << 16); 300 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 301 p = ptr; 302 p[0] = tswap32(e1); 303 p[1] = tswap32(e2); 304 } 305 306 /* only dpl matters as we do only user space emulation */ 307 static void set_idt(int n, unsigned int dpl) 308 { 309 set_gate(idt_table + n, 0, dpl, 0, 0); 310 } 311 #endif 312 313 void cpu_loop(CPUX86State *env) 314 { 315 int trapnr; 316 abi_ulong pc; 317 target_siginfo_t info; 318 319 for(;;) { 320 trapnr = cpu_x86_exec(env); 321 switch(trapnr) { 322 case 0x80: 323 /* linux syscall from int $0x80 */ 324 env->regs[R_EAX] = do_syscall(env, 325 env->regs[R_EAX], 326 env->regs[R_EBX], 327 env->regs[R_ECX], 328 env->regs[R_EDX], 329 env->regs[R_ESI], 330 env->regs[R_EDI], 331 env->regs[R_EBP], 332 0, 0); 333 break; 334 #ifndef TARGET_ABI32 335 case EXCP_SYSCALL: 336 /* linux syscall from syscall instruction */ 337 env->regs[R_EAX] = do_syscall(env, 338 env->regs[R_EAX], 339 env->regs[R_EDI], 340 env->regs[R_ESI], 341 env->regs[R_EDX], 342 env->regs[10], 343 env->regs[8], 344 env->regs[9], 345 0, 0); 346 env->eip = env->exception_next_eip; 347 break; 348 #endif 349 case EXCP0B_NOSEG: 350 case EXCP0C_STACK: 351 info.si_signo = SIGBUS; 352 info.si_errno = 0; 353 info.si_code = TARGET_SI_KERNEL; 354 info._sifields._sigfault._addr = 0; 355 queue_signal(env, info.si_signo, &info); 356 break; 357 case EXCP0D_GPF: 358 /* XXX: potential problem if ABI32 */ 359 #ifndef TARGET_X86_64 360 if (env->eflags & VM_MASK) { 361 handle_vm86_fault(env); 362 } else 363 #endif 364 { 365 info.si_signo = SIGSEGV; 366 info.si_errno = 0; 367 info.si_code = TARGET_SI_KERNEL; 368 info._sifields._sigfault._addr = 0; 369 queue_signal(env, info.si_signo, &info); 370 } 371 break; 372 case EXCP0E_PAGE: 373 info.si_signo = SIGSEGV; 374 info.si_errno = 0; 375 if (!(env->error_code & 1)) 376 info.si_code = TARGET_SEGV_MAPERR; 377 else 378 info.si_code = TARGET_SEGV_ACCERR; 379 info._sifields._sigfault._addr = env->cr[2]; 380 queue_signal(env, info.si_signo, &info); 381 break; 382 case EXCP00_DIVZ: 383 #ifndef TARGET_X86_64 384 if (env->eflags & VM_MASK) { 385 handle_vm86_trap(env, trapnr); 386 } else 387 #endif 388 { 389 /* division by zero */ 390 info.si_signo = SIGFPE; 391 info.si_errno = 0; 392 info.si_code = TARGET_FPE_INTDIV; 393 info._sifields._sigfault._addr = env->eip; 394 queue_signal(env, info.si_signo, &info); 395 } 396 break; 397 case EXCP01_DB: 398 case EXCP03_INT3: 399 #ifndef TARGET_X86_64 400 if (env->eflags & VM_MASK) { 401 handle_vm86_trap(env, trapnr); 402 } else 403 #endif 404 { 405 info.si_signo = SIGTRAP; 406 info.si_errno = 0; 407 if (trapnr == EXCP01_DB) { 408 info.si_code = TARGET_TRAP_BRKPT; 409 info._sifields._sigfault._addr = env->eip; 410 } else { 411 info.si_code = TARGET_SI_KERNEL; 412 info._sifields._sigfault._addr = 0; 413 } 414 queue_signal(env, info.si_signo, &info); 415 } 416 break; 417 case EXCP04_INTO: 418 case EXCP05_BOUND: 419 #ifndef TARGET_X86_64 420 if (env->eflags & VM_MASK) { 421 handle_vm86_trap(env, trapnr); 422 } else 423 #endif 424 { 425 info.si_signo = SIGSEGV; 426 info.si_errno = 0; 427 info.si_code = TARGET_SI_KERNEL; 428 info._sifields._sigfault._addr = 0; 429 queue_signal(env, info.si_signo, &info); 430 } 431 break; 432 case EXCP06_ILLOP: 433 info.si_signo = SIGILL; 434 info.si_errno = 0; 435 info.si_code = TARGET_ILL_ILLOPN; 436 info._sifields._sigfault._addr = env->eip; 437 queue_signal(env, info.si_signo, &info); 438 break; 439 case EXCP_INTERRUPT: 440 /* just indicate that signals should be handled asap */ 441 break; 442 case EXCP_DEBUG: 443 { 444 int sig; 445 446 sig = gdb_handlesig (env, TARGET_SIGTRAP); 447 if (sig) 448 { 449 info.si_signo = sig; 450 info.si_errno = 0; 451 info.si_code = TARGET_TRAP_BRKPT; 452 queue_signal(env, info.si_signo, &info); 453 } 454 } 455 break; 456 default: 457 pc = env->segs[R_CS].base + env->eip; 458 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 459 (long)pc, trapnr); 460 abort(); 461 } 462 process_pending_signals(env); 463 } 464 } 465 #endif 466 467 #ifdef TARGET_ARM 468 469 #define get_user_code_u32(x, gaddr, doswap) \ 470 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 471 if (!__r && (doswap)) { \ 472 (x) = bswap32(x); \ 473 } \ 474 __r; \ 475 }) 476 477 #define get_user_code_u16(x, gaddr, doswap) \ 478 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 479 if (!__r && (doswap)) { \ 480 (x) = bswap16(x); \ 481 } \ 482 __r; \ 483 }) 484 485 /* 486 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 487 * Input: 488 * r0 = pointer to oldval 489 * r1 = pointer to newval 490 * r2 = pointer to target value 491 * 492 * Output: 493 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 494 * C set if *ptr was changed, clear if no exchange happened 495 * 496 * Note segv's in kernel helpers are a bit tricky, we can set the 497 * data address sensibly but the PC address is just the entry point. 498 */ 499 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 500 { 501 uint64_t oldval, newval, val; 502 uint32_t addr, cpsr; 503 target_siginfo_t info; 504 505 /* Based on the 32 bit code in do_kernel_trap */ 506 507 /* XXX: This only works between threads, not between processes. 508 It's probably possible to implement this with native host 509 operations. However things like ldrex/strex are much harder so 510 there's not much point trying. */ 511 start_exclusive(); 512 cpsr = cpsr_read(env); 513 addr = env->regs[2]; 514 515 if (get_user_u64(oldval, env->regs[0])) { 516 env->cp15.c6_data = env->regs[0]; 517 goto segv; 518 }; 519 520 if (get_user_u64(newval, env->regs[1])) { 521 env->cp15.c6_data = env->regs[1]; 522 goto segv; 523 }; 524 525 if (get_user_u64(val, addr)) { 526 env->cp15.c6_data = addr; 527 goto segv; 528 } 529 530 if (val == oldval) { 531 val = newval; 532 533 if (put_user_u64(val, addr)) { 534 env->cp15.c6_data = addr; 535 goto segv; 536 }; 537 538 env->regs[0] = 0; 539 cpsr |= CPSR_C; 540 } else { 541 env->regs[0] = -1; 542 cpsr &= ~CPSR_C; 543 } 544 cpsr_write(env, cpsr, CPSR_C); 545 end_exclusive(); 546 return; 547 548 segv: 549 end_exclusive(); 550 /* We get the PC of the entry address - which is as good as anything, 551 on a real kernel what you get depends on which mode it uses. */ 552 info.si_signo = SIGSEGV; 553 info.si_errno = 0; 554 /* XXX: check env->error_code */ 555 info.si_code = TARGET_SEGV_MAPERR; 556 info._sifields._sigfault._addr = env->cp15.c6_data; 557 queue_signal(env, info.si_signo, &info); 558 559 end_exclusive(); 560 } 561 562 /* Handle a jump to the kernel code page. */ 563 static int 564 do_kernel_trap(CPUARMState *env) 565 { 566 uint32_t addr; 567 uint32_t cpsr; 568 uint32_t val; 569 570 switch (env->regs[15]) { 571 case 0xffff0fa0: /* __kernel_memory_barrier */ 572 /* ??? No-op. Will need to do better for SMP. */ 573 break; 574 case 0xffff0fc0: /* __kernel_cmpxchg */ 575 /* XXX: This only works between threads, not between processes. 576 It's probably possible to implement this with native host 577 operations. However things like ldrex/strex are much harder so 578 there's not much point trying. */ 579 start_exclusive(); 580 cpsr = cpsr_read(env); 581 addr = env->regs[2]; 582 /* FIXME: This should SEGV if the access fails. */ 583 if (get_user_u32(val, addr)) 584 val = ~env->regs[0]; 585 if (val == env->regs[0]) { 586 val = env->regs[1]; 587 /* FIXME: Check for segfaults. */ 588 put_user_u32(val, addr); 589 env->regs[0] = 0; 590 cpsr |= CPSR_C; 591 } else { 592 env->regs[0] = -1; 593 cpsr &= ~CPSR_C; 594 } 595 cpsr_write(env, cpsr, CPSR_C); 596 end_exclusive(); 597 break; 598 case 0xffff0fe0: /* __kernel_get_tls */ 599 env->regs[0] = env->cp15.c13_tls2; 600 break; 601 case 0xffff0f60: /* __kernel_cmpxchg64 */ 602 arm_kernel_cmpxchg64_helper(env); 603 break; 604 605 default: 606 return 1; 607 } 608 /* Jump back to the caller. */ 609 addr = env->regs[14]; 610 if (addr & 1) { 611 env->thumb = 1; 612 addr &= ~1; 613 } 614 env->regs[15] = addr; 615 616 return 0; 617 } 618 619 static int do_strex(CPUARMState *env) 620 { 621 uint32_t val; 622 int size; 623 int rc = 1; 624 int segv = 0; 625 uint32_t addr; 626 start_exclusive(); 627 addr = env->exclusive_addr; 628 if (addr != env->exclusive_test) { 629 goto fail; 630 } 631 size = env->exclusive_info & 0xf; 632 switch (size) { 633 case 0: 634 segv = get_user_u8(val, addr); 635 break; 636 case 1: 637 segv = get_user_u16(val, addr); 638 break; 639 case 2: 640 case 3: 641 segv = get_user_u32(val, addr); 642 break; 643 default: 644 abort(); 645 } 646 if (segv) { 647 env->cp15.c6_data = addr; 648 goto done; 649 } 650 if (val != env->exclusive_val) { 651 goto fail; 652 } 653 if (size == 3) { 654 segv = get_user_u32(val, addr + 4); 655 if (segv) { 656 env->cp15.c6_data = addr + 4; 657 goto done; 658 } 659 if (val != env->exclusive_high) { 660 goto fail; 661 } 662 } 663 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 664 switch (size) { 665 case 0: 666 segv = put_user_u8(val, addr); 667 break; 668 case 1: 669 segv = put_user_u16(val, addr); 670 break; 671 case 2: 672 case 3: 673 segv = put_user_u32(val, addr); 674 break; 675 } 676 if (segv) { 677 env->cp15.c6_data = addr; 678 goto done; 679 } 680 if (size == 3) { 681 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 682 segv = put_user_u32(val, addr + 4); 683 if (segv) { 684 env->cp15.c6_data = addr + 4; 685 goto done; 686 } 687 } 688 rc = 0; 689 fail: 690 env->regs[15] += 4; 691 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 692 done: 693 end_exclusive(); 694 return segv; 695 } 696 697 void cpu_loop(CPUARMState *env) 698 { 699 CPUState *cs = CPU(arm_env_get_cpu(env)); 700 int trapnr; 701 unsigned int n, insn; 702 target_siginfo_t info; 703 uint32_t addr; 704 705 for(;;) { 706 cpu_exec_start(cs); 707 trapnr = cpu_arm_exec(env); 708 cpu_exec_end(cs); 709 switch(trapnr) { 710 case EXCP_UDEF: 711 { 712 TaskState *ts = env->opaque; 713 uint32_t opcode; 714 int rc; 715 716 /* we handle the FPU emulation here, as Linux */ 717 /* we get the opcode */ 718 /* FIXME - what to do if get_user() fails? */ 719 get_user_code_u32(opcode, env->regs[15], env->bswap_code); 720 721 rc = EmulateAll(opcode, &ts->fpa, env); 722 if (rc == 0) { /* illegal instruction */ 723 info.si_signo = SIGILL; 724 info.si_errno = 0; 725 info.si_code = TARGET_ILL_ILLOPN; 726 info._sifields._sigfault._addr = env->regs[15]; 727 queue_signal(env, info.si_signo, &info); 728 } else if (rc < 0) { /* FP exception */ 729 int arm_fpe=0; 730 731 /* translate softfloat flags to FPSR flags */ 732 if (-rc & float_flag_invalid) 733 arm_fpe |= BIT_IOC; 734 if (-rc & float_flag_divbyzero) 735 arm_fpe |= BIT_DZC; 736 if (-rc & float_flag_overflow) 737 arm_fpe |= BIT_OFC; 738 if (-rc & float_flag_underflow) 739 arm_fpe |= BIT_UFC; 740 if (-rc & float_flag_inexact) 741 arm_fpe |= BIT_IXC; 742 743 FPSR fpsr = ts->fpa.fpsr; 744 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 745 746 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 747 info.si_signo = SIGFPE; 748 info.si_errno = 0; 749 750 /* ordered by priority, least first */ 751 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 752 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 753 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 754 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 755 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 756 757 info._sifields._sigfault._addr = env->regs[15]; 758 queue_signal(env, info.si_signo, &info); 759 } else { 760 env->regs[15] += 4; 761 } 762 763 /* accumulate unenabled exceptions */ 764 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 765 fpsr |= BIT_IXC; 766 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 767 fpsr |= BIT_UFC; 768 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 769 fpsr |= BIT_OFC; 770 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 771 fpsr |= BIT_DZC; 772 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 773 fpsr |= BIT_IOC; 774 ts->fpa.fpsr=fpsr; 775 } else { /* everything OK */ 776 /* increment PC */ 777 env->regs[15] += 4; 778 } 779 } 780 break; 781 case EXCP_SWI: 782 case EXCP_BKPT: 783 { 784 env->eabi = 1; 785 /* system call */ 786 if (trapnr == EXCP_BKPT) { 787 if (env->thumb) { 788 /* FIXME - what to do if get_user() fails? */ 789 get_user_code_u16(insn, env->regs[15], env->bswap_code); 790 n = insn & 0xff; 791 env->regs[15] += 2; 792 } else { 793 /* FIXME - what to do if get_user() fails? */ 794 get_user_code_u32(insn, env->regs[15], env->bswap_code); 795 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 796 env->regs[15] += 4; 797 } 798 } else { 799 if (env->thumb) { 800 /* FIXME - what to do if get_user() fails? */ 801 get_user_code_u16(insn, env->regs[15] - 2, 802 env->bswap_code); 803 n = insn & 0xff; 804 } else { 805 /* FIXME - what to do if get_user() fails? */ 806 get_user_code_u32(insn, env->regs[15] - 4, 807 env->bswap_code); 808 n = insn & 0xffffff; 809 } 810 } 811 812 if (n == ARM_NR_cacheflush) { 813 /* nop */ 814 } else if (n == ARM_NR_semihosting 815 || n == ARM_NR_thumb_semihosting) { 816 env->regs[0] = do_arm_semihosting (env); 817 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 818 /* linux syscall */ 819 if (env->thumb || n == 0) { 820 n = env->regs[7]; 821 } else { 822 n -= ARM_SYSCALL_BASE; 823 env->eabi = 0; 824 } 825 if ( n > ARM_NR_BASE) { 826 switch (n) { 827 case ARM_NR_cacheflush: 828 /* nop */ 829 break; 830 case ARM_NR_set_tls: 831 cpu_set_tls(env, env->regs[0]); 832 env->regs[0] = 0; 833 break; 834 default: 835 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 836 n); 837 env->regs[0] = -TARGET_ENOSYS; 838 break; 839 } 840 } else { 841 env->regs[0] = do_syscall(env, 842 n, 843 env->regs[0], 844 env->regs[1], 845 env->regs[2], 846 env->regs[3], 847 env->regs[4], 848 env->regs[5], 849 0, 0); 850 } 851 } else { 852 goto error; 853 } 854 } 855 break; 856 case EXCP_INTERRUPT: 857 /* just indicate that signals should be handled asap */ 858 break; 859 case EXCP_PREFETCH_ABORT: 860 addr = env->cp15.c6_insn; 861 goto do_segv; 862 case EXCP_DATA_ABORT: 863 addr = env->cp15.c6_data; 864 do_segv: 865 { 866 info.si_signo = SIGSEGV; 867 info.si_errno = 0; 868 /* XXX: check env->error_code */ 869 info.si_code = TARGET_SEGV_MAPERR; 870 info._sifields._sigfault._addr = addr; 871 queue_signal(env, info.si_signo, &info); 872 } 873 break; 874 case EXCP_DEBUG: 875 { 876 int sig; 877 878 sig = gdb_handlesig (env, TARGET_SIGTRAP); 879 if (sig) 880 { 881 info.si_signo = sig; 882 info.si_errno = 0; 883 info.si_code = TARGET_TRAP_BRKPT; 884 queue_signal(env, info.si_signo, &info); 885 } 886 } 887 break; 888 case EXCP_KERNEL_TRAP: 889 if (do_kernel_trap(env)) 890 goto error; 891 break; 892 case EXCP_STREX: 893 if (do_strex(env)) { 894 addr = env->cp15.c6_data; 895 goto do_segv; 896 } 897 break; 898 default: 899 error: 900 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 901 trapnr); 902 cpu_dump_state(cs, stderr, fprintf, 0); 903 abort(); 904 } 905 process_pending_signals(env); 906 } 907 } 908 909 #endif 910 911 #ifdef TARGET_UNICORE32 912 913 void cpu_loop(CPUUniCore32State *env) 914 { 915 CPUState *cs = CPU(uc32_env_get_cpu(env)); 916 int trapnr; 917 unsigned int n, insn; 918 target_siginfo_t info; 919 920 for (;;) { 921 cpu_exec_start(cs); 922 trapnr = uc32_cpu_exec(env); 923 cpu_exec_end(cs); 924 switch (trapnr) { 925 case UC32_EXCP_PRIV: 926 { 927 /* system call */ 928 get_user_u32(insn, env->regs[31] - 4); 929 n = insn & 0xffffff; 930 931 if (n >= UC32_SYSCALL_BASE) { 932 /* linux syscall */ 933 n -= UC32_SYSCALL_BASE; 934 if (n == UC32_SYSCALL_NR_set_tls) { 935 cpu_set_tls(env, env->regs[0]); 936 env->regs[0] = 0; 937 } else { 938 env->regs[0] = do_syscall(env, 939 n, 940 env->regs[0], 941 env->regs[1], 942 env->regs[2], 943 env->regs[3], 944 env->regs[4], 945 env->regs[5], 946 0, 0); 947 } 948 } else { 949 goto error; 950 } 951 } 952 break; 953 case UC32_EXCP_DTRAP: 954 case UC32_EXCP_ITRAP: 955 info.si_signo = SIGSEGV; 956 info.si_errno = 0; 957 /* XXX: check env->error_code */ 958 info.si_code = TARGET_SEGV_MAPERR; 959 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 960 queue_signal(env, info.si_signo, &info); 961 break; 962 case EXCP_INTERRUPT: 963 /* just indicate that signals should be handled asap */ 964 break; 965 case EXCP_DEBUG: 966 { 967 int sig; 968 969 sig = gdb_handlesig(env, TARGET_SIGTRAP); 970 if (sig) { 971 info.si_signo = sig; 972 info.si_errno = 0; 973 info.si_code = TARGET_TRAP_BRKPT; 974 queue_signal(env, info.si_signo, &info); 975 } 976 } 977 break; 978 default: 979 goto error; 980 } 981 process_pending_signals(env); 982 } 983 984 error: 985 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 986 cpu_dump_state(cs, stderr, fprintf, 0); 987 abort(); 988 } 989 #endif 990 991 #ifdef TARGET_SPARC 992 #define SPARC64_STACK_BIAS 2047 993 994 //#define DEBUG_WIN 995 996 /* WARNING: dealing with register windows _is_ complicated. More info 997 can be found at http://www.sics.se/~psm/sparcstack.html */ 998 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 999 { 1000 index = (index + cwp * 16) % (16 * env->nwindows); 1001 /* wrap handling : if cwp is on the last window, then we use the 1002 registers 'after' the end */ 1003 if (index < 8 && env->cwp == env->nwindows - 1) 1004 index += 16 * env->nwindows; 1005 return index; 1006 } 1007 1008 /* save the register window 'cwp1' */ 1009 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1010 { 1011 unsigned int i; 1012 abi_ulong sp_ptr; 1013 1014 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1015 #ifdef TARGET_SPARC64 1016 if (sp_ptr & 3) 1017 sp_ptr += SPARC64_STACK_BIAS; 1018 #endif 1019 #if defined(DEBUG_WIN) 1020 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1021 sp_ptr, cwp1); 1022 #endif 1023 for(i = 0; i < 16; i++) { 1024 /* FIXME - what to do if put_user() fails? */ 1025 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1026 sp_ptr += sizeof(abi_ulong); 1027 } 1028 } 1029 1030 static void save_window(CPUSPARCState *env) 1031 { 1032 #ifndef TARGET_SPARC64 1033 unsigned int new_wim; 1034 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1035 ((1LL << env->nwindows) - 1); 1036 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1037 env->wim = new_wim; 1038 #else 1039 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1040 env->cansave++; 1041 env->canrestore--; 1042 #endif 1043 } 1044 1045 static void restore_window(CPUSPARCState *env) 1046 { 1047 #ifndef TARGET_SPARC64 1048 unsigned int new_wim; 1049 #endif 1050 unsigned int i, cwp1; 1051 abi_ulong sp_ptr; 1052 1053 #ifndef TARGET_SPARC64 1054 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1055 ((1LL << env->nwindows) - 1); 1056 #endif 1057 1058 /* restore the invalid window */ 1059 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1060 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1061 #ifdef TARGET_SPARC64 1062 if (sp_ptr & 3) 1063 sp_ptr += SPARC64_STACK_BIAS; 1064 #endif 1065 #if defined(DEBUG_WIN) 1066 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1067 sp_ptr, cwp1); 1068 #endif 1069 for(i = 0; i < 16; i++) { 1070 /* FIXME - what to do if get_user() fails? */ 1071 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1072 sp_ptr += sizeof(abi_ulong); 1073 } 1074 #ifdef TARGET_SPARC64 1075 env->canrestore++; 1076 if (env->cleanwin < env->nwindows - 1) 1077 env->cleanwin++; 1078 env->cansave--; 1079 #else 1080 env->wim = new_wim; 1081 #endif 1082 } 1083 1084 static void flush_windows(CPUSPARCState *env) 1085 { 1086 int offset, cwp1; 1087 1088 offset = 1; 1089 for(;;) { 1090 /* if restore would invoke restore_window(), then we can stop */ 1091 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1092 #ifndef TARGET_SPARC64 1093 if (env->wim & (1 << cwp1)) 1094 break; 1095 #else 1096 if (env->canrestore == 0) 1097 break; 1098 env->cansave++; 1099 env->canrestore--; 1100 #endif 1101 save_window_offset(env, cwp1); 1102 offset++; 1103 } 1104 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1105 #ifndef TARGET_SPARC64 1106 /* set wim so that restore will reload the registers */ 1107 env->wim = 1 << cwp1; 1108 #endif 1109 #if defined(DEBUG_WIN) 1110 printf("flush_windows: nb=%d\n", offset - 1); 1111 #endif 1112 } 1113 1114 void cpu_loop (CPUSPARCState *env) 1115 { 1116 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1117 int trapnr; 1118 abi_long ret; 1119 target_siginfo_t info; 1120 1121 while (1) { 1122 trapnr = cpu_sparc_exec (env); 1123 1124 /* Compute PSR before exposing state. */ 1125 if (env->cc_op != CC_OP_FLAGS) { 1126 cpu_get_psr(env); 1127 } 1128 1129 switch (trapnr) { 1130 #ifndef TARGET_SPARC64 1131 case 0x88: 1132 case 0x90: 1133 #else 1134 case 0x110: 1135 case 0x16d: 1136 #endif 1137 ret = do_syscall (env, env->gregs[1], 1138 env->regwptr[0], env->regwptr[1], 1139 env->regwptr[2], env->regwptr[3], 1140 env->regwptr[4], env->regwptr[5], 1141 0, 0); 1142 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1143 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1144 env->xcc |= PSR_CARRY; 1145 #else 1146 env->psr |= PSR_CARRY; 1147 #endif 1148 ret = -ret; 1149 } else { 1150 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1151 env->xcc &= ~PSR_CARRY; 1152 #else 1153 env->psr &= ~PSR_CARRY; 1154 #endif 1155 } 1156 env->regwptr[0] = ret; 1157 /* next instruction */ 1158 env->pc = env->npc; 1159 env->npc = env->npc + 4; 1160 break; 1161 case 0x83: /* flush windows */ 1162 #ifdef TARGET_ABI32 1163 case 0x103: 1164 #endif 1165 flush_windows(env); 1166 /* next instruction */ 1167 env->pc = env->npc; 1168 env->npc = env->npc + 4; 1169 break; 1170 #ifndef TARGET_SPARC64 1171 case TT_WIN_OVF: /* window overflow */ 1172 save_window(env); 1173 break; 1174 case TT_WIN_UNF: /* window underflow */ 1175 restore_window(env); 1176 break; 1177 case TT_TFAULT: 1178 case TT_DFAULT: 1179 { 1180 info.si_signo = TARGET_SIGSEGV; 1181 info.si_errno = 0; 1182 /* XXX: check env->error_code */ 1183 info.si_code = TARGET_SEGV_MAPERR; 1184 info._sifields._sigfault._addr = env->mmuregs[4]; 1185 queue_signal(env, info.si_signo, &info); 1186 } 1187 break; 1188 #else 1189 case TT_SPILL: /* window overflow */ 1190 save_window(env); 1191 break; 1192 case TT_FILL: /* window underflow */ 1193 restore_window(env); 1194 break; 1195 case TT_TFAULT: 1196 case TT_DFAULT: 1197 { 1198 info.si_signo = TARGET_SIGSEGV; 1199 info.si_errno = 0; 1200 /* XXX: check env->error_code */ 1201 info.si_code = TARGET_SEGV_MAPERR; 1202 if (trapnr == TT_DFAULT) 1203 info._sifields._sigfault._addr = env->dmmuregs[4]; 1204 else 1205 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1206 queue_signal(env, info.si_signo, &info); 1207 } 1208 break; 1209 #ifndef TARGET_ABI32 1210 case 0x16e: 1211 flush_windows(env); 1212 sparc64_get_context(env); 1213 break; 1214 case 0x16f: 1215 flush_windows(env); 1216 sparc64_set_context(env); 1217 break; 1218 #endif 1219 #endif 1220 case EXCP_INTERRUPT: 1221 /* just indicate that signals should be handled asap */ 1222 break; 1223 case TT_ILL_INSN: 1224 { 1225 info.si_signo = TARGET_SIGILL; 1226 info.si_errno = 0; 1227 info.si_code = TARGET_ILL_ILLOPC; 1228 info._sifields._sigfault._addr = env->pc; 1229 queue_signal(env, info.si_signo, &info); 1230 } 1231 break; 1232 case EXCP_DEBUG: 1233 { 1234 int sig; 1235 1236 sig = gdb_handlesig (env, TARGET_SIGTRAP); 1237 if (sig) 1238 { 1239 info.si_signo = sig; 1240 info.si_errno = 0; 1241 info.si_code = TARGET_TRAP_BRKPT; 1242 queue_signal(env, info.si_signo, &info); 1243 } 1244 } 1245 break; 1246 default: 1247 printf ("Unhandled trap: 0x%x\n", trapnr); 1248 cpu_dump_state(cs, stderr, fprintf, 0); 1249 exit (1); 1250 } 1251 process_pending_signals (env); 1252 } 1253 } 1254 1255 #endif 1256 1257 #ifdef TARGET_PPC 1258 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1259 { 1260 /* TO FIX */ 1261 return 0; 1262 } 1263 1264 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1265 { 1266 return cpu_ppc_get_tb(env); 1267 } 1268 1269 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1270 { 1271 return cpu_ppc_get_tb(env) >> 32; 1272 } 1273 1274 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1275 { 1276 return cpu_ppc_get_tb(env); 1277 } 1278 1279 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1280 { 1281 return cpu_ppc_get_tb(env) >> 32; 1282 } 1283 1284 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1285 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1286 1287 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1288 { 1289 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1290 } 1291 1292 /* XXX: to be fixed */ 1293 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1294 { 1295 return -1; 1296 } 1297 1298 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1299 { 1300 return -1; 1301 } 1302 1303 #define EXCP_DUMP(env, fmt, ...) \ 1304 do { \ 1305 CPUState *cs = ENV_GET_CPU(env); \ 1306 fprintf(stderr, fmt , ## __VA_ARGS__); \ 1307 cpu_dump_state(cs, stderr, fprintf, 0); \ 1308 qemu_log(fmt, ## __VA_ARGS__); \ 1309 if (qemu_log_enabled()) { \ 1310 log_cpu_state(cs, 0); \ 1311 } \ 1312 } while (0) 1313 1314 static int do_store_exclusive(CPUPPCState *env) 1315 { 1316 target_ulong addr; 1317 target_ulong page_addr; 1318 target_ulong val; 1319 int flags; 1320 int segv = 0; 1321 1322 addr = env->reserve_ea; 1323 page_addr = addr & TARGET_PAGE_MASK; 1324 start_exclusive(); 1325 mmap_lock(); 1326 flags = page_get_flags(page_addr); 1327 if ((flags & PAGE_READ) == 0) { 1328 segv = 1; 1329 } else { 1330 int reg = env->reserve_info & 0x1f; 1331 int size = (env->reserve_info >> 5) & 0xf; 1332 int stored = 0; 1333 1334 if (addr == env->reserve_addr) { 1335 switch (size) { 1336 case 1: segv = get_user_u8(val, addr); break; 1337 case 2: segv = get_user_u16(val, addr); break; 1338 case 4: segv = get_user_u32(val, addr); break; 1339 #if defined(TARGET_PPC64) 1340 case 8: segv = get_user_u64(val, addr); break; 1341 #endif 1342 default: abort(); 1343 } 1344 if (!segv && val == env->reserve_val) { 1345 val = env->gpr[reg]; 1346 switch (size) { 1347 case 1: segv = put_user_u8(val, addr); break; 1348 case 2: segv = put_user_u16(val, addr); break; 1349 case 4: segv = put_user_u32(val, addr); break; 1350 #if defined(TARGET_PPC64) 1351 case 8: segv = put_user_u64(val, addr); break; 1352 #endif 1353 default: abort(); 1354 } 1355 if (!segv) { 1356 stored = 1; 1357 } 1358 } 1359 } 1360 env->crf[0] = (stored << 1) | xer_so; 1361 env->reserve_addr = (target_ulong)-1; 1362 } 1363 if (!segv) { 1364 env->nip += 4; 1365 } 1366 mmap_unlock(); 1367 end_exclusive(); 1368 return segv; 1369 } 1370 1371 void cpu_loop(CPUPPCState *env) 1372 { 1373 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1374 target_siginfo_t info; 1375 int trapnr; 1376 target_ulong ret; 1377 1378 for(;;) { 1379 cpu_exec_start(cs); 1380 trapnr = cpu_ppc_exec(env); 1381 cpu_exec_end(cs); 1382 switch(trapnr) { 1383 case POWERPC_EXCP_NONE: 1384 /* Just go on */ 1385 break; 1386 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1387 cpu_abort(env, "Critical interrupt while in user mode. " 1388 "Aborting\n"); 1389 break; 1390 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1391 cpu_abort(env, "Machine check exception while in user mode. " 1392 "Aborting\n"); 1393 break; 1394 case POWERPC_EXCP_DSI: /* Data storage exception */ 1395 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", 1396 env->spr[SPR_DAR]); 1397 /* XXX: check this. Seems bugged */ 1398 switch (env->error_code & 0xFF000000) { 1399 case 0x40000000: 1400 info.si_signo = TARGET_SIGSEGV; 1401 info.si_errno = 0; 1402 info.si_code = TARGET_SEGV_MAPERR; 1403 break; 1404 case 0x04000000: 1405 info.si_signo = TARGET_SIGILL; 1406 info.si_errno = 0; 1407 info.si_code = TARGET_ILL_ILLADR; 1408 break; 1409 case 0x08000000: 1410 info.si_signo = TARGET_SIGSEGV; 1411 info.si_errno = 0; 1412 info.si_code = TARGET_SEGV_ACCERR; 1413 break; 1414 default: 1415 /* Let's send a regular segfault... */ 1416 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1417 env->error_code); 1418 info.si_signo = TARGET_SIGSEGV; 1419 info.si_errno = 0; 1420 info.si_code = TARGET_SEGV_MAPERR; 1421 break; 1422 } 1423 info._sifields._sigfault._addr = env->nip; 1424 queue_signal(env, info.si_signo, &info); 1425 break; 1426 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1427 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx 1428 "\n", env->spr[SPR_SRR0]); 1429 /* XXX: check this */ 1430 switch (env->error_code & 0xFF000000) { 1431 case 0x40000000: 1432 info.si_signo = TARGET_SIGSEGV; 1433 info.si_errno = 0; 1434 info.si_code = TARGET_SEGV_MAPERR; 1435 break; 1436 case 0x10000000: 1437 case 0x08000000: 1438 info.si_signo = TARGET_SIGSEGV; 1439 info.si_errno = 0; 1440 info.si_code = TARGET_SEGV_ACCERR; 1441 break; 1442 default: 1443 /* Let's send a regular segfault... */ 1444 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1445 env->error_code); 1446 info.si_signo = TARGET_SIGSEGV; 1447 info.si_errno = 0; 1448 info.si_code = TARGET_SEGV_MAPERR; 1449 break; 1450 } 1451 info._sifields._sigfault._addr = env->nip - 4; 1452 queue_signal(env, info.si_signo, &info); 1453 break; 1454 case POWERPC_EXCP_EXTERNAL: /* External input */ 1455 cpu_abort(env, "External interrupt while in user mode. " 1456 "Aborting\n"); 1457 break; 1458 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1459 EXCP_DUMP(env, "Unaligned memory access\n"); 1460 /* XXX: check this */ 1461 info.si_signo = TARGET_SIGBUS; 1462 info.si_errno = 0; 1463 info.si_code = TARGET_BUS_ADRALN; 1464 info._sifields._sigfault._addr = env->nip - 4; 1465 queue_signal(env, info.si_signo, &info); 1466 break; 1467 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1468 /* XXX: check this */ 1469 switch (env->error_code & ~0xF) { 1470 case POWERPC_EXCP_FP: 1471 EXCP_DUMP(env, "Floating point program exception\n"); 1472 info.si_signo = TARGET_SIGFPE; 1473 info.si_errno = 0; 1474 switch (env->error_code & 0xF) { 1475 case POWERPC_EXCP_FP_OX: 1476 info.si_code = TARGET_FPE_FLTOVF; 1477 break; 1478 case POWERPC_EXCP_FP_UX: 1479 info.si_code = TARGET_FPE_FLTUND; 1480 break; 1481 case POWERPC_EXCP_FP_ZX: 1482 case POWERPC_EXCP_FP_VXZDZ: 1483 info.si_code = TARGET_FPE_FLTDIV; 1484 break; 1485 case POWERPC_EXCP_FP_XX: 1486 info.si_code = TARGET_FPE_FLTRES; 1487 break; 1488 case POWERPC_EXCP_FP_VXSOFT: 1489 info.si_code = TARGET_FPE_FLTINV; 1490 break; 1491 case POWERPC_EXCP_FP_VXSNAN: 1492 case POWERPC_EXCP_FP_VXISI: 1493 case POWERPC_EXCP_FP_VXIDI: 1494 case POWERPC_EXCP_FP_VXIMZ: 1495 case POWERPC_EXCP_FP_VXVC: 1496 case POWERPC_EXCP_FP_VXSQRT: 1497 case POWERPC_EXCP_FP_VXCVI: 1498 info.si_code = TARGET_FPE_FLTSUB; 1499 break; 1500 default: 1501 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1502 env->error_code); 1503 break; 1504 } 1505 break; 1506 case POWERPC_EXCP_INVAL: 1507 EXCP_DUMP(env, "Invalid instruction\n"); 1508 info.si_signo = TARGET_SIGILL; 1509 info.si_errno = 0; 1510 switch (env->error_code & 0xF) { 1511 case POWERPC_EXCP_INVAL_INVAL: 1512 info.si_code = TARGET_ILL_ILLOPC; 1513 break; 1514 case POWERPC_EXCP_INVAL_LSWX: 1515 info.si_code = TARGET_ILL_ILLOPN; 1516 break; 1517 case POWERPC_EXCP_INVAL_SPR: 1518 info.si_code = TARGET_ILL_PRVREG; 1519 break; 1520 case POWERPC_EXCP_INVAL_FP: 1521 info.si_code = TARGET_ILL_COPROC; 1522 break; 1523 default: 1524 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1525 env->error_code & 0xF); 1526 info.si_code = TARGET_ILL_ILLADR; 1527 break; 1528 } 1529 break; 1530 case POWERPC_EXCP_PRIV: 1531 EXCP_DUMP(env, "Privilege violation\n"); 1532 info.si_signo = TARGET_SIGILL; 1533 info.si_errno = 0; 1534 switch (env->error_code & 0xF) { 1535 case POWERPC_EXCP_PRIV_OPC: 1536 info.si_code = TARGET_ILL_PRVOPC; 1537 break; 1538 case POWERPC_EXCP_PRIV_REG: 1539 info.si_code = TARGET_ILL_PRVREG; 1540 break; 1541 default: 1542 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1543 env->error_code & 0xF); 1544 info.si_code = TARGET_ILL_PRVOPC; 1545 break; 1546 } 1547 break; 1548 case POWERPC_EXCP_TRAP: 1549 cpu_abort(env, "Tried to call a TRAP\n"); 1550 break; 1551 default: 1552 /* Should not happen ! */ 1553 cpu_abort(env, "Unknown program exception (%02x)\n", 1554 env->error_code); 1555 break; 1556 } 1557 info._sifields._sigfault._addr = env->nip - 4; 1558 queue_signal(env, info.si_signo, &info); 1559 break; 1560 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1561 EXCP_DUMP(env, "No floating point allowed\n"); 1562 info.si_signo = TARGET_SIGILL; 1563 info.si_errno = 0; 1564 info.si_code = TARGET_ILL_COPROC; 1565 info._sifields._sigfault._addr = env->nip - 4; 1566 queue_signal(env, info.si_signo, &info); 1567 break; 1568 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1569 cpu_abort(env, "Syscall exception while in user mode. " 1570 "Aborting\n"); 1571 break; 1572 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1573 EXCP_DUMP(env, "No APU instruction allowed\n"); 1574 info.si_signo = TARGET_SIGILL; 1575 info.si_errno = 0; 1576 info.si_code = TARGET_ILL_COPROC; 1577 info._sifields._sigfault._addr = env->nip - 4; 1578 queue_signal(env, info.si_signo, &info); 1579 break; 1580 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1581 cpu_abort(env, "Decrementer interrupt while in user mode. " 1582 "Aborting\n"); 1583 break; 1584 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1585 cpu_abort(env, "Fix interval timer interrupt while in user mode. " 1586 "Aborting\n"); 1587 break; 1588 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1589 cpu_abort(env, "Watchdog timer interrupt while in user mode. " 1590 "Aborting\n"); 1591 break; 1592 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1593 cpu_abort(env, "Data TLB exception while in user mode. " 1594 "Aborting\n"); 1595 break; 1596 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1597 cpu_abort(env, "Instruction TLB exception while in user mode. " 1598 "Aborting\n"); 1599 break; 1600 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1601 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); 1602 info.si_signo = TARGET_SIGILL; 1603 info.si_errno = 0; 1604 info.si_code = TARGET_ILL_COPROC; 1605 info._sifields._sigfault._addr = env->nip - 4; 1606 queue_signal(env, info.si_signo, &info); 1607 break; 1608 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1609 cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); 1610 break; 1611 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1612 cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); 1613 break; 1614 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1615 cpu_abort(env, "Performance monitor exception not handled\n"); 1616 break; 1617 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1618 cpu_abort(env, "Doorbell interrupt while in user mode. " 1619 "Aborting\n"); 1620 break; 1621 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1622 cpu_abort(env, "Doorbell critical interrupt while in user mode. " 1623 "Aborting\n"); 1624 break; 1625 case POWERPC_EXCP_RESET: /* System reset exception */ 1626 cpu_abort(env, "Reset interrupt while in user mode. " 1627 "Aborting\n"); 1628 break; 1629 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1630 cpu_abort(env, "Data segment exception while in user mode. " 1631 "Aborting\n"); 1632 break; 1633 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1634 cpu_abort(env, "Instruction segment exception " 1635 "while in user mode. Aborting\n"); 1636 break; 1637 /* PowerPC 64 with hypervisor mode support */ 1638 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1639 cpu_abort(env, "Hypervisor decrementer interrupt " 1640 "while in user mode. Aborting\n"); 1641 break; 1642 case POWERPC_EXCP_TRACE: /* Trace exception */ 1643 /* Nothing to do: 1644 * we use this exception to emulate step-by-step execution mode. 1645 */ 1646 break; 1647 /* PowerPC 64 with hypervisor mode support */ 1648 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1649 cpu_abort(env, "Hypervisor data storage exception " 1650 "while in user mode. Aborting\n"); 1651 break; 1652 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1653 cpu_abort(env, "Hypervisor instruction storage exception " 1654 "while in user mode. Aborting\n"); 1655 break; 1656 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1657 cpu_abort(env, "Hypervisor data segment exception " 1658 "while in user mode. Aborting\n"); 1659 break; 1660 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1661 cpu_abort(env, "Hypervisor instruction segment exception " 1662 "while in user mode. Aborting\n"); 1663 break; 1664 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1665 EXCP_DUMP(env, "No Altivec instructions allowed\n"); 1666 info.si_signo = TARGET_SIGILL; 1667 info.si_errno = 0; 1668 info.si_code = TARGET_ILL_COPROC; 1669 info._sifields._sigfault._addr = env->nip - 4; 1670 queue_signal(env, info.si_signo, &info); 1671 break; 1672 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1673 cpu_abort(env, "Programmable interval timer interrupt " 1674 "while in user mode. Aborting\n"); 1675 break; 1676 case POWERPC_EXCP_IO: /* IO error exception */ 1677 cpu_abort(env, "IO error exception while in user mode. " 1678 "Aborting\n"); 1679 break; 1680 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1681 cpu_abort(env, "Run mode exception while in user mode. " 1682 "Aborting\n"); 1683 break; 1684 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1685 cpu_abort(env, "Emulation trap exception not handled\n"); 1686 break; 1687 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1688 cpu_abort(env, "Instruction fetch TLB exception " 1689 "while in user-mode. Aborting"); 1690 break; 1691 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1692 cpu_abort(env, "Data load TLB exception while in user-mode. " 1693 "Aborting"); 1694 break; 1695 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1696 cpu_abort(env, "Data store TLB exception while in user-mode. " 1697 "Aborting"); 1698 break; 1699 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1700 cpu_abort(env, "Floating-point assist exception not handled\n"); 1701 break; 1702 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1703 cpu_abort(env, "Instruction address breakpoint exception " 1704 "not handled\n"); 1705 break; 1706 case POWERPC_EXCP_SMI: /* System management interrupt */ 1707 cpu_abort(env, "System management interrupt while in user mode. " 1708 "Aborting\n"); 1709 break; 1710 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1711 cpu_abort(env, "Thermal interrupt interrupt while in user mode. " 1712 "Aborting\n"); 1713 break; 1714 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1715 cpu_abort(env, "Performance monitor exception not handled\n"); 1716 break; 1717 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1718 cpu_abort(env, "Vector assist exception not handled\n"); 1719 break; 1720 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1721 cpu_abort(env, "Soft patch exception not handled\n"); 1722 break; 1723 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1724 cpu_abort(env, "Maintenance exception while in user mode. " 1725 "Aborting\n"); 1726 break; 1727 case POWERPC_EXCP_STOP: /* stop translation */ 1728 /* We did invalidate the instruction cache. Go on */ 1729 break; 1730 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1731 /* We just stopped because of a branch. Go on */ 1732 break; 1733 case POWERPC_EXCP_SYSCALL_USER: 1734 /* system call in user-mode emulation */ 1735 /* WARNING: 1736 * PPC ABI uses overflow flag in cr0 to signal an error 1737 * in syscalls. 1738 */ 1739 env->crf[0] &= ~0x1; 1740 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1741 env->gpr[5], env->gpr[6], env->gpr[7], 1742 env->gpr[8], 0, 0); 1743 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1744 /* Returning from a successful sigreturn syscall. 1745 Avoid corrupting register state. */ 1746 break; 1747 } 1748 if (ret > (target_ulong)(-515)) { 1749 env->crf[0] |= 0x1; 1750 ret = -ret; 1751 } 1752 env->gpr[3] = ret; 1753 break; 1754 case POWERPC_EXCP_STCX: 1755 if (do_store_exclusive(env)) { 1756 info.si_signo = TARGET_SIGSEGV; 1757 info.si_errno = 0; 1758 info.si_code = TARGET_SEGV_MAPERR; 1759 info._sifields._sigfault._addr = env->nip; 1760 queue_signal(env, info.si_signo, &info); 1761 } 1762 break; 1763 case EXCP_DEBUG: 1764 { 1765 int sig; 1766 1767 sig = gdb_handlesig(env, TARGET_SIGTRAP); 1768 if (sig) { 1769 info.si_signo = sig; 1770 info.si_errno = 0; 1771 info.si_code = TARGET_TRAP_BRKPT; 1772 queue_signal(env, info.si_signo, &info); 1773 } 1774 } 1775 break; 1776 case EXCP_INTERRUPT: 1777 /* just indicate that signals should be handled asap */ 1778 break; 1779 default: 1780 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); 1781 break; 1782 } 1783 process_pending_signals(env); 1784 } 1785 } 1786 #endif 1787 1788 #ifdef TARGET_MIPS 1789 1790 # ifdef TARGET_ABI_MIPSO32 1791 # define MIPS_SYS(name, args) args, 1792 static const uint8_t mips_syscall_args[] = { 1793 MIPS_SYS(sys_syscall , 8) /* 4000 */ 1794 MIPS_SYS(sys_exit , 1) 1795 MIPS_SYS(sys_fork , 0) 1796 MIPS_SYS(sys_read , 3) 1797 MIPS_SYS(sys_write , 3) 1798 MIPS_SYS(sys_open , 3) /* 4005 */ 1799 MIPS_SYS(sys_close , 1) 1800 MIPS_SYS(sys_waitpid , 3) 1801 MIPS_SYS(sys_creat , 2) 1802 MIPS_SYS(sys_link , 2) 1803 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1804 MIPS_SYS(sys_execve , 0) 1805 MIPS_SYS(sys_chdir , 1) 1806 MIPS_SYS(sys_time , 1) 1807 MIPS_SYS(sys_mknod , 3) 1808 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1809 MIPS_SYS(sys_lchown , 3) 1810 MIPS_SYS(sys_ni_syscall , 0) 1811 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1812 MIPS_SYS(sys_lseek , 3) 1813 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1814 MIPS_SYS(sys_mount , 5) 1815 MIPS_SYS(sys_oldumount , 1) 1816 MIPS_SYS(sys_setuid , 1) 1817 MIPS_SYS(sys_getuid , 0) 1818 MIPS_SYS(sys_stime , 1) /* 4025 */ 1819 MIPS_SYS(sys_ptrace , 4) 1820 MIPS_SYS(sys_alarm , 1) 1821 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1822 MIPS_SYS(sys_pause , 0) 1823 MIPS_SYS(sys_utime , 2) /* 4030 */ 1824 MIPS_SYS(sys_ni_syscall , 0) 1825 MIPS_SYS(sys_ni_syscall , 0) 1826 MIPS_SYS(sys_access , 2) 1827 MIPS_SYS(sys_nice , 1) 1828 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 1829 MIPS_SYS(sys_sync , 0) 1830 MIPS_SYS(sys_kill , 2) 1831 MIPS_SYS(sys_rename , 2) 1832 MIPS_SYS(sys_mkdir , 2) 1833 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 1834 MIPS_SYS(sys_dup , 1) 1835 MIPS_SYS(sys_pipe , 0) 1836 MIPS_SYS(sys_times , 1) 1837 MIPS_SYS(sys_ni_syscall , 0) 1838 MIPS_SYS(sys_brk , 1) /* 4045 */ 1839 MIPS_SYS(sys_setgid , 1) 1840 MIPS_SYS(sys_getgid , 0) 1841 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 1842 MIPS_SYS(sys_geteuid , 0) 1843 MIPS_SYS(sys_getegid , 0) /* 4050 */ 1844 MIPS_SYS(sys_acct , 0) 1845 MIPS_SYS(sys_umount , 2) 1846 MIPS_SYS(sys_ni_syscall , 0) 1847 MIPS_SYS(sys_ioctl , 3) 1848 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 1849 MIPS_SYS(sys_ni_syscall , 2) 1850 MIPS_SYS(sys_setpgid , 2) 1851 MIPS_SYS(sys_ni_syscall , 0) 1852 MIPS_SYS(sys_olduname , 1) 1853 MIPS_SYS(sys_umask , 1) /* 4060 */ 1854 MIPS_SYS(sys_chroot , 1) 1855 MIPS_SYS(sys_ustat , 2) 1856 MIPS_SYS(sys_dup2 , 2) 1857 MIPS_SYS(sys_getppid , 0) 1858 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 1859 MIPS_SYS(sys_setsid , 0) 1860 MIPS_SYS(sys_sigaction , 3) 1861 MIPS_SYS(sys_sgetmask , 0) 1862 MIPS_SYS(sys_ssetmask , 1) 1863 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 1864 MIPS_SYS(sys_setregid , 2) 1865 MIPS_SYS(sys_sigsuspend , 0) 1866 MIPS_SYS(sys_sigpending , 1) 1867 MIPS_SYS(sys_sethostname , 2) 1868 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 1869 MIPS_SYS(sys_getrlimit , 2) 1870 MIPS_SYS(sys_getrusage , 2) 1871 MIPS_SYS(sys_gettimeofday, 2) 1872 MIPS_SYS(sys_settimeofday, 2) 1873 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 1874 MIPS_SYS(sys_setgroups , 2) 1875 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 1876 MIPS_SYS(sys_symlink , 2) 1877 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 1878 MIPS_SYS(sys_readlink , 3) /* 4085 */ 1879 MIPS_SYS(sys_uselib , 1) 1880 MIPS_SYS(sys_swapon , 2) 1881 MIPS_SYS(sys_reboot , 3) 1882 MIPS_SYS(old_readdir , 3) 1883 MIPS_SYS(old_mmap , 6) /* 4090 */ 1884 MIPS_SYS(sys_munmap , 2) 1885 MIPS_SYS(sys_truncate , 2) 1886 MIPS_SYS(sys_ftruncate , 2) 1887 MIPS_SYS(sys_fchmod , 2) 1888 MIPS_SYS(sys_fchown , 3) /* 4095 */ 1889 MIPS_SYS(sys_getpriority , 2) 1890 MIPS_SYS(sys_setpriority , 3) 1891 MIPS_SYS(sys_ni_syscall , 0) 1892 MIPS_SYS(sys_statfs , 2) 1893 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 1894 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 1895 MIPS_SYS(sys_socketcall , 2) 1896 MIPS_SYS(sys_syslog , 3) 1897 MIPS_SYS(sys_setitimer , 3) 1898 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 1899 MIPS_SYS(sys_newstat , 2) 1900 MIPS_SYS(sys_newlstat , 2) 1901 MIPS_SYS(sys_newfstat , 2) 1902 MIPS_SYS(sys_uname , 1) 1903 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 1904 MIPS_SYS(sys_vhangup , 0) 1905 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 1906 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 1907 MIPS_SYS(sys_wait4 , 4) 1908 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 1909 MIPS_SYS(sys_sysinfo , 1) 1910 MIPS_SYS(sys_ipc , 6) 1911 MIPS_SYS(sys_fsync , 1) 1912 MIPS_SYS(sys_sigreturn , 0) 1913 MIPS_SYS(sys_clone , 6) /* 4120 */ 1914 MIPS_SYS(sys_setdomainname, 2) 1915 MIPS_SYS(sys_newuname , 1) 1916 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 1917 MIPS_SYS(sys_adjtimex , 1) 1918 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 1919 MIPS_SYS(sys_sigprocmask , 3) 1920 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 1921 MIPS_SYS(sys_init_module , 5) 1922 MIPS_SYS(sys_delete_module, 1) 1923 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 1924 MIPS_SYS(sys_quotactl , 0) 1925 MIPS_SYS(sys_getpgid , 1) 1926 MIPS_SYS(sys_fchdir , 1) 1927 MIPS_SYS(sys_bdflush , 2) 1928 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 1929 MIPS_SYS(sys_personality , 1) 1930 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 1931 MIPS_SYS(sys_setfsuid , 1) 1932 MIPS_SYS(sys_setfsgid , 1) 1933 MIPS_SYS(sys_llseek , 5) /* 4140 */ 1934 MIPS_SYS(sys_getdents , 3) 1935 MIPS_SYS(sys_select , 5) 1936 MIPS_SYS(sys_flock , 2) 1937 MIPS_SYS(sys_msync , 3) 1938 MIPS_SYS(sys_readv , 3) /* 4145 */ 1939 MIPS_SYS(sys_writev , 3) 1940 MIPS_SYS(sys_cacheflush , 3) 1941 MIPS_SYS(sys_cachectl , 3) 1942 MIPS_SYS(sys_sysmips , 4) 1943 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 1944 MIPS_SYS(sys_getsid , 1) 1945 MIPS_SYS(sys_fdatasync , 0) 1946 MIPS_SYS(sys_sysctl , 1) 1947 MIPS_SYS(sys_mlock , 2) 1948 MIPS_SYS(sys_munlock , 2) /* 4155 */ 1949 MIPS_SYS(sys_mlockall , 1) 1950 MIPS_SYS(sys_munlockall , 0) 1951 MIPS_SYS(sys_sched_setparam, 2) 1952 MIPS_SYS(sys_sched_getparam, 2) 1953 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 1954 MIPS_SYS(sys_sched_getscheduler, 1) 1955 MIPS_SYS(sys_sched_yield , 0) 1956 MIPS_SYS(sys_sched_get_priority_max, 1) 1957 MIPS_SYS(sys_sched_get_priority_min, 1) 1958 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 1959 MIPS_SYS(sys_nanosleep, 2) 1960 MIPS_SYS(sys_mremap , 4) 1961 MIPS_SYS(sys_accept , 3) 1962 MIPS_SYS(sys_bind , 3) 1963 MIPS_SYS(sys_connect , 3) /* 4170 */ 1964 MIPS_SYS(sys_getpeername , 3) 1965 MIPS_SYS(sys_getsockname , 3) 1966 MIPS_SYS(sys_getsockopt , 5) 1967 MIPS_SYS(sys_listen , 2) 1968 MIPS_SYS(sys_recv , 4) /* 4175 */ 1969 MIPS_SYS(sys_recvfrom , 6) 1970 MIPS_SYS(sys_recvmsg , 3) 1971 MIPS_SYS(sys_send , 4) 1972 MIPS_SYS(sys_sendmsg , 3) 1973 MIPS_SYS(sys_sendto , 6) /* 4180 */ 1974 MIPS_SYS(sys_setsockopt , 5) 1975 MIPS_SYS(sys_shutdown , 2) 1976 MIPS_SYS(sys_socket , 3) 1977 MIPS_SYS(sys_socketpair , 4) 1978 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 1979 MIPS_SYS(sys_getresuid , 3) 1980 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 1981 MIPS_SYS(sys_poll , 3) 1982 MIPS_SYS(sys_nfsservctl , 3) 1983 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 1984 MIPS_SYS(sys_getresgid , 3) 1985 MIPS_SYS(sys_prctl , 5) 1986 MIPS_SYS(sys_rt_sigreturn, 0) 1987 MIPS_SYS(sys_rt_sigaction, 4) 1988 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 1989 MIPS_SYS(sys_rt_sigpending, 2) 1990 MIPS_SYS(sys_rt_sigtimedwait, 4) 1991 MIPS_SYS(sys_rt_sigqueueinfo, 3) 1992 MIPS_SYS(sys_rt_sigsuspend, 0) 1993 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 1994 MIPS_SYS(sys_pwrite64 , 6) 1995 MIPS_SYS(sys_chown , 3) 1996 MIPS_SYS(sys_getcwd , 2) 1997 MIPS_SYS(sys_capget , 2) 1998 MIPS_SYS(sys_capset , 2) /* 4205 */ 1999 MIPS_SYS(sys_sigaltstack , 2) 2000 MIPS_SYS(sys_sendfile , 4) 2001 MIPS_SYS(sys_ni_syscall , 0) 2002 MIPS_SYS(sys_ni_syscall , 0) 2003 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2004 MIPS_SYS(sys_truncate64 , 4) 2005 MIPS_SYS(sys_ftruncate64 , 4) 2006 MIPS_SYS(sys_stat64 , 2) 2007 MIPS_SYS(sys_lstat64 , 2) 2008 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2009 MIPS_SYS(sys_pivot_root , 2) 2010 MIPS_SYS(sys_mincore , 3) 2011 MIPS_SYS(sys_madvise , 3) 2012 MIPS_SYS(sys_getdents64 , 3) 2013 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2014 MIPS_SYS(sys_ni_syscall , 0) 2015 MIPS_SYS(sys_gettid , 0) 2016 MIPS_SYS(sys_readahead , 5) 2017 MIPS_SYS(sys_setxattr , 5) 2018 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2019 MIPS_SYS(sys_fsetxattr , 5) 2020 MIPS_SYS(sys_getxattr , 4) 2021 MIPS_SYS(sys_lgetxattr , 4) 2022 MIPS_SYS(sys_fgetxattr , 4) 2023 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2024 MIPS_SYS(sys_llistxattr , 3) 2025 MIPS_SYS(sys_flistxattr , 3) 2026 MIPS_SYS(sys_removexattr , 2) 2027 MIPS_SYS(sys_lremovexattr, 2) 2028 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2029 MIPS_SYS(sys_tkill , 2) 2030 MIPS_SYS(sys_sendfile64 , 5) 2031 MIPS_SYS(sys_futex , 2) 2032 MIPS_SYS(sys_sched_setaffinity, 3) 2033 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2034 MIPS_SYS(sys_io_setup , 2) 2035 MIPS_SYS(sys_io_destroy , 1) 2036 MIPS_SYS(sys_io_getevents, 5) 2037 MIPS_SYS(sys_io_submit , 3) 2038 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2039 MIPS_SYS(sys_exit_group , 1) 2040 MIPS_SYS(sys_lookup_dcookie, 3) 2041 MIPS_SYS(sys_epoll_create, 1) 2042 MIPS_SYS(sys_epoll_ctl , 4) 2043 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2044 MIPS_SYS(sys_remap_file_pages, 5) 2045 MIPS_SYS(sys_set_tid_address, 1) 2046 MIPS_SYS(sys_restart_syscall, 0) 2047 MIPS_SYS(sys_fadvise64_64, 7) 2048 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2049 MIPS_SYS(sys_fstatfs64 , 2) 2050 MIPS_SYS(sys_timer_create, 3) 2051 MIPS_SYS(sys_timer_settime, 4) 2052 MIPS_SYS(sys_timer_gettime, 2) 2053 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2054 MIPS_SYS(sys_timer_delete, 1) 2055 MIPS_SYS(sys_clock_settime, 2) 2056 MIPS_SYS(sys_clock_gettime, 2) 2057 MIPS_SYS(sys_clock_getres, 2) 2058 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2059 MIPS_SYS(sys_tgkill , 3) 2060 MIPS_SYS(sys_utimes , 2) 2061 MIPS_SYS(sys_mbind , 4) 2062 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2063 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2064 MIPS_SYS(sys_mq_open , 4) 2065 MIPS_SYS(sys_mq_unlink , 1) 2066 MIPS_SYS(sys_mq_timedsend, 5) 2067 MIPS_SYS(sys_mq_timedreceive, 5) 2068 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2069 MIPS_SYS(sys_mq_getsetattr, 3) 2070 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2071 MIPS_SYS(sys_waitid , 4) 2072 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2073 MIPS_SYS(sys_add_key , 5) 2074 MIPS_SYS(sys_request_key, 4) 2075 MIPS_SYS(sys_keyctl , 5) 2076 MIPS_SYS(sys_set_thread_area, 1) 2077 MIPS_SYS(sys_inotify_init, 0) 2078 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2079 MIPS_SYS(sys_inotify_rm_watch, 2) 2080 MIPS_SYS(sys_migrate_pages, 4) 2081 MIPS_SYS(sys_openat, 4) 2082 MIPS_SYS(sys_mkdirat, 3) 2083 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2084 MIPS_SYS(sys_fchownat, 5) 2085 MIPS_SYS(sys_futimesat, 3) 2086 MIPS_SYS(sys_fstatat64, 4) 2087 MIPS_SYS(sys_unlinkat, 3) 2088 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2089 MIPS_SYS(sys_linkat, 5) 2090 MIPS_SYS(sys_symlinkat, 3) 2091 MIPS_SYS(sys_readlinkat, 4) 2092 MIPS_SYS(sys_fchmodat, 3) 2093 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2094 MIPS_SYS(sys_pselect6, 6) 2095 MIPS_SYS(sys_ppoll, 5) 2096 MIPS_SYS(sys_unshare, 1) 2097 MIPS_SYS(sys_splice, 4) 2098 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2099 MIPS_SYS(sys_tee, 4) 2100 MIPS_SYS(sys_vmsplice, 4) 2101 MIPS_SYS(sys_move_pages, 6) 2102 MIPS_SYS(sys_set_robust_list, 2) 2103 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2104 MIPS_SYS(sys_kexec_load, 4) 2105 MIPS_SYS(sys_getcpu, 3) 2106 MIPS_SYS(sys_epoll_pwait, 6) 2107 MIPS_SYS(sys_ioprio_set, 3) 2108 MIPS_SYS(sys_ioprio_get, 2) 2109 MIPS_SYS(sys_utimensat, 4) 2110 MIPS_SYS(sys_signalfd, 3) 2111 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2112 MIPS_SYS(sys_eventfd, 1) 2113 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2114 MIPS_SYS(sys_timerfd_create, 2) 2115 MIPS_SYS(sys_timerfd_gettime, 2) 2116 MIPS_SYS(sys_timerfd_settime, 4) 2117 MIPS_SYS(sys_signalfd4, 4) 2118 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2119 MIPS_SYS(sys_epoll_create1, 1) 2120 MIPS_SYS(sys_dup3, 3) 2121 MIPS_SYS(sys_pipe2, 2) 2122 MIPS_SYS(sys_inotify_init1, 1) 2123 MIPS_SYS(sys_preadv, 6) /* 4330 */ 2124 MIPS_SYS(sys_pwritev, 6) 2125 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2126 MIPS_SYS(sys_perf_event_open, 5) 2127 MIPS_SYS(sys_accept4, 4) 2128 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2129 MIPS_SYS(sys_fanotify_init, 2) 2130 MIPS_SYS(sys_fanotify_mark, 6) 2131 MIPS_SYS(sys_prlimit64, 4) 2132 MIPS_SYS(sys_name_to_handle_at, 5) 2133 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2134 MIPS_SYS(sys_clock_adjtime, 2) 2135 MIPS_SYS(sys_syncfs, 1) 2136 }; 2137 # undef MIPS_SYS 2138 # endif /* O32 */ 2139 2140 static int do_store_exclusive(CPUMIPSState *env) 2141 { 2142 target_ulong addr; 2143 target_ulong page_addr; 2144 target_ulong val; 2145 int flags; 2146 int segv = 0; 2147 int reg; 2148 int d; 2149 2150 addr = env->lladdr; 2151 page_addr = addr & TARGET_PAGE_MASK; 2152 start_exclusive(); 2153 mmap_lock(); 2154 flags = page_get_flags(page_addr); 2155 if ((flags & PAGE_READ) == 0) { 2156 segv = 1; 2157 } else { 2158 reg = env->llreg & 0x1f; 2159 d = (env->llreg & 0x20) != 0; 2160 if (d) { 2161 segv = get_user_s64(val, addr); 2162 } else { 2163 segv = get_user_s32(val, addr); 2164 } 2165 if (!segv) { 2166 if (val != env->llval) { 2167 env->active_tc.gpr[reg] = 0; 2168 } else { 2169 if (d) { 2170 segv = put_user_u64(env->llnewval, addr); 2171 } else { 2172 segv = put_user_u32(env->llnewval, addr); 2173 } 2174 if (!segv) { 2175 env->active_tc.gpr[reg] = 1; 2176 } 2177 } 2178 } 2179 } 2180 env->lladdr = -1; 2181 if (!segv) { 2182 env->active_tc.PC += 4; 2183 } 2184 mmap_unlock(); 2185 end_exclusive(); 2186 return segv; 2187 } 2188 2189 /* Break codes */ 2190 enum { 2191 BRK_OVERFLOW = 6, 2192 BRK_DIVZERO = 7 2193 }; 2194 2195 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2196 unsigned int code) 2197 { 2198 int ret = -1; 2199 2200 switch (code) { 2201 case BRK_OVERFLOW: 2202 case BRK_DIVZERO: 2203 info->si_signo = TARGET_SIGFPE; 2204 info->si_errno = 0; 2205 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2206 queue_signal(env, info->si_signo, &*info); 2207 ret = 0; 2208 break; 2209 default: 2210 break; 2211 } 2212 2213 return ret; 2214 } 2215 2216 void cpu_loop(CPUMIPSState *env) 2217 { 2218 CPUState *cs = CPU(mips_env_get_cpu(env)); 2219 target_siginfo_t info; 2220 int trapnr; 2221 abi_long ret; 2222 # ifdef TARGET_ABI_MIPSO32 2223 unsigned int syscall_num; 2224 # endif 2225 2226 for(;;) { 2227 cpu_exec_start(cs); 2228 trapnr = cpu_mips_exec(env); 2229 cpu_exec_end(cs); 2230 switch(trapnr) { 2231 case EXCP_SYSCALL: 2232 env->active_tc.PC += 4; 2233 # ifdef TARGET_ABI_MIPSO32 2234 syscall_num = env->active_tc.gpr[2] - 4000; 2235 if (syscall_num >= sizeof(mips_syscall_args)) { 2236 ret = -TARGET_ENOSYS; 2237 } else { 2238 int nb_args; 2239 abi_ulong sp_reg; 2240 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2241 2242 nb_args = mips_syscall_args[syscall_num]; 2243 sp_reg = env->active_tc.gpr[29]; 2244 switch (nb_args) { 2245 /* these arguments are taken from the stack */ 2246 case 8: 2247 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2248 goto done_syscall; 2249 } 2250 case 7: 2251 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2252 goto done_syscall; 2253 } 2254 case 6: 2255 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2256 goto done_syscall; 2257 } 2258 case 5: 2259 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2260 goto done_syscall; 2261 } 2262 default: 2263 break; 2264 } 2265 ret = do_syscall(env, env->active_tc.gpr[2], 2266 env->active_tc.gpr[4], 2267 env->active_tc.gpr[5], 2268 env->active_tc.gpr[6], 2269 env->active_tc.gpr[7], 2270 arg5, arg6, arg7, arg8); 2271 } 2272 done_syscall: 2273 # else 2274 ret = do_syscall(env, env->active_tc.gpr[2], 2275 env->active_tc.gpr[4], env->active_tc.gpr[5], 2276 env->active_tc.gpr[6], env->active_tc.gpr[7], 2277 env->active_tc.gpr[8], env->active_tc.gpr[9], 2278 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2279 # endif /* O32 */ 2280 if (ret == -TARGET_QEMU_ESIGRETURN) { 2281 /* Returning from a successful sigreturn syscall. 2282 Avoid clobbering register state. */ 2283 break; 2284 } 2285 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2286 env->active_tc.gpr[7] = 1; /* error flag */ 2287 ret = -ret; 2288 } else { 2289 env->active_tc.gpr[7] = 0; /* error flag */ 2290 } 2291 env->active_tc.gpr[2] = ret; 2292 break; 2293 case EXCP_TLBL: 2294 case EXCP_TLBS: 2295 case EXCP_AdEL: 2296 case EXCP_AdES: 2297 info.si_signo = TARGET_SIGSEGV; 2298 info.si_errno = 0; 2299 /* XXX: check env->error_code */ 2300 info.si_code = TARGET_SEGV_MAPERR; 2301 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2302 queue_signal(env, info.si_signo, &info); 2303 break; 2304 case EXCP_CpU: 2305 case EXCP_RI: 2306 info.si_signo = TARGET_SIGILL; 2307 info.si_errno = 0; 2308 info.si_code = 0; 2309 queue_signal(env, info.si_signo, &info); 2310 break; 2311 case EXCP_INTERRUPT: 2312 /* just indicate that signals should be handled asap */ 2313 break; 2314 case EXCP_DEBUG: 2315 { 2316 int sig; 2317 2318 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2319 if (sig) 2320 { 2321 info.si_signo = sig; 2322 info.si_errno = 0; 2323 info.si_code = TARGET_TRAP_BRKPT; 2324 queue_signal(env, info.si_signo, &info); 2325 } 2326 } 2327 break; 2328 case EXCP_SC: 2329 if (do_store_exclusive(env)) { 2330 info.si_signo = TARGET_SIGSEGV; 2331 info.si_errno = 0; 2332 info.si_code = TARGET_SEGV_MAPERR; 2333 info._sifields._sigfault._addr = env->active_tc.PC; 2334 queue_signal(env, info.si_signo, &info); 2335 } 2336 break; 2337 case EXCP_DSPDIS: 2338 info.si_signo = TARGET_SIGILL; 2339 info.si_errno = 0; 2340 info.si_code = TARGET_ILL_ILLOPC; 2341 queue_signal(env, info.si_signo, &info); 2342 break; 2343 /* The code below was inspired by the MIPS Linux kernel trap 2344 * handling code in arch/mips/kernel/traps.c. 2345 */ 2346 case EXCP_BREAK: 2347 { 2348 abi_ulong trap_instr; 2349 unsigned int code; 2350 2351 ret = get_user_ual(trap_instr, env->active_tc.PC); 2352 if (ret != 0) { 2353 goto error; 2354 } 2355 2356 /* As described in the original Linux kernel code, the 2357 * below checks on 'code' are to work around an old 2358 * assembly bug. 2359 */ 2360 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2361 if (code >= (1 << 10)) { 2362 code >>= 10; 2363 } 2364 2365 if (do_break(env, &info, code) != 0) { 2366 goto error; 2367 } 2368 } 2369 break; 2370 case EXCP_TRAP: 2371 { 2372 abi_ulong trap_instr; 2373 unsigned int code = 0; 2374 2375 ret = get_user_ual(trap_instr, env->active_tc.PC); 2376 if (ret != 0) { 2377 goto error; 2378 } 2379 2380 /* The immediate versions don't provide a code. */ 2381 if (!(trap_instr & 0xFC000000)) { 2382 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2383 } 2384 2385 if (do_break(env, &info, code) != 0) { 2386 goto error; 2387 } 2388 } 2389 break; 2390 default: 2391 error: 2392 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2393 trapnr); 2394 cpu_dump_state(cs, stderr, fprintf, 0); 2395 abort(); 2396 } 2397 process_pending_signals(env); 2398 } 2399 } 2400 #endif 2401 2402 #ifdef TARGET_OPENRISC 2403 2404 void cpu_loop(CPUOpenRISCState *env) 2405 { 2406 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2407 int trapnr, gdbsig; 2408 2409 for (;;) { 2410 trapnr = cpu_exec(env); 2411 gdbsig = 0; 2412 2413 switch (trapnr) { 2414 case EXCP_RESET: 2415 qemu_log("\nReset request, exit, pc is %#x\n", env->pc); 2416 exit(1); 2417 break; 2418 case EXCP_BUSERR: 2419 qemu_log("\nBus error, exit, pc is %#x\n", env->pc); 2420 gdbsig = SIGBUS; 2421 break; 2422 case EXCP_DPF: 2423 case EXCP_IPF: 2424 cpu_dump_state(cs, stderr, fprintf, 0); 2425 gdbsig = TARGET_SIGSEGV; 2426 break; 2427 case EXCP_TICK: 2428 qemu_log("\nTick time interrupt pc is %#x\n", env->pc); 2429 break; 2430 case EXCP_ALIGN: 2431 qemu_log("\nAlignment pc is %#x\n", env->pc); 2432 gdbsig = SIGBUS; 2433 break; 2434 case EXCP_ILLEGAL: 2435 qemu_log("\nIllegal instructionpc is %#x\n", env->pc); 2436 gdbsig = SIGILL; 2437 break; 2438 case EXCP_INT: 2439 qemu_log("\nExternal interruptpc is %#x\n", env->pc); 2440 break; 2441 case EXCP_DTLBMISS: 2442 case EXCP_ITLBMISS: 2443 qemu_log("\nTLB miss\n"); 2444 break; 2445 case EXCP_RANGE: 2446 qemu_log("\nRange\n"); 2447 gdbsig = SIGSEGV; 2448 break; 2449 case EXCP_SYSCALL: 2450 env->pc += 4; /* 0xc00; */ 2451 env->gpr[11] = do_syscall(env, 2452 env->gpr[11], /* return value */ 2453 env->gpr[3], /* r3 - r7 are params */ 2454 env->gpr[4], 2455 env->gpr[5], 2456 env->gpr[6], 2457 env->gpr[7], 2458 env->gpr[8], 0, 0); 2459 break; 2460 case EXCP_FPE: 2461 qemu_log("\nFloating point error\n"); 2462 break; 2463 case EXCP_TRAP: 2464 qemu_log("\nTrap\n"); 2465 gdbsig = SIGTRAP; 2466 break; 2467 case EXCP_NR: 2468 qemu_log("\nNR\n"); 2469 break; 2470 default: 2471 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n", 2472 trapnr); 2473 cpu_dump_state(cs, stderr, fprintf, 0); 2474 gdbsig = TARGET_SIGILL; 2475 break; 2476 } 2477 if (gdbsig) { 2478 gdb_handlesig(env, gdbsig); 2479 if (gdbsig != TARGET_SIGTRAP) { 2480 exit(1); 2481 } 2482 } 2483 2484 process_pending_signals(env); 2485 } 2486 } 2487 2488 #endif /* TARGET_OPENRISC */ 2489 2490 #ifdef TARGET_SH4 2491 void cpu_loop(CPUSH4State *env) 2492 { 2493 CPUState *cs = CPU(sh_env_get_cpu(env)); 2494 int trapnr, ret; 2495 target_siginfo_t info; 2496 2497 while (1) { 2498 trapnr = cpu_sh4_exec (env); 2499 2500 switch (trapnr) { 2501 case 0x160: 2502 env->pc += 2; 2503 ret = do_syscall(env, 2504 env->gregs[3], 2505 env->gregs[4], 2506 env->gregs[5], 2507 env->gregs[6], 2508 env->gregs[7], 2509 env->gregs[0], 2510 env->gregs[1], 2511 0, 0); 2512 env->gregs[0] = ret; 2513 break; 2514 case EXCP_INTERRUPT: 2515 /* just indicate that signals should be handled asap */ 2516 break; 2517 case EXCP_DEBUG: 2518 { 2519 int sig; 2520 2521 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2522 if (sig) 2523 { 2524 info.si_signo = sig; 2525 info.si_errno = 0; 2526 info.si_code = TARGET_TRAP_BRKPT; 2527 queue_signal(env, info.si_signo, &info); 2528 } 2529 } 2530 break; 2531 case 0xa0: 2532 case 0xc0: 2533 info.si_signo = SIGSEGV; 2534 info.si_errno = 0; 2535 info.si_code = TARGET_SEGV_MAPERR; 2536 info._sifields._sigfault._addr = env->tea; 2537 queue_signal(env, info.si_signo, &info); 2538 break; 2539 2540 default: 2541 printf ("Unhandled trap: 0x%x\n", trapnr); 2542 cpu_dump_state(cs, stderr, fprintf, 0); 2543 exit (1); 2544 } 2545 process_pending_signals (env); 2546 } 2547 } 2548 #endif 2549 2550 #ifdef TARGET_CRIS 2551 void cpu_loop(CPUCRISState *env) 2552 { 2553 CPUState *cs = CPU(cris_env_get_cpu(env)); 2554 int trapnr, ret; 2555 target_siginfo_t info; 2556 2557 while (1) { 2558 trapnr = cpu_cris_exec (env); 2559 switch (trapnr) { 2560 case 0xaa: 2561 { 2562 info.si_signo = SIGSEGV; 2563 info.si_errno = 0; 2564 /* XXX: check env->error_code */ 2565 info.si_code = TARGET_SEGV_MAPERR; 2566 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2567 queue_signal(env, info.si_signo, &info); 2568 } 2569 break; 2570 case EXCP_INTERRUPT: 2571 /* just indicate that signals should be handled asap */ 2572 break; 2573 case EXCP_BREAK: 2574 ret = do_syscall(env, 2575 env->regs[9], 2576 env->regs[10], 2577 env->regs[11], 2578 env->regs[12], 2579 env->regs[13], 2580 env->pregs[7], 2581 env->pregs[11], 2582 0, 0); 2583 env->regs[10] = ret; 2584 break; 2585 case EXCP_DEBUG: 2586 { 2587 int sig; 2588 2589 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2590 if (sig) 2591 { 2592 info.si_signo = sig; 2593 info.si_errno = 0; 2594 info.si_code = TARGET_TRAP_BRKPT; 2595 queue_signal(env, info.si_signo, &info); 2596 } 2597 } 2598 break; 2599 default: 2600 printf ("Unhandled trap: 0x%x\n", trapnr); 2601 cpu_dump_state(cs, stderr, fprintf, 0); 2602 exit (1); 2603 } 2604 process_pending_signals (env); 2605 } 2606 } 2607 #endif 2608 2609 #ifdef TARGET_MICROBLAZE 2610 void cpu_loop(CPUMBState *env) 2611 { 2612 CPUState *cs = CPU(mb_env_get_cpu(env)); 2613 int trapnr, ret; 2614 target_siginfo_t info; 2615 2616 while (1) { 2617 trapnr = cpu_mb_exec (env); 2618 switch (trapnr) { 2619 case 0xaa: 2620 { 2621 info.si_signo = SIGSEGV; 2622 info.si_errno = 0; 2623 /* XXX: check env->error_code */ 2624 info.si_code = TARGET_SEGV_MAPERR; 2625 info._sifields._sigfault._addr = 0; 2626 queue_signal(env, info.si_signo, &info); 2627 } 2628 break; 2629 case EXCP_INTERRUPT: 2630 /* just indicate that signals should be handled asap */ 2631 break; 2632 case EXCP_BREAK: 2633 /* Return address is 4 bytes after the call. */ 2634 env->regs[14] += 4; 2635 env->sregs[SR_PC] = env->regs[14]; 2636 ret = do_syscall(env, 2637 env->regs[12], 2638 env->regs[5], 2639 env->regs[6], 2640 env->regs[7], 2641 env->regs[8], 2642 env->regs[9], 2643 env->regs[10], 2644 0, 0); 2645 env->regs[3] = ret; 2646 break; 2647 case EXCP_HW_EXCP: 2648 env->regs[17] = env->sregs[SR_PC] + 4; 2649 if (env->iflags & D_FLAG) { 2650 env->sregs[SR_ESR] |= 1 << 12; 2651 env->sregs[SR_PC] -= 4; 2652 /* FIXME: if branch was immed, replay the imm as well. */ 2653 } 2654 2655 env->iflags &= ~(IMM_FLAG | D_FLAG); 2656 2657 switch (env->sregs[SR_ESR] & 31) { 2658 case ESR_EC_DIVZERO: 2659 info.si_signo = SIGFPE; 2660 info.si_errno = 0; 2661 info.si_code = TARGET_FPE_FLTDIV; 2662 info._sifields._sigfault._addr = 0; 2663 queue_signal(env, info.si_signo, &info); 2664 break; 2665 case ESR_EC_FPU: 2666 info.si_signo = SIGFPE; 2667 info.si_errno = 0; 2668 if (env->sregs[SR_FSR] & FSR_IO) { 2669 info.si_code = TARGET_FPE_FLTINV; 2670 } 2671 if (env->sregs[SR_FSR] & FSR_DZ) { 2672 info.si_code = TARGET_FPE_FLTDIV; 2673 } 2674 info._sifields._sigfault._addr = 0; 2675 queue_signal(env, info.si_signo, &info); 2676 break; 2677 default: 2678 printf ("Unhandled hw-exception: 0x%x\n", 2679 env->sregs[SR_ESR] & ESR_EC_MASK); 2680 cpu_dump_state(cs, stderr, fprintf, 0); 2681 exit (1); 2682 break; 2683 } 2684 break; 2685 case EXCP_DEBUG: 2686 { 2687 int sig; 2688 2689 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2690 if (sig) 2691 { 2692 info.si_signo = sig; 2693 info.si_errno = 0; 2694 info.si_code = TARGET_TRAP_BRKPT; 2695 queue_signal(env, info.si_signo, &info); 2696 } 2697 } 2698 break; 2699 default: 2700 printf ("Unhandled trap: 0x%x\n", trapnr); 2701 cpu_dump_state(cs, stderr, fprintf, 0); 2702 exit (1); 2703 } 2704 process_pending_signals (env); 2705 } 2706 } 2707 #endif 2708 2709 #ifdef TARGET_M68K 2710 2711 void cpu_loop(CPUM68KState *env) 2712 { 2713 CPUState *cs = CPU(m68k_env_get_cpu(env)); 2714 int trapnr; 2715 unsigned int n; 2716 target_siginfo_t info; 2717 TaskState *ts = env->opaque; 2718 2719 for(;;) { 2720 trapnr = cpu_m68k_exec(env); 2721 switch(trapnr) { 2722 case EXCP_ILLEGAL: 2723 { 2724 if (ts->sim_syscalls) { 2725 uint16_t nr; 2726 nr = lduw(env->pc + 2); 2727 env->pc += 4; 2728 do_m68k_simcall(env, nr); 2729 } else { 2730 goto do_sigill; 2731 } 2732 } 2733 break; 2734 case EXCP_HALT_INSN: 2735 /* Semihosing syscall. */ 2736 env->pc += 4; 2737 do_m68k_semihosting(env, env->dregs[0]); 2738 break; 2739 case EXCP_LINEA: 2740 case EXCP_LINEF: 2741 case EXCP_UNSUPPORTED: 2742 do_sigill: 2743 info.si_signo = SIGILL; 2744 info.si_errno = 0; 2745 info.si_code = TARGET_ILL_ILLOPN; 2746 info._sifields._sigfault._addr = env->pc; 2747 queue_signal(env, info.si_signo, &info); 2748 break; 2749 case EXCP_TRAP0: 2750 { 2751 ts->sim_syscalls = 0; 2752 n = env->dregs[0]; 2753 env->pc += 2; 2754 env->dregs[0] = do_syscall(env, 2755 n, 2756 env->dregs[1], 2757 env->dregs[2], 2758 env->dregs[3], 2759 env->dregs[4], 2760 env->dregs[5], 2761 env->aregs[0], 2762 0, 0); 2763 } 2764 break; 2765 case EXCP_INTERRUPT: 2766 /* just indicate that signals should be handled asap */ 2767 break; 2768 case EXCP_ACCESS: 2769 { 2770 info.si_signo = SIGSEGV; 2771 info.si_errno = 0; 2772 /* XXX: check env->error_code */ 2773 info.si_code = TARGET_SEGV_MAPERR; 2774 info._sifields._sigfault._addr = env->mmu.ar; 2775 queue_signal(env, info.si_signo, &info); 2776 } 2777 break; 2778 case EXCP_DEBUG: 2779 { 2780 int sig; 2781 2782 sig = gdb_handlesig (env, TARGET_SIGTRAP); 2783 if (sig) 2784 { 2785 info.si_signo = sig; 2786 info.si_errno = 0; 2787 info.si_code = TARGET_TRAP_BRKPT; 2788 queue_signal(env, info.si_signo, &info); 2789 } 2790 } 2791 break; 2792 default: 2793 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", 2794 trapnr); 2795 cpu_dump_state(cs, stderr, fprintf, 0); 2796 abort(); 2797 } 2798 process_pending_signals(env); 2799 } 2800 } 2801 #endif /* TARGET_M68K */ 2802 2803 #ifdef TARGET_ALPHA 2804 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 2805 { 2806 target_ulong addr, val, tmp; 2807 target_siginfo_t info; 2808 int ret = 0; 2809 2810 addr = env->lock_addr; 2811 tmp = env->lock_st_addr; 2812 env->lock_addr = -1; 2813 env->lock_st_addr = 0; 2814 2815 start_exclusive(); 2816 mmap_lock(); 2817 2818 if (addr == tmp) { 2819 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 2820 goto do_sigsegv; 2821 } 2822 2823 if (val == env->lock_value) { 2824 tmp = env->ir[reg]; 2825 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 2826 goto do_sigsegv; 2827 } 2828 ret = 1; 2829 } 2830 } 2831 env->ir[reg] = ret; 2832 env->pc += 4; 2833 2834 mmap_unlock(); 2835 end_exclusive(); 2836 return; 2837 2838 do_sigsegv: 2839 mmap_unlock(); 2840 end_exclusive(); 2841 2842 info.si_signo = TARGET_SIGSEGV; 2843 info.si_errno = 0; 2844 info.si_code = TARGET_SEGV_MAPERR; 2845 info._sifields._sigfault._addr = addr; 2846 queue_signal(env, TARGET_SIGSEGV, &info); 2847 } 2848 2849 void cpu_loop(CPUAlphaState *env) 2850 { 2851 CPUState *cs = CPU(alpha_env_get_cpu(env)); 2852 int trapnr; 2853 target_siginfo_t info; 2854 abi_long sysret; 2855 2856 while (1) { 2857 trapnr = cpu_alpha_exec (env); 2858 2859 /* All of the traps imply a transition through PALcode, which 2860 implies an REI instruction has been executed. Which means 2861 that the intr_flag should be cleared. */ 2862 env->intr_flag = 0; 2863 2864 switch (trapnr) { 2865 case EXCP_RESET: 2866 fprintf(stderr, "Reset requested. Exit\n"); 2867 exit(1); 2868 break; 2869 case EXCP_MCHK: 2870 fprintf(stderr, "Machine check exception. Exit\n"); 2871 exit(1); 2872 break; 2873 case EXCP_SMP_INTERRUPT: 2874 case EXCP_CLK_INTERRUPT: 2875 case EXCP_DEV_INTERRUPT: 2876 fprintf(stderr, "External interrupt. Exit\n"); 2877 exit(1); 2878 break; 2879 case EXCP_MMFAULT: 2880 env->lock_addr = -1; 2881 info.si_signo = TARGET_SIGSEGV; 2882 info.si_errno = 0; 2883 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 2884 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 2885 info._sifields._sigfault._addr = env->trap_arg0; 2886 queue_signal(env, info.si_signo, &info); 2887 break; 2888 case EXCP_UNALIGN: 2889 env->lock_addr = -1; 2890 info.si_signo = TARGET_SIGBUS; 2891 info.si_errno = 0; 2892 info.si_code = TARGET_BUS_ADRALN; 2893 info._sifields._sigfault._addr = env->trap_arg0; 2894 queue_signal(env, info.si_signo, &info); 2895 break; 2896 case EXCP_OPCDEC: 2897 do_sigill: 2898 env->lock_addr = -1; 2899 info.si_signo = TARGET_SIGILL; 2900 info.si_errno = 0; 2901 info.si_code = TARGET_ILL_ILLOPC; 2902 info._sifields._sigfault._addr = env->pc; 2903 queue_signal(env, info.si_signo, &info); 2904 break; 2905 case EXCP_ARITH: 2906 env->lock_addr = -1; 2907 info.si_signo = TARGET_SIGFPE; 2908 info.si_errno = 0; 2909 info.si_code = TARGET_FPE_FLTINV; 2910 info._sifields._sigfault._addr = env->pc; 2911 queue_signal(env, info.si_signo, &info); 2912 break; 2913 case EXCP_FEN: 2914 /* No-op. Linux simply re-enables the FPU. */ 2915 break; 2916 case EXCP_CALL_PAL: 2917 env->lock_addr = -1; 2918 switch (env->error_code) { 2919 case 0x80: 2920 /* BPT */ 2921 info.si_signo = TARGET_SIGTRAP; 2922 info.si_errno = 0; 2923 info.si_code = TARGET_TRAP_BRKPT; 2924 info._sifields._sigfault._addr = env->pc; 2925 queue_signal(env, info.si_signo, &info); 2926 break; 2927 case 0x81: 2928 /* BUGCHK */ 2929 info.si_signo = TARGET_SIGTRAP; 2930 info.si_errno = 0; 2931 info.si_code = 0; 2932 info._sifields._sigfault._addr = env->pc; 2933 queue_signal(env, info.si_signo, &info); 2934 break; 2935 case 0x83: 2936 /* CALLSYS */ 2937 trapnr = env->ir[IR_V0]; 2938 sysret = do_syscall(env, trapnr, 2939 env->ir[IR_A0], env->ir[IR_A1], 2940 env->ir[IR_A2], env->ir[IR_A3], 2941 env->ir[IR_A4], env->ir[IR_A5], 2942 0, 0); 2943 if (trapnr == TARGET_NR_sigreturn 2944 || trapnr == TARGET_NR_rt_sigreturn) { 2945 break; 2946 } 2947 /* Syscall writes 0 to V0 to bypass error check, similar 2948 to how this is handled internal to Linux kernel. 2949 (Ab)use trapnr temporarily as boolean indicating error. */ 2950 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 2951 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 2952 env->ir[IR_A3] = trapnr; 2953 break; 2954 case 0x86: 2955 /* IMB */ 2956 /* ??? We can probably elide the code using page_unprotect 2957 that is checking for self-modifying code. Instead we 2958 could simply call tb_flush here. Until we work out the 2959 changes required to turn off the extra write protection, 2960 this can be a no-op. */ 2961 break; 2962 case 0x9E: 2963 /* RDUNIQUE */ 2964 /* Handled in the translator for usermode. */ 2965 abort(); 2966 case 0x9F: 2967 /* WRUNIQUE */ 2968 /* Handled in the translator for usermode. */ 2969 abort(); 2970 case 0xAA: 2971 /* GENTRAP */ 2972 info.si_signo = TARGET_SIGFPE; 2973 switch (env->ir[IR_A0]) { 2974 case TARGET_GEN_INTOVF: 2975 info.si_code = TARGET_FPE_INTOVF; 2976 break; 2977 case TARGET_GEN_INTDIV: 2978 info.si_code = TARGET_FPE_INTDIV; 2979 break; 2980 case TARGET_GEN_FLTOVF: 2981 info.si_code = TARGET_FPE_FLTOVF; 2982 break; 2983 case TARGET_GEN_FLTUND: 2984 info.si_code = TARGET_FPE_FLTUND; 2985 break; 2986 case TARGET_GEN_FLTINV: 2987 info.si_code = TARGET_FPE_FLTINV; 2988 break; 2989 case TARGET_GEN_FLTINE: 2990 info.si_code = TARGET_FPE_FLTRES; 2991 break; 2992 case TARGET_GEN_ROPRAND: 2993 info.si_code = 0; 2994 break; 2995 default: 2996 info.si_signo = TARGET_SIGTRAP; 2997 info.si_code = 0; 2998 break; 2999 } 3000 info.si_errno = 0; 3001 info._sifields._sigfault._addr = env->pc; 3002 queue_signal(env, info.si_signo, &info); 3003 break; 3004 default: 3005 goto do_sigill; 3006 } 3007 break; 3008 case EXCP_DEBUG: 3009 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP); 3010 if (info.si_signo) { 3011 env->lock_addr = -1; 3012 info.si_errno = 0; 3013 info.si_code = TARGET_TRAP_BRKPT; 3014 queue_signal(env, info.si_signo, &info); 3015 } 3016 break; 3017 case EXCP_STL_C: 3018 case EXCP_STQ_C: 3019 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3020 break; 3021 case EXCP_INTERRUPT: 3022 /* Just indicate that signals should be handled asap. */ 3023 break; 3024 default: 3025 printf ("Unhandled trap: 0x%x\n", trapnr); 3026 cpu_dump_state(cs, stderr, fprintf, 0); 3027 exit (1); 3028 } 3029 process_pending_signals (env); 3030 } 3031 } 3032 #endif /* TARGET_ALPHA */ 3033 3034 #ifdef TARGET_S390X 3035 void cpu_loop(CPUS390XState *env) 3036 { 3037 CPUState *cs = CPU(s390_env_get_cpu(env)); 3038 int trapnr, n, sig; 3039 target_siginfo_t info; 3040 target_ulong addr; 3041 3042 while (1) { 3043 trapnr = cpu_s390x_exec(env); 3044 switch (trapnr) { 3045 case EXCP_INTERRUPT: 3046 /* Just indicate that signals should be handled asap. */ 3047 break; 3048 3049 case EXCP_SVC: 3050 n = env->int_svc_code; 3051 if (!n) { 3052 /* syscalls > 255 */ 3053 n = env->regs[1]; 3054 } 3055 env->psw.addr += env->int_svc_ilen; 3056 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], 3057 env->regs[4], env->regs[5], 3058 env->regs[6], env->regs[7], 0, 0); 3059 break; 3060 3061 case EXCP_DEBUG: 3062 sig = gdb_handlesig(env, TARGET_SIGTRAP); 3063 if (sig) { 3064 n = TARGET_TRAP_BRKPT; 3065 goto do_signal_pc; 3066 } 3067 break; 3068 case EXCP_PGM: 3069 n = env->int_pgm_code; 3070 switch (n) { 3071 case PGM_OPERATION: 3072 case PGM_PRIVILEGED: 3073 sig = SIGILL; 3074 n = TARGET_ILL_ILLOPC; 3075 goto do_signal_pc; 3076 case PGM_PROTECTION: 3077 case PGM_ADDRESSING: 3078 sig = SIGSEGV; 3079 /* XXX: check env->error_code */ 3080 n = TARGET_SEGV_MAPERR; 3081 addr = env->__excp_addr; 3082 goto do_signal; 3083 case PGM_EXECUTE: 3084 case PGM_SPECIFICATION: 3085 case PGM_SPECIAL_OP: 3086 case PGM_OPERAND: 3087 do_sigill_opn: 3088 sig = SIGILL; 3089 n = TARGET_ILL_ILLOPN; 3090 goto do_signal_pc; 3091 3092 case PGM_FIXPT_OVERFLOW: 3093 sig = SIGFPE; 3094 n = TARGET_FPE_INTOVF; 3095 goto do_signal_pc; 3096 case PGM_FIXPT_DIVIDE: 3097 sig = SIGFPE; 3098 n = TARGET_FPE_INTDIV; 3099 goto do_signal_pc; 3100 3101 case PGM_DATA: 3102 n = (env->fpc >> 8) & 0xff; 3103 if (n == 0xff) { 3104 /* compare-and-trap */ 3105 goto do_sigill_opn; 3106 } else { 3107 /* An IEEE exception, simulated or otherwise. */ 3108 if (n & 0x80) { 3109 n = TARGET_FPE_FLTINV; 3110 } else if (n & 0x40) { 3111 n = TARGET_FPE_FLTDIV; 3112 } else if (n & 0x20) { 3113 n = TARGET_FPE_FLTOVF; 3114 } else if (n & 0x10) { 3115 n = TARGET_FPE_FLTUND; 3116 } else if (n & 0x08) { 3117 n = TARGET_FPE_FLTRES; 3118 } else { 3119 /* ??? Quantum exception; BFP, DFP error. */ 3120 goto do_sigill_opn; 3121 } 3122 sig = SIGFPE; 3123 goto do_signal_pc; 3124 } 3125 3126 default: 3127 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3128 cpu_dump_state(cs, stderr, fprintf, 0); 3129 exit(1); 3130 } 3131 break; 3132 3133 do_signal_pc: 3134 addr = env->psw.addr; 3135 do_signal: 3136 info.si_signo = sig; 3137 info.si_errno = 0; 3138 info.si_code = n; 3139 info._sifields._sigfault._addr = addr; 3140 queue_signal(env, info.si_signo, &info); 3141 break; 3142 3143 default: 3144 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3145 cpu_dump_state(cs, stderr, fprintf, 0); 3146 exit(1); 3147 } 3148 process_pending_signals (env); 3149 } 3150 } 3151 3152 #endif /* TARGET_S390X */ 3153 3154 THREAD CPUState *thread_cpu; 3155 3156 void task_settid(TaskState *ts) 3157 { 3158 if (ts->ts_tid == 0) { 3159 #ifdef CONFIG_USE_NPTL 3160 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3161 #else 3162 /* when no threads are used, tid becomes pid */ 3163 ts->ts_tid = getpid(); 3164 #endif 3165 } 3166 } 3167 3168 void stop_all_tasks(void) 3169 { 3170 /* 3171 * We trust that when using NPTL, start_exclusive() 3172 * handles thread stopping correctly. 3173 */ 3174 start_exclusive(); 3175 } 3176 3177 /* Assumes contents are already zeroed. */ 3178 void init_task_state(TaskState *ts) 3179 { 3180 int i; 3181 3182 ts->used = 1; 3183 ts->first_free = ts->sigqueue_table; 3184 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { 3185 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; 3186 } 3187 ts->sigqueue_table[i].next = NULL; 3188 } 3189 3190 static void handle_arg_help(const char *arg) 3191 { 3192 usage(); 3193 } 3194 3195 static void handle_arg_log(const char *arg) 3196 { 3197 int mask; 3198 3199 mask = qemu_str_to_log_mask(arg); 3200 if (!mask) { 3201 qemu_print_log_usage(stdout); 3202 exit(1); 3203 } 3204 qemu_set_log(mask); 3205 } 3206 3207 static void handle_arg_log_filename(const char *arg) 3208 { 3209 qemu_set_log_filename(arg); 3210 } 3211 3212 static void handle_arg_set_env(const char *arg) 3213 { 3214 char *r, *p, *token; 3215 r = p = strdup(arg); 3216 while ((token = strsep(&p, ",")) != NULL) { 3217 if (envlist_setenv(envlist, token) != 0) { 3218 usage(); 3219 } 3220 } 3221 free(r); 3222 } 3223 3224 static void handle_arg_unset_env(const char *arg) 3225 { 3226 char *r, *p, *token; 3227 r = p = strdup(arg); 3228 while ((token = strsep(&p, ",")) != NULL) { 3229 if (envlist_unsetenv(envlist, token) != 0) { 3230 usage(); 3231 } 3232 } 3233 free(r); 3234 } 3235 3236 static void handle_arg_argv0(const char *arg) 3237 { 3238 argv0 = strdup(arg); 3239 } 3240 3241 static void handle_arg_stack_size(const char *arg) 3242 { 3243 char *p; 3244 guest_stack_size = strtoul(arg, &p, 0); 3245 if (guest_stack_size == 0) { 3246 usage(); 3247 } 3248 3249 if (*p == 'M') { 3250 guest_stack_size *= 1024 * 1024; 3251 } else if (*p == 'k' || *p == 'K') { 3252 guest_stack_size *= 1024; 3253 } 3254 } 3255 3256 static void handle_arg_ld_prefix(const char *arg) 3257 { 3258 interp_prefix = strdup(arg); 3259 } 3260 3261 static void handle_arg_pagesize(const char *arg) 3262 { 3263 qemu_host_page_size = atoi(arg); 3264 if (qemu_host_page_size == 0 || 3265 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3266 fprintf(stderr, "page size must be a power of two\n"); 3267 exit(1); 3268 } 3269 } 3270 3271 static void handle_arg_gdb(const char *arg) 3272 { 3273 gdbstub_port = atoi(arg); 3274 } 3275 3276 static void handle_arg_uname(const char *arg) 3277 { 3278 qemu_uname_release = strdup(arg); 3279 } 3280 3281 static void handle_arg_cpu(const char *arg) 3282 { 3283 cpu_model = strdup(arg); 3284 if (cpu_model == NULL || is_help_option(cpu_model)) { 3285 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3286 #if defined(cpu_list) 3287 cpu_list(stdout, &fprintf); 3288 #endif 3289 exit(1); 3290 } 3291 } 3292 3293 #if defined(CONFIG_USE_GUEST_BASE) 3294 static void handle_arg_guest_base(const char *arg) 3295 { 3296 guest_base = strtol(arg, NULL, 0); 3297 have_guest_base = 1; 3298 } 3299 3300 static void handle_arg_reserved_va(const char *arg) 3301 { 3302 char *p; 3303 int shift = 0; 3304 reserved_va = strtoul(arg, &p, 0); 3305 switch (*p) { 3306 case 'k': 3307 case 'K': 3308 shift = 10; 3309 break; 3310 case 'M': 3311 shift = 20; 3312 break; 3313 case 'G': 3314 shift = 30; 3315 break; 3316 } 3317 if (shift) { 3318 unsigned long unshifted = reserved_va; 3319 p++; 3320 reserved_va <<= shift; 3321 if (((reserved_va >> shift) != unshifted) 3322 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3323 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3324 #endif 3325 ) { 3326 fprintf(stderr, "Reserved virtual address too big\n"); 3327 exit(1); 3328 } 3329 } 3330 if (*p) { 3331 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3332 exit(1); 3333 } 3334 } 3335 #endif 3336 3337 static void handle_arg_singlestep(const char *arg) 3338 { 3339 singlestep = 1; 3340 } 3341 3342 static void handle_arg_strace(const char *arg) 3343 { 3344 do_strace = 1; 3345 } 3346 3347 static void handle_arg_version(const char *arg) 3348 { 3349 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3350 ", Copyright (c) 2003-2008 Fabrice Bellard\n"); 3351 exit(0); 3352 } 3353 3354 struct qemu_argument { 3355 const char *argv; 3356 const char *env; 3357 bool has_arg; 3358 void (*handle_opt)(const char *arg); 3359 const char *example; 3360 const char *help; 3361 }; 3362 3363 static const struct qemu_argument arg_table[] = { 3364 {"h", "", false, handle_arg_help, 3365 "", "print this help"}, 3366 {"g", "QEMU_GDB", true, handle_arg_gdb, 3367 "port", "wait gdb connection to 'port'"}, 3368 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3369 "path", "set the elf interpreter prefix to 'path'"}, 3370 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3371 "size", "set the stack size to 'size' bytes"}, 3372 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3373 "model", "select CPU (-cpu help for list)"}, 3374 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3375 "var=value", "sets targets environment variable (see below)"}, 3376 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3377 "var", "unsets targets environment variable (see below)"}, 3378 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 3379 "argv0", "forces target process argv[0] to be 'argv0'"}, 3380 {"r", "QEMU_UNAME", true, handle_arg_uname, 3381 "uname", "set qemu uname release string to 'uname'"}, 3382 #if defined(CONFIG_USE_GUEST_BASE) 3383 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 3384 "address", "set guest_base address to 'address'"}, 3385 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 3386 "size", "reserve 'size' bytes for guest virtual address space"}, 3387 #endif 3388 {"d", "QEMU_LOG", true, handle_arg_log, 3389 "item[,...]", "enable logging of specified items " 3390 "(use '-d help' for a list of items)"}, 3391 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 3392 "logfile", "write logs to 'logfile' (default stderr)"}, 3393 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 3394 "pagesize", "set the host page size to 'pagesize'"}, 3395 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 3396 "", "run in singlestep mode"}, 3397 {"strace", "QEMU_STRACE", false, handle_arg_strace, 3398 "", "log system calls"}, 3399 {"version", "QEMU_VERSION", false, handle_arg_version, 3400 "", "display version information and exit"}, 3401 {NULL, NULL, false, NULL, NULL, NULL} 3402 }; 3403 3404 static void usage(void) 3405 { 3406 const struct qemu_argument *arginfo; 3407 int maxarglen; 3408 int maxenvlen; 3409 3410 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 3411 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 3412 "\n" 3413 "Options and associated environment variables:\n" 3414 "\n"); 3415 3416 /* Calculate column widths. We must always have at least enough space 3417 * for the column header. 3418 */ 3419 maxarglen = strlen("Argument"); 3420 maxenvlen = strlen("Env-variable"); 3421 3422 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3423 int arglen = strlen(arginfo->argv); 3424 if (arginfo->has_arg) { 3425 arglen += strlen(arginfo->example) + 1; 3426 } 3427 if (strlen(arginfo->env) > maxenvlen) { 3428 maxenvlen = strlen(arginfo->env); 3429 } 3430 if (arglen > maxarglen) { 3431 maxarglen = arglen; 3432 } 3433 } 3434 3435 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 3436 maxenvlen, "Env-variable"); 3437 3438 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3439 if (arginfo->has_arg) { 3440 printf("-%s %-*s %-*s %s\n", arginfo->argv, 3441 (int)(maxarglen - strlen(arginfo->argv) - 1), 3442 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 3443 } else { 3444 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 3445 maxenvlen, arginfo->env, 3446 arginfo->help); 3447 } 3448 } 3449 3450 printf("\n" 3451 "Defaults:\n" 3452 "QEMU_LD_PREFIX = %s\n" 3453 "QEMU_STACK_SIZE = %ld byte\n", 3454 interp_prefix, 3455 guest_stack_size); 3456 3457 printf("\n" 3458 "You can use -E and -U options or the QEMU_SET_ENV and\n" 3459 "QEMU_UNSET_ENV environment variables to set and unset\n" 3460 "environment variables for the target process.\n" 3461 "It is possible to provide several variables by separating them\n" 3462 "by commas in getsubopt(3) style. Additionally it is possible to\n" 3463 "provide the -E and -U options multiple times.\n" 3464 "The following lines are equivalent:\n" 3465 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 3466 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 3467 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 3468 "Note that if you provide several changes to a single variable\n" 3469 "the last change will stay in effect.\n"); 3470 3471 exit(1); 3472 } 3473 3474 static int parse_args(int argc, char **argv) 3475 { 3476 const char *r; 3477 int optind; 3478 const struct qemu_argument *arginfo; 3479 3480 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3481 if (arginfo->env == NULL) { 3482 continue; 3483 } 3484 3485 r = getenv(arginfo->env); 3486 if (r != NULL) { 3487 arginfo->handle_opt(r); 3488 } 3489 } 3490 3491 optind = 1; 3492 for (;;) { 3493 if (optind >= argc) { 3494 break; 3495 } 3496 r = argv[optind]; 3497 if (r[0] != '-') { 3498 break; 3499 } 3500 optind++; 3501 r++; 3502 if (!strcmp(r, "-")) { 3503 break; 3504 } 3505 3506 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 3507 if (!strcmp(r, arginfo->argv)) { 3508 if (arginfo->has_arg) { 3509 if (optind >= argc) { 3510 usage(); 3511 } 3512 arginfo->handle_opt(argv[optind]); 3513 optind++; 3514 } else { 3515 arginfo->handle_opt(NULL); 3516 } 3517 break; 3518 } 3519 } 3520 3521 /* no option matched the current argv */ 3522 if (arginfo->handle_opt == NULL) { 3523 usage(); 3524 } 3525 } 3526 3527 if (optind >= argc) { 3528 usage(); 3529 } 3530 3531 filename = argv[optind]; 3532 exec_path = argv[optind]; 3533 3534 return optind; 3535 } 3536 3537 int main(int argc, char **argv, char **envp) 3538 { 3539 struct target_pt_regs regs1, *regs = ®s1; 3540 struct image_info info1, *info = &info1; 3541 struct linux_binprm bprm; 3542 TaskState *ts; 3543 CPUArchState *env; 3544 int optind; 3545 char **target_environ, **wrk; 3546 char **target_argv; 3547 int target_argc; 3548 int i; 3549 int ret; 3550 3551 module_call_init(MODULE_INIT_QOM); 3552 3553 qemu_cache_utils_init(envp); 3554 3555 if ((envlist = envlist_create()) == NULL) { 3556 (void) fprintf(stderr, "Unable to allocate envlist\n"); 3557 exit(1); 3558 } 3559 3560 /* add current environment into the list */ 3561 for (wrk = environ; *wrk != NULL; wrk++) { 3562 (void) envlist_setenv(envlist, *wrk); 3563 } 3564 3565 /* Read the stack limit from the kernel. If it's "unlimited", 3566 then we can do little else besides use the default. */ 3567 { 3568 struct rlimit lim; 3569 if (getrlimit(RLIMIT_STACK, &lim) == 0 3570 && lim.rlim_cur != RLIM_INFINITY 3571 && lim.rlim_cur == (target_long)lim.rlim_cur) { 3572 guest_stack_size = lim.rlim_cur; 3573 } 3574 } 3575 3576 cpu_model = NULL; 3577 #if defined(cpudef_setup) 3578 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */ 3579 #endif 3580 3581 optind = parse_args(argc, argv); 3582 3583 /* Zero out regs */ 3584 memset(regs, 0, sizeof(struct target_pt_regs)); 3585 3586 /* Zero out image_info */ 3587 memset(info, 0, sizeof(struct image_info)); 3588 3589 memset(&bprm, 0, sizeof (bprm)); 3590 3591 /* Scan interp_prefix dir for replacement files. */ 3592 init_paths(interp_prefix); 3593 3594 if (cpu_model == NULL) { 3595 #if defined(TARGET_I386) 3596 #ifdef TARGET_X86_64 3597 cpu_model = "qemu64"; 3598 #else 3599 cpu_model = "qemu32"; 3600 #endif 3601 #elif defined(TARGET_ARM) 3602 cpu_model = "any"; 3603 #elif defined(TARGET_UNICORE32) 3604 cpu_model = "any"; 3605 #elif defined(TARGET_M68K) 3606 cpu_model = "any"; 3607 #elif defined(TARGET_SPARC) 3608 #ifdef TARGET_SPARC64 3609 cpu_model = "TI UltraSparc II"; 3610 #else 3611 cpu_model = "Fujitsu MB86904"; 3612 #endif 3613 #elif defined(TARGET_MIPS) 3614 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 3615 cpu_model = "20Kc"; 3616 #else 3617 cpu_model = "24Kf"; 3618 #endif 3619 #elif defined TARGET_OPENRISC 3620 cpu_model = "or1200"; 3621 #elif defined(TARGET_PPC) 3622 #ifdef TARGET_PPC64 3623 cpu_model = "970fx"; 3624 #else 3625 cpu_model = "750"; 3626 #endif 3627 #else 3628 cpu_model = "any"; 3629 #endif 3630 } 3631 tcg_exec_init(0); 3632 cpu_exec_init_all(); 3633 /* NOTE: we need to init the CPU at this stage to get 3634 qemu_host_page_size */ 3635 env = cpu_init(cpu_model); 3636 if (!env) { 3637 fprintf(stderr, "Unable to find CPU definition\n"); 3638 exit(1); 3639 } 3640 #if defined(TARGET_SPARC) || defined(TARGET_PPC) 3641 cpu_reset(ENV_GET_CPU(env)); 3642 #endif 3643 3644 thread_cpu = ENV_GET_CPU(env); 3645 3646 if (getenv("QEMU_STRACE")) { 3647 do_strace = 1; 3648 } 3649 3650 target_environ = envlist_to_environ(envlist, NULL); 3651 envlist_free(envlist); 3652 3653 #if defined(CONFIG_USE_GUEST_BASE) 3654 /* 3655 * Now that page sizes are configured in cpu_init() we can do 3656 * proper page alignment for guest_base. 3657 */ 3658 guest_base = HOST_PAGE_ALIGN(guest_base); 3659 3660 if (reserved_va || have_guest_base) { 3661 guest_base = init_guest_space(guest_base, reserved_va, 0, 3662 have_guest_base); 3663 if (guest_base == (unsigned long)-1) { 3664 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 3665 "space for use as guest address space (check your virtual " 3666 "memory ulimit setting or reserve less using -R option)\n", 3667 reserved_va); 3668 exit(1); 3669 } 3670 3671 if (reserved_va) { 3672 mmap_next_start = reserved_va; 3673 } 3674 } 3675 #endif /* CONFIG_USE_GUEST_BASE */ 3676 3677 /* 3678 * Read in mmap_min_addr kernel parameter. This value is used 3679 * When loading the ELF image to determine whether guest_base 3680 * is needed. It is also used in mmap_find_vma. 3681 */ 3682 { 3683 FILE *fp; 3684 3685 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 3686 unsigned long tmp; 3687 if (fscanf(fp, "%lu", &tmp) == 1) { 3688 mmap_min_addr = tmp; 3689 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr); 3690 } 3691 fclose(fp); 3692 } 3693 } 3694 3695 /* 3696 * Prepare copy of argv vector for target. 3697 */ 3698 target_argc = argc - optind; 3699 target_argv = calloc(target_argc + 1, sizeof (char *)); 3700 if (target_argv == NULL) { 3701 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 3702 exit(1); 3703 } 3704 3705 /* 3706 * If argv0 is specified (using '-0' switch) we replace 3707 * argv[0] pointer with the given one. 3708 */ 3709 i = 0; 3710 if (argv0 != NULL) { 3711 target_argv[i++] = strdup(argv0); 3712 } 3713 for (; i < target_argc; i++) { 3714 target_argv[i] = strdup(argv[optind + i]); 3715 } 3716 target_argv[target_argc] = NULL; 3717 3718 ts = g_malloc0 (sizeof(TaskState)); 3719 init_task_state(ts); 3720 /* build Task State */ 3721 ts->info = info; 3722 ts->bprm = &bprm; 3723 env->opaque = ts; 3724 task_settid(ts); 3725 3726 ret = loader_exec(filename, target_argv, target_environ, regs, 3727 info, &bprm); 3728 if (ret != 0) { 3729 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 3730 _exit(1); 3731 } 3732 3733 for (wrk = target_environ; *wrk; wrk++) { 3734 free(*wrk); 3735 } 3736 3737 free(target_environ); 3738 3739 if (qemu_log_enabled()) { 3740 #if defined(CONFIG_USE_GUEST_BASE) 3741 qemu_log("guest_base 0x%lx\n", guest_base); 3742 #endif 3743 log_page_dump(); 3744 3745 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 3746 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 3747 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 3748 info->start_code); 3749 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 3750 info->start_data); 3751 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 3752 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 3753 info->start_stack); 3754 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 3755 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 3756 } 3757 3758 target_set_brk(info->brk); 3759 syscall_init(); 3760 signal_init(); 3761 3762 #if defined(CONFIG_USE_GUEST_BASE) 3763 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 3764 generating the prologue until now so that the prologue can take 3765 the real value of GUEST_BASE into account. */ 3766 tcg_prologue_init(&tcg_ctx); 3767 #endif 3768 3769 #if defined(TARGET_I386) 3770 cpu_x86_set_cpl(env, 3); 3771 3772 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 3773 env->hflags |= HF_PE_MASK; 3774 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 3775 env->cr[4] |= CR4_OSFXSR_MASK; 3776 env->hflags |= HF_OSFXSR_MASK; 3777 } 3778 #ifndef TARGET_ABI32 3779 /* enable 64 bit mode if possible */ 3780 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 3781 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 3782 exit(1); 3783 } 3784 env->cr[4] |= CR4_PAE_MASK; 3785 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 3786 env->hflags |= HF_LMA_MASK; 3787 #endif 3788 3789 /* flags setup : we activate the IRQs by default as in user mode */ 3790 env->eflags |= IF_MASK; 3791 3792 /* linux register setup */ 3793 #ifndef TARGET_ABI32 3794 env->regs[R_EAX] = regs->rax; 3795 env->regs[R_EBX] = regs->rbx; 3796 env->regs[R_ECX] = regs->rcx; 3797 env->regs[R_EDX] = regs->rdx; 3798 env->regs[R_ESI] = regs->rsi; 3799 env->regs[R_EDI] = regs->rdi; 3800 env->regs[R_EBP] = regs->rbp; 3801 env->regs[R_ESP] = regs->rsp; 3802 env->eip = regs->rip; 3803 #else 3804 env->regs[R_EAX] = regs->eax; 3805 env->regs[R_EBX] = regs->ebx; 3806 env->regs[R_ECX] = regs->ecx; 3807 env->regs[R_EDX] = regs->edx; 3808 env->regs[R_ESI] = regs->esi; 3809 env->regs[R_EDI] = regs->edi; 3810 env->regs[R_EBP] = regs->ebp; 3811 env->regs[R_ESP] = regs->esp; 3812 env->eip = regs->eip; 3813 #endif 3814 3815 /* linux interrupt setup */ 3816 #ifndef TARGET_ABI32 3817 env->idt.limit = 511; 3818 #else 3819 env->idt.limit = 255; 3820 #endif 3821 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 3822 PROT_READ|PROT_WRITE, 3823 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 3824 idt_table = g2h(env->idt.base); 3825 set_idt(0, 0); 3826 set_idt(1, 0); 3827 set_idt(2, 0); 3828 set_idt(3, 3); 3829 set_idt(4, 3); 3830 set_idt(5, 0); 3831 set_idt(6, 0); 3832 set_idt(7, 0); 3833 set_idt(8, 0); 3834 set_idt(9, 0); 3835 set_idt(10, 0); 3836 set_idt(11, 0); 3837 set_idt(12, 0); 3838 set_idt(13, 0); 3839 set_idt(14, 0); 3840 set_idt(15, 0); 3841 set_idt(16, 0); 3842 set_idt(17, 0); 3843 set_idt(18, 0); 3844 set_idt(19, 0); 3845 set_idt(0x80, 3); 3846 3847 /* linux segment setup */ 3848 { 3849 uint64_t *gdt_table; 3850 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 3851 PROT_READ|PROT_WRITE, 3852 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 3853 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 3854 gdt_table = g2h(env->gdt.base); 3855 #ifdef TARGET_ABI32 3856 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 3857 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 3858 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 3859 #else 3860 /* 64 bit code segment */ 3861 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 3862 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 3863 DESC_L_MASK | 3864 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 3865 #endif 3866 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 3867 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 3868 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 3869 } 3870 cpu_x86_load_seg(env, R_CS, __USER_CS); 3871 cpu_x86_load_seg(env, R_SS, __USER_DS); 3872 #ifdef TARGET_ABI32 3873 cpu_x86_load_seg(env, R_DS, __USER_DS); 3874 cpu_x86_load_seg(env, R_ES, __USER_DS); 3875 cpu_x86_load_seg(env, R_FS, __USER_DS); 3876 cpu_x86_load_seg(env, R_GS, __USER_DS); 3877 /* This hack makes Wine work... */ 3878 env->segs[R_FS].selector = 0; 3879 #else 3880 cpu_x86_load_seg(env, R_DS, 0); 3881 cpu_x86_load_seg(env, R_ES, 0); 3882 cpu_x86_load_seg(env, R_FS, 0); 3883 cpu_x86_load_seg(env, R_GS, 0); 3884 #endif 3885 #elif defined(TARGET_ARM) 3886 { 3887 int i; 3888 cpsr_write(env, regs->uregs[16], 0xffffffff); 3889 for(i = 0; i < 16; i++) { 3890 env->regs[i] = regs->uregs[i]; 3891 } 3892 /* Enable BE8. */ 3893 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 3894 && (info->elf_flags & EF_ARM_BE8)) { 3895 env->bswap_code = 1; 3896 } 3897 } 3898 #elif defined(TARGET_UNICORE32) 3899 { 3900 int i; 3901 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 3902 for (i = 0; i < 32; i++) { 3903 env->regs[i] = regs->uregs[i]; 3904 } 3905 } 3906 #elif defined(TARGET_SPARC) 3907 { 3908 int i; 3909 env->pc = regs->pc; 3910 env->npc = regs->npc; 3911 env->y = regs->y; 3912 for(i = 0; i < 8; i++) 3913 env->gregs[i] = regs->u_regs[i]; 3914 for(i = 0; i < 8; i++) 3915 env->regwptr[i] = regs->u_regs[i + 8]; 3916 } 3917 #elif defined(TARGET_PPC) 3918 { 3919 int i; 3920 3921 #if defined(TARGET_PPC64) 3922 #if defined(TARGET_ABI32) 3923 env->msr &= ~((target_ulong)1 << MSR_SF); 3924 #else 3925 env->msr |= (target_ulong)1 << MSR_SF; 3926 #endif 3927 #endif 3928 env->nip = regs->nip; 3929 for(i = 0; i < 32; i++) { 3930 env->gpr[i] = regs->gpr[i]; 3931 } 3932 } 3933 #elif defined(TARGET_M68K) 3934 { 3935 env->pc = regs->pc; 3936 env->dregs[0] = regs->d0; 3937 env->dregs[1] = regs->d1; 3938 env->dregs[2] = regs->d2; 3939 env->dregs[3] = regs->d3; 3940 env->dregs[4] = regs->d4; 3941 env->dregs[5] = regs->d5; 3942 env->dregs[6] = regs->d6; 3943 env->dregs[7] = regs->d7; 3944 env->aregs[0] = regs->a0; 3945 env->aregs[1] = regs->a1; 3946 env->aregs[2] = regs->a2; 3947 env->aregs[3] = regs->a3; 3948 env->aregs[4] = regs->a4; 3949 env->aregs[5] = regs->a5; 3950 env->aregs[6] = regs->a6; 3951 env->aregs[7] = regs->usp; 3952 env->sr = regs->sr; 3953 ts->sim_syscalls = 1; 3954 } 3955 #elif defined(TARGET_MICROBLAZE) 3956 { 3957 env->regs[0] = regs->r0; 3958 env->regs[1] = regs->r1; 3959 env->regs[2] = regs->r2; 3960 env->regs[3] = regs->r3; 3961 env->regs[4] = regs->r4; 3962 env->regs[5] = regs->r5; 3963 env->regs[6] = regs->r6; 3964 env->regs[7] = regs->r7; 3965 env->regs[8] = regs->r8; 3966 env->regs[9] = regs->r9; 3967 env->regs[10] = regs->r10; 3968 env->regs[11] = regs->r11; 3969 env->regs[12] = regs->r12; 3970 env->regs[13] = regs->r13; 3971 env->regs[14] = regs->r14; 3972 env->regs[15] = regs->r15; 3973 env->regs[16] = regs->r16; 3974 env->regs[17] = regs->r17; 3975 env->regs[18] = regs->r18; 3976 env->regs[19] = regs->r19; 3977 env->regs[20] = regs->r20; 3978 env->regs[21] = regs->r21; 3979 env->regs[22] = regs->r22; 3980 env->regs[23] = regs->r23; 3981 env->regs[24] = regs->r24; 3982 env->regs[25] = regs->r25; 3983 env->regs[26] = regs->r26; 3984 env->regs[27] = regs->r27; 3985 env->regs[28] = regs->r28; 3986 env->regs[29] = regs->r29; 3987 env->regs[30] = regs->r30; 3988 env->regs[31] = regs->r31; 3989 env->sregs[SR_PC] = regs->pc; 3990 } 3991 #elif defined(TARGET_MIPS) 3992 { 3993 int i; 3994 3995 for(i = 0; i < 32; i++) { 3996 env->active_tc.gpr[i] = regs->regs[i]; 3997 } 3998 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 3999 if (regs->cp0_epc & 1) { 4000 env->hflags |= MIPS_HFLAG_M16; 4001 } 4002 } 4003 #elif defined(TARGET_OPENRISC) 4004 { 4005 int i; 4006 4007 for (i = 0; i < 32; i++) { 4008 env->gpr[i] = regs->gpr[i]; 4009 } 4010 4011 env->sr = regs->sr; 4012 env->pc = regs->pc; 4013 } 4014 #elif defined(TARGET_SH4) 4015 { 4016 int i; 4017 4018 for(i = 0; i < 16; i++) { 4019 env->gregs[i] = regs->regs[i]; 4020 } 4021 env->pc = regs->pc; 4022 } 4023 #elif defined(TARGET_ALPHA) 4024 { 4025 int i; 4026 4027 for(i = 0; i < 28; i++) { 4028 env->ir[i] = ((abi_ulong *)regs)[i]; 4029 } 4030 env->ir[IR_SP] = regs->usp; 4031 env->pc = regs->pc; 4032 } 4033 #elif defined(TARGET_CRIS) 4034 { 4035 env->regs[0] = regs->r0; 4036 env->regs[1] = regs->r1; 4037 env->regs[2] = regs->r2; 4038 env->regs[3] = regs->r3; 4039 env->regs[4] = regs->r4; 4040 env->regs[5] = regs->r5; 4041 env->regs[6] = regs->r6; 4042 env->regs[7] = regs->r7; 4043 env->regs[8] = regs->r8; 4044 env->regs[9] = regs->r9; 4045 env->regs[10] = regs->r10; 4046 env->regs[11] = regs->r11; 4047 env->regs[12] = regs->r12; 4048 env->regs[13] = regs->r13; 4049 env->regs[14] = info->start_stack; 4050 env->regs[15] = regs->acr; 4051 env->pc = regs->erp; 4052 } 4053 #elif defined(TARGET_S390X) 4054 { 4055 int i; 4056 for (i = 0; i < 16; i++) { 4057 env->regs[i] = regs->gprs[i]; 4058 } 4059 env->psw.mask = regs->psw.mask; 4060 env->psw.addr = regs->psw.addr; 4061 } 4062 #else 4063 #error unsupported target CPU 4064 #endif 4065 4066 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4067 ts->stack_base = info->start_stack; 4068 ts->heap_base = info->brk; 4069 /* This will be filled in on the first SYS_HEAPINFO call. */ 4070 ts->heap_limit = 0; 4071 #endif 4072 4073 if (gdbstub_port) { 4074 if (gdbserver_start(gdbstub_port) < 0) { 4075 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4076 gdbstub_port); 4077 exit(1); 4078 } 4079 gdb_handlesig(env, 0); 4080 } 4081 cpu_loop(env); 4082 /* never exits */ 4083 return 0; 4084 } 4085