1 /* 2 * qemu user main 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qemu-version.h" 21 #include <sys/syscall.h> 22 #include <sys/resource.h> 23 24 #include "qapi/error.h" 25 #include "qemu.h" 26 #include "qemu/path.h" 27 #include "qemu/config-file.h" 28 #include "qemu/cutils.h" 29 #include "qemu/help_option.h" 30 #include "cpu.h" 31 #include "exec/exec-all.h" 32 #include "tcg.h" 33 #include "qemu/timer.h" 34 #include "qemu/envlist.h" 35 #include "elf.h" 36 #include "exec/log.h" 37 #include "trace/control.h" 38 #include "glib-compat.h" 39 40 char *exec_path; 41 42 int singlestep; 43 static const char *filename; 44 static const char *argv0; 45 static int gdbstub_port; 46 static envlist_t *envlist; 47 static const char *cpu_model; 48 unsigned long mmap_min_addr; 49 unsigned long guest_base; 50 int have_guest_base; 51 52 #define EXCP_DUMP(env, fmt, ...) \ 53 do { \ 54 CPUState *cs = ENV_GET_CPU(env); \ 55 fprintf(stderr, fmt , ## __VA_ARGS__); \ 56 cpu_dump_state(cs, stderr, fprintf, 0); \ 57 if (qemu_log_separate()) { \ 58 qemu_log(fmt, ## __VA_ARGS__); \ 59 log_cpu_state(cs, 0); \ 60 } \ 61 } while (0) 62 63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) 64 /* 65 * When running 32-on-64 we should make sure we can fit all of the possible 66 * guest address space into a contiguous chunk of virtual host memory. 67 * 68 * This way we will never overlap with our own libraries or binaries or stack 69 * or anything else that QEMU maps. 70 */ 71 # ifdef TARGET_MIPS 72 /* MIPS only supports 31 bits of virtual address space for user space */ 73 unsigned long reserved_va = 0x77000000; 74 # else 75 unsigned long reserved_va = 0xf7000000; 76 # endif 77 #else 78 unsigned long reserved_va; 79 #endif 80 81 static void usage(int exitcode); 82 83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; 84 const char *qemu_uname_release; 85 86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so 87 we allocate a bigger stack. Need a better solution, for example 88 by remapping the process stack directly at the right place */ 89 unsigned long guest_stack_size = 8 * 1024 * 1024UL; 90 91 void gemu_log(const char *fmt, ...) 92 { 93 va_list ap; 94 95 va_start(ap, fmt); 96 vfprintf(stderr, fmt, ap); 97 va_end(ap); 98 } 99 100 #if defined(TARGET_I386) 101 int cpu_get_pic_interrupt(CPUX86State *env) 102 { 103 return -1; 104 } 105 #endif 106 107 /***********************************************************/ 108 /* Helper routines for implementing atomic operations. */ 109 110 /* Make sure everything is in a consistent state for calling fork(). */ 111 void fork_start(void) 112 { 113 cpu_list_lock(); 114 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); 115 mmap_fork_start(); 116 } 117 118 void fork_end(int child) 119 { 120 mmap_fork_end(child); 121 if (child) { 122 CPUState *cpu, *next_cpu; 123 /* Child processes created by fork() only have a single thread. 124 Discard information about the parent threads. */ 125 CPU_FOREACH_SAFE(cpu, next_cpu) { 126 if (cpu != thread_cpu) { 127 QTAILQ_REMOVE(&cpus, cpu, node); 128 } 129 } 130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); 131 qemu_init_cpu_list(); 132 gdbserver_fork(thread_cpu); 133 } else { 134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); 135 cpu_list_unlock(); 136 } 137 } 138 139 #ifdef TARGET_I386 140 /***********************************************************/ 141 /* CPUX86 core interface */ 142 143 uint64_t cpu_get_tsc(CPUX86State *env) 144 { 145 return cpu_get_host_ticks(); 146 } 147 148 static void write_dt(void *ptr, unsigned long addr, unsigned long limit, 149 int flags) 150 { 151 unsigned int e1, e2; 152 uint32_t *p; 153 e1 = (addr << 16) | (limit & 0xffff); 154 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); 155 e2 |= flags; 156 p = ptr; 157 p[0] = tswap32(e1); 158 p[1] = tswap32(e2); 159 } 160 161 static uint64_t *idt_table; 162 #ifdef TARGET_X86_64 163 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, 164 uint64_t addr, unsigned int sel) 165 { 166 uint32_t *p, e1, e2; 167 e1 = (addr & 0xffff) | (sel << 16); 168 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 169 p = ptr; 170 p[0] = tswap32(e1); 171 p[1] = tswap32(e2); 172 p[2] = tswap32(addr >> 32); 173 p[3] = 0; 174 } 175 /* only dpl matters as we do only user space emulation */ 176 static void set_idt(int n, unsigned int dpl) 177 { 178 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); 179 } 180 #else 181 static void set_gate(void *ptr, unsigned int type, unsigned int dpl, 182 uint32_t addr, unsigned int sel) 183 { 184 uint32_t *p, e1, e2; 185 e1 = (addr & 0xffff) | (sel << 16); 186 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); 187 p = ptr; 188 p[0] = tswap32(e1); 189 p[1] = tswap32(e2); 190 } 191 192 /* only dpl matters as we do only user space emulation */ 193 static void set_idt(int n, unsigned int dpl) 194 { 195 set_gate(idt_table + n, 0, dpl, 0, 0); 196 } 197 #endif 198 199 void cpu_loop(CPUX86State *env) 200 { 201 CPUState *cs = CPU(x86_env_get_cpu(env)); 202 int trapnr; 203 abi_ulong pc; 204 abi_ulong ret; 205 target_siginfo_t info; 206 207 for(;;) { 208 cpu_exec_start(cs); 209 trapnr = cpu_exec(cs); 210 cpu_exec_end(cs); 211 process_queued_cpu_work(cs); 212 213 switch(trapnr) { 214 case 0x80: 215 /* linux syscall from int $0x80 */ 216 ret = do_syscall(env, 217 env->regs[R_EAX], 218 env->regs[R_EBX], 219 env->regs[R_ECX], 220 env->regs[R_EDX], 221 env->regs[R_ESI], 222 env->regs[R_EDI], 223 env->regs[R_EBP], 224 0, 0); 225 if (ret == -TARGET_ERESTARTSYS) { 226 env->eip -= 2; 227 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 228 env->regs[R_EAX] = ret; 229 } 230 break; 231 #ifndef TARGET_ABI32 232 case EXCP_SYSCALL: 233 /* linux syscall from syscall instruction */ 234 ret = do_syscall(env, 235 env->regs[R_EAX], 236 env->regs[R_EDI], 237 env->regs[R_ESI], 238 env->regs[R_EDX], 239 env->regs[10], 240 env->regs[8], 241 env->regs[9], 242 0, 0); 243 if (ret == -TARGET_ERESTARTSYS) { 244 env->eip -= 2; 245 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 246 env->regs[R_EAX] = ret; 247 } 248 break; 249 #endif 250 case EXCP0B_NOSEG: 251 case EXCP0C_STACK: 252 info.si_signo = TARGET_SIGBUS; 253 info.si_errno = 0; 254 info.si_code = TARGET_SI_KERNEL; 255 info._sifields._sigfault._addr = 0; 256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 257 break; 258 case EXCP0D_GPF: 259 /* XXX: potential problem if ABI32 */ 260 #ifndef TARGET_X86_64 261 if (env->eflags & VM_MASK) { 262 handle_vm86_fault(env); 263 } else 264 #endif 265 { 266 info.si_signo = TARGET_SIGSEGV; 267 info.si_errno = 0; 268 info.si_code = TARGET_SI_KERNEL; 269 info._sifields._sigfault._addr = 0; 270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 271 } 272 break; 273 case EXCP0E_PAGE: 274 info.si_signo = TARGET_SIGSEGV; 275 info.si_errno = 0; 276 if (!(env->error_code & 1)) 277 info.si_code = TARGET_SEGV_MAPERR; 278 else 279 info.si_code = TARGET_SEGV_ACCERR; 280 info._sifields._sigfault._addr = env->cr[2]; 281 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 282 break; 283 case EXCP00_DIVZ: 284 #ifndef TARGET_X86_64 285 if (env->eflags & VM_MASK) { 286 handle_vm86_trap(env, trapnr); 287 } else 288 #endif 289 { 290 /* division by zero */ 291 info.si_signo = TARGET_SIGFPE; 292 info.si_errno = 0; 293 info.si_code = TARGET_FPE_INTDIV; 294 info._sifields._sigfault._addr = env->eip; 295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 296 } 297 break; 298 case EXCP01_DB: 299 case EXCP03_INT3: 300 #ifndef TARGET_X86_64 301 if (env->eflags & VM_MASK) { 302 handle_vm86_trap(env, trapnr); 303 } else 304 #endif 305 { 306 info.si_signo = TARGET_SIGTRAP; 307 info.si_errno = 0; 308 if (trapnr == EXCP01_DB) { 309 info.si_code = TARGET_TRAP_BRKPT; 310 info._sifields._sigfault._addr = env->eip; 311 } else { 312 info.si_code = TARGET_SI_KERNEL; 313 info._sifields._sigfault._addr = 0; 314 } 315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 316 } 317 break; 318 case EXCP04_INTO: 319 case EXCP05_BOUND: 320 #ifndef TARGET_X86_64 321 if (env->eflags & VM_MASK) { 322 handle_vm86_trap(env, trapnr); 323 } else 324 #endif 325 { 326 info.si_signo = TARGET_SIGSEGV; 327 info.si_errno = 0; 328 info.si_code = TARGET_SI_KERNEL; 329 info._sifields._sigfault._addr = 0; 330 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 331 } 332 break; 333 case EXCP06_ILLOP: 334 info.si_signo = TARGET_SIGILL; 335 info.si_errno = 0; 336 info.si_code = TARGET_ILL_ILLOPN; 337 info._sifields._sigfault._addr = env->eip; 338 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 339 break; 340 case EXCP_INTERRUPT: 341 /* just indicate that signals should be handled asap */ 342 break; 343 case EXCP_DEBUG: 344 { 345 int sig; 346 347 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 348 if (sig) 349 { 350 info.si_signo = sig; 351 info.si_errno = 0; 352 info.si_code = TARGET_TRAP_BRKPT; 353 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 354 } 355 } 356 break; 357 default: 358 pc = env->segs[R_CS].base + env->eip; 359 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", 360 (long)pc, trapnr); 361 abort(); 362 } 363 process_pending_signals(env); 364 } 365 } 366 #endif 367 368 #ifdef TARGET_ARM 369 370 #define get_user_code_u32(x, gaddr, env) \ 371 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 372 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 373 (x) = bswap32(x); \ 374 } \ 375 __r; \ 376 }) 377 378 #define get_user_code_u16(x, gaddr, env) \ 379 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 380 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 381 (x) = bswap16(x); \ 382 } \ 383 __r; \ 384 }) 385 386 #define get_user_data_u32(x, gaddr, env) \ 387 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 388 if (!__r && arm_cpu_bswap_data(env)) { \ 389 (x) = bswap32(x); \ 390 } \ 391 __r; \ 392 }) 393 394 #define get_user_data_u16(x, gaddr, env) \ 395 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 396 if (!__r && arm_cpu_bswap_data(env)) { \ 397 (x) = bswap16(x); \ 398 } \ 399 __r; \ 400 }) 401 402 #define put_user_data_u32(x, gaddr, env) \ 403 ({ typeof(x) __x = (x); \ 404 if (arm_cpu_bswap_data(env)) { \ 405 __x = bswap32(__x); \ 406 } \ 407 put_user_u32(__x, (gaddr)); \ 408 }) 409 410 #define put_user_data_u16(x, gaddr, env) \ 411 ({ typeof(x) __x = (x); \ 412 if (arm_cpu_bswap_data(env)) { \ 413 __x = bswap16(__x); \ 414 } \ 415 put_user_u16(__x, (gaddr)); \ 416 }) 417 418 #ifdef TARGET_ABI32 419 /* Commpage handling -- there is no commpage for AArch64 */ 420 421 /* 422 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt 423 * Input: 424 * r0 = pointer to oldval 425 * r1 = pointer to newval 426 * r2 = pointer to target value 427 * 428 * Output: 429 * r0 = 0 if *ptr was changed, non-0 if no exchange happened 430 * C set if *ptr was changed, clear if no exchange happened 431 * 432 * Note segv's in kernel helpers are a bit tricky, we can set the 433 * data address sensibly but the PC address is just the entry point. 434 */ 435 static void arm_kernel_cmpxchg64_helper(CPUARMState *env) 436 { 437 uint64_t oldval, newval, val; 438 uint32_t addr, cpsr; 439 target_siginfo_t info; 440 441 /* Based on the 32 bit code in do_kernel_trap */ 442 443 /* XXX: This only works between threads, not between processes. 444 It's probably possible to implement this with native host 445 operations. However things like ldrex/strex are much harder so 446 there's not much point trying. */ 447 start_exclusive(); 448 cpsr = cpsr_read(env); 449 addr = env->regs[2]; 450 451 if (get_user_u64(oldval, env->regs[0])) { 452 env->exception.vaddress = env->regs[0]; 453 goto segv; 454 }; 455 456 if (get_user_u64(newval, env->regs[1])) { 457 env->exception.vaddress = env->regs[1]; 458 goto segv; 459 }; 460 461 if (get_user_u64(val, addr)) { 462 env->exception.vaddress = addr; 463 goto segv; 464 } 465 466 if (val == oldval) { 467 val = newval; 468 469 if (put_user_u64(val, addr)) { 470 env->exception.vaddress = addr; 471 goto segv; 472 }; 473 474 env->regs[0] = 0; 475 cpsr |= CPSR_C; 476 } else { 477 env->regs[0] = -1; 478 cpsr &= ~CPSR_C; 479 } 480 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 481 end_exclusive(); 482 return; 483 484 segv: 485 end_exclusive(); 486 /* We get the PC of the entry address - which is as good as anything, 487 on a real kernel what you get depends on which mode it uses. */ 488 info.si_signo = TARGET_SIGSEGV; 489 info.si_errno = 0; 490 /* XXX: check env->error_code */ 491 info.si_code = TARGET_SEGV_MAPERR; 492 info._sifields._sigfault._addr = env->exception.vaddress; 493 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 494 } 495 496 /* Handle a jump to the kernel code page. */ 497 static int 498 do_kernel_trap(CPUARMState *env) 499 { 500 uint32_t addr; 501 uint32_t cpsr; 502 uint32_t val; 503 504 switch (env->regs[15]) { 505 case 0xffff0fa0: /* __kernel_memory_barrier */ 506 /* ??? No-op. Will need to do better for SMP. */ 507 break; 508 case 0xffff0fc0: /* __kernel_cmpxchg */ 509 /* XXX: This only works between threads, not between processes. 510 It's probably possible to implement this with native host 511 operations. However things like ldrex/strex are much harder so 512 there's not much point trying. */ 513 start_exclusive(); 514 cpsr = cpsr_read(env); 515 addr = env->regs[2]; 516 /* FIXME: This should SEGV if the access fails. */ 517 if (get_user_u32(val, addr)) 518 val = ~env->regs[0]; 519 if (val == env->regs[0]) { 520 val = env->regs[1]; 521 /* FIXME: Check for segfaults. */ 522 put_user_u32(val, addr); 523 env->regs[0] = 0; 524 cpsr |= CPSR_C; 525 } else { 526 env->regs[0] = -1; 527 cpsr &= ~CPSR_C; 528 } 529 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); 530 end_exclusive(); 531 break; 532 case 0xffff0fe0: /* __kernel_get_tls */ 533 env->regs[0] = cpu_get_tls(env); 534 break; 535 case 0xffff0f60: /* __kernel_cmpxchg64 */ 536 arm_kernel_cmpxchg64_helper(env); 537 break; 538 539 default: 540 return 1; 541 } 542 /* Jump back to the caller. */ 543 addr = env->regs[14]; 544 if (addr & 1) { 545 env->thumb = 1; 546 addr &= ~1; 547 } 548 env->regs[15] = addr; 549 550 return 0; 551 } 552 553 /* Store exclusive handling for AArch32 */ 554 static int do_strex(CPUARMState *env) 555 { 556 uint64_t val; 557 int size; 558 int rc = 1; 559 int segv = 0; 560 uint32_t addr; 561 start_exclusive(); 562 if (env->exclusive_addr != env->exclusive_test) { 563 goto fail; 564 } 565 /* We know we're always AArch32 so the address is in uint32_t range 566 * unless it was the -1 exclusive-monitor-lost value (which won't 567 * match exclusive_test above). 568 */ 569 assert(extract64(env->exclusive_addr, 32, 32) == 0); 570 addr = env->exclusive_addr; 571 size = env->exclusive_info & 0xf; 572 switch (size) { 573 case 0: 574 segv = get_user_u8(val, addr); 575 break; 576 case 1: 577 segv = get_user_data_u16(val, addr, env); 578 break; 579 case 2: 580 case 3: 581 segv = get_user_data_u32(val, addr, env); 582 break; 583 default: 584 abort(); 585 } 586 if (segv) { 587 env->exception.vaddress = addr; 588 goto done; 589 } 590 if (size == 3) { 591 uint32_t valhi; 592 segv = get_user_data_u32(valhi, addr + 4, env); 593 if (segv) { 594 env->exception.vaddress = addr + 4; 595 goto done; 596 } 597 if (arm_cpu_bswap_data(env)) { 598 val = deposit64((uint64_t)valhi, 32, 32, val); 599 } else { 600 val = deposit64(val, 32, 32, valhi); 601 } 602 } 603 if (val != env->exclusive_val) { 604 goto fail; 605 } 606 607 val = env->regs[(env->exclusive_info >> 8) & 0xf]; 608 switch (size) { 609 case 0: 610 segv = put_user_u8(val, addr); 611 break; 612 case 1: 613 segv = put_user_data_u16(val, addr, env); 614 break; 615 case 2: 616 case 3: 617 segv = put_user_data_u32(val, addr, env); 618 break; 619 } 620 if (segv) { 621 env->exception.vaddress = addr; 622 goto done; 623 } 624 if (size == 3) { 625 val = env->regs[(env->exclusive_info >> 12) & 0xf]; 626 segv = put_user_data_u32(val, addr + 4, env); 627 if (segv) { 628 env->exception.vaddress = addr + 4; 629 goto done; 630 } 631 } 632 rc = 0; 633 fail: 634 env->regs[15] += 4; 635 env->regs[(env->exclusive_info >> 4) & 0xf] = rc; 636 done: 637 end_exclusive(); 638 return segv; 639 } 640 641 void cpu_loop(CPUARMState *env) 642 { 643 CPUState *cs = CPU(arm_env_get_cpu(env)); 644 int trapnr; 645 unsigned int n, insn; 646 target_siginfo_t info; 647 uint32_t addr; 648 abi_ulong ret; 649 650 for(;;) { 651 cpu_exec_start(cs); 652 trapnr = cpu_exec(cs); 653 cpu_exec_end(cs); 654 process_queued_cpu_work(cs); 655 656 switch(trapnr) { 657 case EXCP_UDEF: 658 { 659 TaskState *ts = cs->opaque; 660 uint32_t opcode; 661 int rc; 662 663 /* we handle the FPU emulation here, as Linux */ 664 /* we get the opcode */ 665 /* FIXME - what to do if get_user() fails? */ 666 get_user_code_u32(opcode, env->regs[15], env); 667 668 rc = EmulateAll(opcode, &ts->fpa, env); 669 if (rc == 0) { /* illegal instruction */ 670 info.si_signo = TARGET_SIGILL; 671 info.si_errno = 0; 672 info.si_code = TARGET_ILL_ILLOPN; 673 info._sifields._sigfault._addr = env->regs[15]; 674 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 675 } else if (rc < 0) { /* FP exception */ 676 int arm_fpe=0; 677 678 /* translate softfloat flags to FPSR flags */ 679 if (-rc & float_flag_invalid) 680 arm_fpe |= BIT_IOC; 681 if (-rc & float_flag_divbyzero) 682 arm_fpe |= BIT_DZC; 683 if (-rc & float_flag_overflow) 684 arm_fpe |= BIT_OFC; 685 if (-rc & float_flag_underflow) 686 arm_fpe |= BIT_UFC; 687 if (-rc & float_flag_inexact) 688 arm_fpe |= BIT_IXC; 689 690 FPSR fpsr = ts->fpa.fpsr; 691 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); 692 693 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ 694 info.si_signo = TARGET_SIGFPE; 695 info.si_errno = 0; 696 697 /* ordered by priority, least first */ 698 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; 699 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; 700 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; 701 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; 702 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; 703 704 info._sifields._sigfault._addr = env->regs[15]; 705 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 706 } else { 707 env->regs[15] += 4; 708 } 709 710 /* accumulate unenabled exceptions */ 711 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) 712 fpsr |= BIT_IXC; 713 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) 714 fpsr |= BIT_UFC; 715 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) 716 fpsr |= BIT_OFC; 717 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) 718 fpsr |= BIT_DZC; 719 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) 720 fpsr |= BIT_IOC; 721 ts->fpa.fpsr=fpsr; 722 } else { /* everything OK */ 723 /* increment PC */ 724 env->regs[15] += 4; 725 } 726 } 727 break; 728 case EXCP_SWI: 729 case EXCP_BKPT: 730 { 731 env->eabi = 1; 732 /* system call */ 733 if (trapnr == EXCP_BKPT) { 734 if (env->thumb) { 735 /* FIXME - what to do if get_user() fails? */ 736 get_user_code_u16(insn, env->regs[15], env); 737 n = insn & 0xff; 738 env->regs[15] += 2; 739 } else { 740 /* FIXME - what to do if get_user() fails? */ 741 get_user_code_u32(insn, env->regs[15], env); 742 n = (insn & 0xf) | ((insn >> 4) & 0xff0); 743 env->regs[15] += 4; 744 } 745 } else { 746 if (env->thumb) { 747 /* FIXME - what to do if get_user() fails? */ 748 get_user_code_u16(insn, env->regs[15] - 2, env); 749 n = insn & 0xff; 750 } else { 751 /* FIXME - what to do if get_user() fails? */ 752 get_user_code_u32(insn, env->regs[15] - 4, env); 753 n = insn & 0xffffff; 754 } 755 } 756 757 if (n == ARM_NR_cacheflush) { 758 /* nop */ 759 } else if (n == ARM_NR_semihosting 760 || n == ARM_NR_thumb_semihosting) { 761 env->regs[0] = do_arm_semihosting (env); 762 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { 763 /* linux syscall */ 764 if (env->thumb || n == 0) { 765 n = env->regs[7]; 766 } else { 767 n -= ARM_SYSCALL_BASE; 768 env->eabi = 0; 769 } 770 if ( n > ARM_NR_BASE) { 771 switch (n) { 772 case ARM_NR_cacheflush: 773 /* nop */ 774 break; 775 case ARM_NR_set_tls: 776 cpu_set_tls(env, env->regs[0]); 777 env->regs[0] = 0; 778 break; 779 case ARM_NR_breakpoint: 780 env->regs[15] -= env->thumb ? 2 : 4; 781 goto excp_debug; 782 default: 783 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", 784 n); 785 env->regs[0] = -TARGET_ENOSYS; 786 break; 787 } 788 } else { 789 ret = do_syscall(env, 790 n, 791 env->regs[0], 792 env->regs[1], 793 env->regs[2], 794 env->regs[3], 795 env->regs[4], 796 env->regs[5], 797 0, 0); 798 if (ret == -TARGET_ERESTARTSYS) { 799 env->regs[15] -= env->thumb ? 2 : 4; 800 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 801 env->regs[0] = ret; 802 } 803 } 804 } else { 805 goto error; 806 } 807 } 808 break; 809 case EXCP_INTERRUPT: 810 /* just indicate that signals should be handled asap */ 811 break; 812 case EXCP_STREX: 813 if (!do_strex(env)) { 814 break; 815 } 816 /* fall through for segv */ 817 case EXCP_PREFETCH_ABORT: 818 case EXCP_DATA_ABORT: 819 addr = env->exception.vaddress; 820 { 821 info.si_signo = TARGET_SIGSEGV; 822 info.si_errno = 0; 823 /* XXX: check env->error_code */ 824 info.si_code = TARGET_SEGV_MAPERR; 825 info._sifields._sigfault._addr = addr; 826 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 827 } 828 break; 829 case EXCP_DEBUG: 830 excp_debug: 831 { 832 int sig; 833 834 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 835 if (sig) 836 { 837 info.si_signo = sig; 838 info.si_errno = 0; 839 info.si_code = TARGET_TRAP_BRKPT; 840 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 841 } 842 } 843 break; 844 case EXCP_KERNEL_TRAP: 845 if (do_kernel_trap(env)) 846 goto error; 847 break; 848 case EXCP_YIELD: 849 /* nothing to do here for user-mode, just resume guest code */ 850 break; 851 default: 852 error: 853 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 854 abort(); 855 } 856 process_pending_signals(env); 857 } 858 } 859 860 #else 861 862 /* 863 * Handle AArch64 store-release exclusive 864 * 865 * rs = gets the status result of store exclusive 866 * rt = is the register that is stored 867 * rt2 = is the second register store (in STP) 868 * 869 */ 870 static int do_strex_a64(CPUARMState *env) 871 { 872 uint64_t val; 873 int size; 874 bool is_pair; 875 int rc = 1; 876 int segv = 0; 877 uint64_t addr; 878 int rs, rt, rt2; 879 880 start_exclusive(); 881 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ 882 size = extract32(env->exclusive_info, 0, 2); 883 is_pair = extract32(env->exclusive_info, 2, 1); 884 rs = extract32(env->exclusive_info, 4, 5); 885 rt = extract32(env->exclusive_info, 9, 5); 886 rt2 = extract32(env->exclusive_info, 14, 5); 887 888 addr = env->exclusive_addr; 889 890 if (addr != env->exclusive_test) { 891 goto finish; 892 } 893 894 switch (size) { 895 case 0: 896 segv = get_user_u8(val, addr); 897 break; 898 case 1: 899 segv = get_user_u16(val, addr); 900 break; 901 case 2: 902 segv = get_user_u32(val, addr); 903 break; 904 case 3: 905 segv = get_user_u64(val, addr); 906 break; 907 default: 908 abort(); 909 } 910 if (segv) { 911 env->exception.vaddress = addr; 912 goto error; 913 } 914 if (val != env->exclusive_val) { 915 goto finish; 916 } 917 if (is_pair) { 918 if (size == 2) { 919 segv = get_user_u32(val, addr + 4); 920 } else { 921 segv = get_user_u64(val, addr + 8); 922 } 923 if (segv) { 924 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 925 goto error; 926 } 927 if (val != env->exclusive_high) { 928 goto finish; 929 } 930 } 931 /* handle the zero register */ 932 val = rt == 31 ? 0 : env->xregs[rt]; 933 switch (size) { 934 case 0: 935 segv = put_user_u8(val, addr); 936 break; 937 case 1: 938 segv = put_user_u16(val, addr); 939 break; 940 case 2: 941 segv = put_user_u32(val, addr); 942 break; 943 case 3: 944 segv = put_user_u64(val, addr); 945 break; 946 } 947 if (segv) { 948 goto error; 949 } 950 if (is_pair) { 951 /* handle the zero register */ 952 val = rt2 == 31 ? 0 : env->xregs[rt2]; 953 if (size == 2) { 954 segv = put_user_u32(val, addr + 4); 955 } else { 956 segv = put_user_u64(val, addr + 8); 957 } 958 if (segv) { 959 env->exception.vaddress = addr + (size == 2 ? 4 : 8); 960 goto error; 961 } 962 } 963 rc = 0; 964 finish: 965 env->pc += 4; 966 /* rs == 31 encodes a write to the ZR, thus throwing away 967 * the status return. This is rather silly but valid. 968 */ 969 if (rs < 31) { 970 env->xregs[rs] = rc; 971 } 972 error: 973 /* instruction faulted, PC does not advance */ 974 /* either way a strex releases any exclusive lock we have */ 975 env->exclusive_addr = -1; 976 end_exclusive(); 977 return segv; 978 } 979 980 /* AArch64 main loop */ 981 void cpu_loop(CPUARMState *env) 982 { 983 CPUState *cs = CPU(arm_env_get_cpu(env)); 984 int trapnr, sig; 985 abi_long ret; 986 target_siginfo_t info; 987 988 for (;;) { 989 cpu_exec_start(cs); 990 trapnr = cpu_exec(cs); 991 cpu_exec_end(cs); 992 process_queued_cpu_work(cs); 993 994 switch (trapnr) { 995 case EXCP_SWI: 996 ret = do_syscall(env, 997 env->xregs[8], 998 env->xregs[0], 999 env->xregs[1], 1000 env->xregs[2], 1001 env->xregs[3], 1002 env->xregs[4], 1003 env->xregs[5], 1004 0, 0); 1005 if (ret == -TARGET_ERESTARTSYS) { 1006 env->pc -= 4; 1007 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 1008 env->xregs[0] = ret; 1009 } 1010 break; 1011 case EXCP_INTERRUPT: 1012 /* just indicate that signals should be handled asap */ 1013 break; 1014 case EXCP_UDEF: 1015 info.si_signo = TARGET_SIGILL; 1016 info.si_errno = 0; 1017 info.si_code = TARGET_ILL_ILLOPN; 1018 info._sifields._sigfault._addr = env->pc; 1019 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1020 break; 1021 case EXCP_STREX: 1022 if (!do_strex_a64(env)) { 1023 break; 1024 } 1025 /* fall through for segv */ 1026 case EXCP_PREFETCH_ABORT: 1027 case EXCP_DATA_ABORT: 1028 info.si_signo = TARGET_SIGSEGV; 1029 info.si_errno = 0; 1030 /* XXX: check env->error_code */ 1031 info.si_code = TARGET_SEGV_MAPERR; 1032 info._sifields._sigfault._addr = env->exception.vaddress; 1033 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1034 break; 1035 case EXCP_DEBUG: 1036 case EXCP_BKPT: 1037 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1038 if (sig) { 1039 info.si_signo = sig; 1040 info.si_errno = 0; 1041 info.si_code = TARGET_TRAP_BRKPT; 1042 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1043 } 1044 break; 1045 case EXCP_SEMIHOST: 1046 env->xregs[0] = do_arm_semihosting(env); 1047 break; 1048 case EXCP_YIELD: 1049 /* nothing to do here for user-mode, just resume guest code */ 1050 break; 1051 default: 1052 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1053 abort(); 1054 } 1055 process_pending_signals(env); 1056 /* Exception return on AArch64 always clears the exclusive monitor, 1057 * so any return to running guest code implies this. 1058 * A strex (successful or otherwise) also clears the monitor, so 1059 * we don't need to specialcase EXCP_STREX. 1060 */ 1061 env->exclusive_addr = -1; 1062 } 1063 } 1064 #endif /* ndef TARGET_ABI32 */ 1065 1066 #endif 1067 1068 #ifdef TARGET_UNICORE32 1069 1070 void cpu_loop(CPUUniCore32State *env) 1071 { 1072 CPUState *cs = CPU(uc32_env_get_cpu(env)); 1073 int trapnr; 1074 unsigned int n, insn; 1075 target_siginfo_t info; 1076 1077 for (;;) { 1078 cpu_exec_start(cs); 1079 trapnr = cpu_exec(cs); 1080 cpu_exec_end(cs); 1081 process_queued_cpu_work(cs); 1082 1083 switch (trapnr) { 1084 case UC32_EXCP_PRIV: 1085 { 1086 /* system call */ 1087 get_user_u32(insn, env->regs[31] - 4); 1088 n = insn & 0xffffff; 1089 1090 if (n >= UC32_SYSCALL_BASE) { 1091 /* linux syscall */ 1092 n -= UC32_SYSCALL_BASE; 1093 if (n == UC32_SYSCALL_NR_set_tls) { 1094 cpu_set_tls(env, env->regs[0]); 1095 env->regs[0] = 0; 1096 } else { 1097 abi_long ret = do_syscall(env, 1098 n, 1099 env->regs[0], 1100 env->regs[1], 1101 env->regs[2], 1102 env->regs[3], 1103 env->regs[4], 1104 env->regs[5], 1105 0, 0); 1106 if (ret == -TARGET_ERESTARTSYS) { 1107 env->regs[31] -= 4; 1108 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 1109 env->regs[0] = ret; 1110 } 1111 } 1112 } else { 1113 goto error; 1114 } 1115 } 1116 break; 1117 case UC32_EXCP_DTRAP: 1118 case UC32_EXCP_ITRAP: 1119 info.si_signo = TARGET_SIGSEGV; 1120 info.si_errno = 0; 1121 /* XXX: check env->error_code */ 1122 info.si_code = TARGET_SEGV_MAPERR; 1123 info._sifields._sigfault._addr = env->cp0.c4_faultaddr; 1124 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1125 break; 1126 case EXCP_INTERRUPT: 1127 /* just indicate that signals should be handled asap */ 1128 break; 1129 case EXCP_DEBUG: 1130 { 1131 int sig; 1132 1133 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1134 if (sig) { 1135 info.si_signo = sig; 1136 info.si_errno = 0; 1137 info.si_code = TARGET_TRAP_BRKPT; 1138 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1139 } 1140 } 1141 break; 1142 default: 1143 goto error; 1144 } 1145 process_pending_signals(env); 1146 } 1147 1148 error: 1149 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 1150 abort(); 1151 } 1152 #endif 1153 1154 #ifdef TARGET_SPARC 1155 #define SPARC64_STACK_BIAS 2047 1156 1157 //#define DEBUG_WIN 1158 1159 /* WARNING: dealing with register windows _is_ complicated. More info 1160 can be found at http://www.sics.se/~psm/sparcstack.html */ 1161 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) 1162 { 1163 index = (index + cwp * 16) % (16 * env->nwindows); 1164 /* wrap handling : if cwp is on the last window, then we use the 1165 registers 'after' the end */ 1166 if (index < 8 && env->cwp == env->nwindows - 1) 1167 index += 16 * env->nwindows; 1168 return index; 1169 } 1170 1171 /* save the register window 'cwp1' */ 1172 static inline void save_window_offset(CPUSPARCState *env, int cwp1) 1173 { 1174 unsigned int i; 1175 abi_ulong sp_ptr; 1176 1177 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1178 #ifdef TARGET_SPARC64 1179 if (sp_ptr & 3) 1180 sp_ptr += SPARC64_STACK_BIAS; 1181 #endif 1182 #if defined(DEBUG_WIN) 1183 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", 1184 sp_ptr, cwp1); 1185 #endif 1186 for(i = 0; i < 16; i++) { 1187 /* FIXME - what to do if put_user() fails? */ 1188 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1189 sp_ptr += sizeof(abi_ulong); 1190 } 1191 } 1192 1193 static void save_window(CPUSPARCState *env) 1194 { 1195 #ifndef TARGET_SPARC64 1196 unsigned int new_wim; 1197 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & 1198 ((1LL << env->nwindows) - 1); 1199 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1200 env->wim = new_wim; 1201 #else 1202 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); 1203 env->cansave++; 1204 env->canrestore--; 1205 #endif 1206 } 1207 1208 static void restore_window(CPUSPARCState *env) 1209 { 1210 #ifndef TARGET_SPARC64 1211 unsigned int new_wim; 1212 #endif 1213 unsigned int i, cwp1; 1214 abi_ulong sp_ptr; 1215 1216 #ifndef TARGET_SPARC64 1217 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & 1218 ((1LL << env->nwindows) - 1); 1219 #endif 1220 1221 /* restore the invalid window */ 1222 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1223 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; 1224 #ifdef TARGET_SPARC64 1225 if (sp_ptr & 3) 1226 sp_ptr += SPARC64_STACK_BIAS; 1227 #endif 1228 #if defined(DEBUG_WIN) 1229 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", 1230 sp_ptr, cwp1); 1231 #endif 1232 for(i = 0; i < 16; i++) { 1233 /* FIXME - what to do if get_user() fails? */ 1234 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); 1235 sp_ptr += sizeof(abi_ulong); 1236 } 1237 #ifdef TARGET_SPARC64 1238 env->canrestore++; 1239 if (env->cleanwin < env->nwindows - 1) 1240 env->cleanwin++; 1241 env->cansave--; 1242 #else 1243 env->wim = new_wim; 1244 #endif 1245 } 1246 1247 static void flush_windows(CPUSPARCState *env) 1248 { 1249 int offset, cwp1; 1250 1251 offset = 1; 1252 for(;;) { 1253 /* if restore would invoke restore_window(), then we can stop */ 1254 cwp1 = cpu_cwp_inc(env, env->cwp + offset); 1255 #ifndef TARGET_SPARC64 1256 if (env->wim & (1 << cwp1)) 1257 break; 1258 #else 1259 if (env->canrestore == 0) 1260 break; 1261 env->cansave++; 1262 env->canrestore--; 1263 #endif 1264 save_window_offset(env, cwp1); 1265 offset++; 1266 } 1267 cwp1 = cpu_cwp_inc(env, env->cwp + 1); 1268 #ifndef TARGET_SPARC64 1269 /* set wim so that restore will reload the registers */ 1270 env->wim = 1 << cwp1; 1271 #endif 1272 #if defined(DEBUG_WIN) 1273 printf("flush_windows: nb=%d\n", offset - 1); 1274 #endif 1275 } 1276 1277 void cpu_loop (CPUSPARCState *env) 1278 { 1279 CPUState *cs = CPU(sparc_env_get_cpu(env)); 1280 int trapnr; 1281 abi_long ret; 1282 target_siginfo_t info; 1283 1284 while (1) { 1285 cpu_exec_start(cs); 1286 trapnr = cpu_exec(cs); 1287 cpu_exec_end(cs); 1288 process_queued_cpu_work(cs); 1289 1290 /* Compute PSR before exposing state. */ 1291 if (env->cc_op != CC_OP_FLAGS) { 1292 cpu_get_psr(env); 1293 } 1294 1295 switch (trapnr) { 1296 #ifndef TARGET_SPARC64 1297 case 0x88: 1298 case 0x90: 1299 #else 1300 case 0x110: 1301 case 0x16d: 1302 #endif 1303 ret = do_syscall (env, env->gregs[1], 1304 env->regwptr[0], env->regwptr[1], 1305 env->regwptr[2], env->regwptr[3], 1306 env->regwptr[4], env->regwptr[5], 1307 0, 0); 1308 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { 1309 break; 1310 } 1311 if ((abi_ulong)ret >= (abi_ulong)(-515)) { 1312 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1313 env->xcc |= PSR_CARRY; 1314 #else 1315 env->psr |= PSR_CARRY; 1316 #endif 1317 ret = -ret; 1318 } else { 1319 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) 1320 env->xcc &= ~PSR_CARRY; 1321 #else 1322 env->psr &= ~PSR_CARRY; 1323 #endif 1324 } 1325 env->regwptr[0] = ret; 1326 /* next instruction */ 1327 env->pc = env->npc; 1328 env->npc = env->npc + 4; 1329 break; 1330 case 0x83: /* flush windows */ 1331 #ifdef TARGET_ABI32 1332 case 0x103: 1333 #endif 1334 flush_windows(env); 1335 /* next instruction */ 1336 env->pc = env->npc; 1337 env->npc = env->npc + 4; 1338 break; 1339 #ifndef TARGET_SPARC64 1340 case TT_WIN_OVF: /* window overflow */ 1341 save_window(env); 1342 break; 1343 case TT_WIN_UNF: /* window underflow */ 1344 restore_window(env); 1345 break; 1346 case TT_TFAULT: 1347 case TT_DFAULT: 1348 { 1349 info.si_signo = TARGET_SIGSEGV; 1350 info.si_errno = 0; 1351 /* XXX: check env->error_code */ 1352 info.si_code = TARGET_SEGV_MAPERR; 1353 info._sifields._sigfault._addr = env->mmuregs[4]; 1354 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1355 } 1356 break; 1357 #else 1358 case TT_SPILL: /* window overflow */ 1359 save_window(env); 1360 break; 1361 case TT_FILL: /* window underflow */ 1362 restore_window(env); 1363 break; 1364 case TT_TFAULT: 1365 case TT_DFAULT: 1366 { 1367 info.si_signo = TARGET_SIGSEGV; 1368 info.si_errno = 0; 1369 /* XXX: check env->error_code */ 1370 info.si_code = TARGET_SEGV_MAPERR; 1371 if (trapnr == TT_DFAULT) 1372 info._sifields._sigfault._addr = env->dmmuregs[4]; 1373 else 1374 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; 1375 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1376 } 1377 break; 1378 #ifndef TARGET_ABI32 1379 case 0x16e: 1380 flush_windows(env); 1381 sparc64_get_context(env); 1382 break; 1383 case 0x16f: 1384 flush_windows(env); 1385 sparc64_set_context(env); 1386 break; 1387 #endif 1388 #endif 1389 case EXCP_INTERRUPT: 1390 /* just indicate that signals should be handled asap */ 1391 break; 1392 case TT_ILL_INSN: 1393 { 1394 info.si_signo = TARGET_SIGILL; 1395 info.si_errno = 0; 1396 info.si_code = TARGET_ILL_ILLOPC; 1397 info._sifields._sigfault._addr = env->pc; 1398 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1399 } 1400 break; 1401 case EXCP_DEBUG: 1402 { 1403 int sig; 1404 1405 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1406 if (sig) 1407 { 1408 info.si_signo = sig; 1409 info.si_errno = 0; 1410 info.si_code = TARGET_TRAP_BRKPT; 1411 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1412 } 1413 } 1414 break; 1415 default: 1416 printf ("Unhandled trap: 0x%x\n", trapnr); 1417 cpu_dump_state(cs, stderr, fprintf, 0); 1418 exit(EXIT_FAILURE); 1419 } 1420 process_pending_signals (env); 1421 } 1422 } 1423 1424 #endif 1425 1426 #ifdef TARGET_PPC 1427 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) 1428 { 1429 return cpu_get_host_ticks(); 1430 } 1431 1432 uint64_t cpu_ppc_load_tbl(CPUPPCState *env) 1433 { 1434 return cpu_ppc_get_tb(env); 1435 } 1436 1437 uint32_t cpu_ppc_load_tbu(CPUPPCState *env) 1438 { 1439 return cpu_ppc_get_tb(env) >> 32; 1440 } 1441 1442 uint64_t cpu_ppc_load_atbl(CPUPPCState *env) 1443 { 1444 return cpu_ppc_get_tb(env); 1445 } 1446 1447 uint32_t cpu_ppc_load_atbu(CPUPPCState *env) 1448 { 1449 return cpu_ppc_get_tb(env) >> 32; 1450 } 1451 1452 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) 1453 __attribute__ (( alias ("cpu_ppc_load_tbu") )); 1454 1455 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) 1456 { 1457 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1458 } 1459 1460 /* XXX: to be fixed */ 1461 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1462 { 1463 return -1; 1464 } 1465 1466 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1467 { 1468 return -1; 1469 } 1470 1471 static int do_store_exclusive(CPUPPCState *env) 1472 { 1473 target_ulong addr; 1474 target_ulong page_addr; 1475 target_ulong val, val2 __attribute__((unused)) = 0; 1476 int flags; 1477 int segv = 0; 1478 1479 addr = env->reserve_ea; 1480 page_addr = addr & TARGET_PAGE_MASK; 1481 start_exclusive(); 1482 mmap_lock(); 1483 flags = page_get_flags(page_addr); 1484 if ((flags & PAGE_READ) == 0) { 1485 segv = 1; 1486 } else { 1487 int reg = env->reserve_info & 0x1f; 1488 int size = env->reserve_info >> 5; 1489 int stored = 0; 1490 1491 if (addr == env->reserve_addr) { 1492 switch (size) { 1493 case 1: segv = get_user_u8(val, addr); break; 1494 case 2: segv = get_user_u16(val, addr); break; 1495 case 4: segv = get_user_u32(val, addr); break; 1496 #if defined(TARGET_PPC64) 1497 case 8: segv = get_user_u64(val, addr); break; 1498 case 16: { 1499 segv = get_user_u64(val, addr); 1500 if (!segv) { 1501 segv = get_user_u64(val2, addr + 8); 1502 } 1503 break; 1504 } 1505 #endif 1506 default: abort(); 1507 } 1508 if (!segv && val == env->reserve_val) { 1509 val = env->gpr[reg]; 1510 switch (size) { 1511 case 1: segv = put_user_u8(val, addr); break; 1512 case 2: segv = put_user_u16(val, addr); break; 1513 case 4: segv = put_user_u32(val, addr); break; 1514 #if defined(TARGET_PPC64) 1515 case 8: segv = put_user_u64(val, addr); break; 1516 case 16: { 1517 if (val2 == env->reserve_val2) { 1518 if (msr_le) { 1519 val2 = val; 1520 val = env->gpr[reg+1]; 1521 } else { 1522 val2 = env->gpr[reg+1]; 1523 } 1524 segv = put_user_u64(val, addr); 1525 if (!segv) { 1526 segv = put_user_u64(val2, addr + 8); 1527 } 1528 } 1529 break; 1530 } 1531 #endif 1532 default: abort(); 1533 } 1534 if (!segv) { 1535 stored = 1; 1536 } 1537 } 1538 } 1539 env->crf[0] = (stored << 1) | xer_so; 1540 env->reserve_addr = (target_ulong)-1; 1541 } 1542 if (!segv) { 1543 env->nip += 4; 1544 } 1545 mmap_unlock(); 1546 end_exclusive(); 1547 return segv; 1548 } 1549 1550 void cpu_loop(CPUPPCState *env) 1551 { 1552 CPUState *cs = CPU(ppc_env_get_cpu(env)); 1553 target_siginfo_t info; 1554 int trapnr; 1555 target_ulong ret; 1556 1557 for(;;) { 1558 cpu_exec_start(cs); 1559 trapnr = cpu_exec(cs); 1560 cpu_exec_end(cs); 1561 process_queued_cpu_work(cs); 1562 1563 switch(trapnr) { 1564 case POWERPC_EXCP_NONE: 1565 /* Just go on */ 1566 break; 1567 case POWERPC_EXCP_CRITICAL: /* Critical input */ 1568 cpu_abort(cs, "Critical interrupt while in user mode. " 1569 "Aborting\n"); 1570 break; 1571 case POWERPC_EXCP_MCHECK: /* Machine check exception */ 1572 cpu_abort(cs, "Machine check exception while in user mode. " 1573 "Aborting\n"); 1574 break; 1575 case POWERPC_EXCP_DSI: /* Data storage exception */ 1576 /* XXX: check this. Seems bugged */ 1577 switch (env->error_code & 0xFF000000) { 1578 case 0x40000000: 1579 case 0x42000000: 1580 info.si_signo = TARGET_SIGSEGV; 1581 info.si_errno = 0; 1582 info.si_code = TARGET_SEGV_MAPERR; 1583 break; 1584 case 0x04000000: 1585 info.si_signo = TARGET_SIGILL; 1586 info.si_errno = 0; 1587 info.si_code = TARGET_ILL_ILLADR; 1588 break; 1589 case 0x08000000: 1590 info.si_signo = TARGET_SIGSEGV; 1591 info.si_errno = 0; 1592 info.si_code = TARGET_SEGV_ACCERR; 1593 break; 1594 default: 1595 /* Let's send a regular segfault... */ 1596 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1597 env->error_code); 1598 info.si_signo = TARGET_SIGSEGV; 1599 info.si_errno = 0; 1600 info.si_code = TARGET_SEGV_MAPERR; 1601 break; 1602 } 1603 info._sifields._sigfault._addr = env->nip; 1604 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1605 break; 1606 case POWERPC_EXCP_ISI: /* Instruction storage exception */ 1607 /* XXX: check this */ 1608 switch (env->error_code & 0xFF000000) { 1609 case 0x40000000: 1610 info.si_signo = TARGET_SIGSEGV; 1611 info.si_errno = 0; 1612 info.si_code = TARGET_SEGV_MAPERR; 1613 break; 1614 case 0x10000000: 1615 case 0x08000000: 1616 info.si_signo = TARGET_SIGSEGV; 1617 info.si_errno = 0; 1618 info.si_code = TARGET_SEGV_ACCERR; 1619 break; 1620 default: 1621 /* Let's send a regular segfault... */ 1622 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", 1623 env->error_code); 1624 info.si_signo = TARGET_SIGSEGV; 1625 info.si_errno = 0; 1626 info.si_code = TARGET_SEGV_MAPERR; 1627 break; 1628 } 1629 info._sifields._sigfault._addr = env->nip - 4; 1630 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1631 break; 1632 case POWERPC_EXCP_EXTERNAL: /* External input */ 1633 cpu_abort(cs, "External interrupt while in user mode. " 1634 "Aborting\n"); 1635 break; 1636 case POWERPC_EXCP_ALIGN: /* Alignment exception */ 1637 /* XXX: check this */ 1638 info.si_signo = TARGET_SIGBUS; 1639 info.si_errno = 0; 1640 info.si_code = TARGET_BUS_ADRALN; 1641 info._sifields._sigfault._addr = env->nip; 1642 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1643 break; 1644 case POWERPC_EXCP_PROGRAM: /* Program exception */ 1645 case POWERPC_EXCP_HV_EMU: /* HV emulation */ 1646 /* XXX: check this */ 1647 switch (env->error_code & ~0xF) { 1648 case POWERPC_EXCP_FP: 1649 info.si_signo = TARGET_SIGFPE; 1650 info.si_errno = 0; 1651 switch (env->error_code & 0xF) { 1652 case POWERPC_EXCP_FP_OX: 1653 info.si_code = TARGET_FPE_FLTOVF; 1654 break; 1655 case POWERPC_EXCP_FP_UX: 1656 info.si_code = TARGET_FPE_FLTUND; 1657 break; 1658 case POWERPC_EXCP_FP_ZX: 1659 case POWERPC_EXCP_FP_VXZDZ: 1660 info.si_code = TARGET_FPE_FLTDIV; 1661 break; 1662 case POWERPC_EXCP_FP_XX: 1663 info.si_code = TARGET_FPE_FLTRES; 1664 break; 1665 case POWERPC_EXCP_FP_VXSOFT: 1666 info.si_code = TARGET_FPE_FLTINV; 1667 break; 1668 case POWERPC_EXCP_FP_VXSNAN: 1669 case POWERPC_EXCP_FP_VXISI: 1670 case POWERPC_EXCP_FP_VXIDI: 1671 case POWERPC_EXCP_FP_VXIMZ: 1672 case POWERPC_EXCP_FP_VXVC: 1673 case POWERPC_EXCP_FP_VXSQRT: 1674 case POWERPC_EXCP_FP_VXCVI: 1675 info.si_code = TARGET_FPE_FLTSUB; 1676 break; 1677 default: 1678 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", 1679 env->error_code); 1680 break; 1681 } 1682 break; 1683 case POWERPC_EXCP_INVAL: 1684 info.si_signo = TARGET_SIGILL; 1685 info.si_errno = 0; 1686 switch (env->error_code & 0xF) { 1687 case POWERPC_EXCP_INVAL_INVAL: 1688 info.si_code = TARGET_ILL_ILLOPC; 1689 break; 1690 case POWERPC_EXCP_INVAL_LSWX: 1691 info.si_code = TARGET_ILL_ILLOPN; 1692 break; 1693 case POWERPC_EXCP_INVAL_SPR: 1694 info.si_code = TARGET_ILL_PRVREG; 1695 break; 1696 case POWERPC_EXCP_INVAL_FP: 1697 info.si_code = TARGET_ILL_COPROC; 1698 break; 1699 default: 1700 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", 1701 env->error_code & 0xF); 1702 info.si_code = TARGET_ILL_ILLADR; 1703 break; 1704 } 1705 break; 1706 case POWERPC_EXCP_PRIV: 1707 info.si_signo = TARGET_SIGILL; 1708 info.si_errno = 0; 1709 switch (env->error_code & 0xF) { 1710 case POWERPC_EXCP_PRIV_OPC: 1711 info.si_code = TARGET_ILL_PRVOPC; 1712 break; 1713 case POWERPC_EXCP_PRIV_REG: 1714 info.si_code = TARGET_ILL_PRVREG; 1715 break; 1716 default: 1717 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", 1718 env->error_code & 0xF); 1719 info.si_code = TARGET_ILL_PRVOPC; 1720 break; 1721 } 1722 break; 1723 case POWERPC_EXCP_TRAP: 1724 cpu_abort(cs, "Tried to call a TRAP\n"); 1725 break; 1726 default: 1727 /* Should not happen ! */ 1728 cpu_abort(cs, "Unknown program exception (%02x)\n", 1729 env->error_code); 1730 break; 1731 } 1732 info._sifields._sigfault._addr = env->nip; 1733 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1734 break; 1735 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ 1736 info.si_signo = TARGET_SIGILL; 1737 info.si_errno = 0; 1738 info.si_code = TARGET_ILL_COPROC; 1739 info._sifields._sigfault._addr = env->nip; 1740 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1741 break; 1742 case POWERPC_EXCP_SYSCALL: /* System call exception */ 1743 cpu_abort(cs, "Syscall exception while in user mode. " 1744 "Aborting\n"); 1745 break; 1746 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ 1747 info.si_signo = TARGET_SIGILL; 1748 info.si_errno = 0; 1749 info.si_code = TARGET_ILL_COPROC; 1750 info._sifields._sigfault._addr = env->nip; 1751 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1752 break; 1753 case POWERPC_EXCP_DECR: /* Decrementer exception */ 1754 cpu_abort(cs, "Decrementer interrupt while in user mode. " 1755 "Aborting\n"); 1756 break; 1757 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ 1758 cpu_abort(cs, "Fix interval timer interrupt while in user mode. " 1759 "Aborting\n"); 1760 break; 1761 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ 1762 cpu_abort(cs, "Watchdog timer interrupt while in user mode. " 1763 "Aborting\n"); 1764 break; 1765 case POWERPC_EXCP_DTLB: /* Data TLB error */ 1766 cpu_abort(cs, "Data TLB exception while in user mode. " 1767 "Aborting\n"); 1768 break; 1769 case POWERPC_EXCP_ITLB: /* Instruction TLB error */ 1770 cpu_abort(cs, "Instruction TLB exception while in user mode. " 1771 "Aborting\n"); 1772 break; 1773 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ 1774 info.si_signo = TARGET_SIGILL; 1775 info.si_errno = 0; 1776 info.si_code = TARGET_ILL_COPROC; 1777 info._sifields._sigfault._addr = env->nip; 1778 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1779 break; 1780 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ 1781 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); 1782 break; 1783 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ 1784 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); 1785 break; 1786 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ 1787 cpu_abort(cs, "Performance monitor exception not handled\n"); 1788 break; 1789 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ 1790 cpu_abort(cs, "Doorbell interrupt while in user mode. " 1791 "Aborting\n"); 1792 break; 1793 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ 1794 cpu_abort(cs, "Doorbell critical interrupt while in user mode. " 1795 "Aborting\n"); 1796 break; 1797 case POWERPC_EXCP_RESET: /* System reset exception */ 1798 cpu_abort(cs, "Reset interrupt while in user mode. " 1799 "Aborting\n"); 1800 break; 1801 case POWERPC_EXCP_DSEG: /* Data segment exception */ 1802 cpu_abort(cs, "Data segment exception while in user mode. " 1803 "Aborting\n"); 1804 break; 1805 case POWERPC_EXCP_ISEG: /* Instruction segment exception */ 1806 cpu_abort(cs, "Instruction segment exception " 1807 "while in user mode. Aborting\n"); 1808 break; 1809 /* PowerPC 64 with hypervisor mode support */ 1810 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ 1811 cpu_abort(cs, "Hypervisor decrementer interrupt " 1812 "while in user mode. Aborting\n"); 1813 break; 1814 case POWERPC_EXCP_TRACE: /* Trace exception */ 1815 /* Nothing to do: 1816 * we use this exception to emulate step-by-step execution mode. 1817 */ 1818 break; 1819 /* PowerPC 64 with hypervisor mode support */ 1820 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ 1821 cpu_abort(cs, "Hypervisor data storage exception " 1822 "while in user mode. Aborting\n"); 1823 break; 1824 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ 1825 cpu_abort(cs, "Hypervisor instruction storage exception " 1826 "while in user mode. Aborting\n"); 1827 break; 1828 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ 1829 cpu_abort(cs, "Hypervisor data segment exception " 1830 "while in user mode. Aborting\n"); 1831 break; 1832 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ 1833 cpu_abort(cs, "Hypervisor instruction segment exception " 1834 "while in user mode. Aborting\n"); 1835 break; 1836 case POWERPC_EXCP_VPU: /* Vector unavailable exception */ 1837 info.si_signo = TARGET_SIGILL; 1838 info.si_errno = 0; 1839 info.si_code = TARGET_ILL_COPROC; 1840 info._sifields._sigfault._addr = env->nip; 1841 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1842 break; 1843 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ 1844 cpu_abort(cs, "Programmable interval timer interrupt " 1845 "while in user mode. Aborting\n"); 1846 break; 1847 case POWERPC_EXCP_IO: /* IO error exception */ 1848 cpu_abort(cs, "IO error exception while in user mode. " 1849 "Aborting\n"); 1850 break; 1851 case POWERPC_EXCP_RUNM: /* Run mode exception */ 1852 cpu_abort(cs, "Run mode exception while in user mode. " 1853 "Aborting\n"); 1854 break; 1855 case POWERPC_EXCP_EMUL: /* Emulation trap exception */ 1856 cpu_abort(cs, "Emulation trap exception not handled\n"); 1857 break; 1858 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ 1859 cpu_abort(cs, "Instruction fetch TLB exception " 1860 "while in user-mode. Aborting"); 1861 break; 1862 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ 1863 cpu_abort(cs, "Data load TLB exception while in user-mode. " 1864 "Aborting"); 1865 break; 1866 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ 1867 cpu_abort(cs, "Data store TLB exception while in user-mode. " 1868 "Aborting"); 1869 break; 1870 case POWERPC_EXCP_FPA: /* Floating-point assist exception */ 1871 cpu_abort(cs, "Floating-point assist exception not handled\n"); 1872 break; 1873 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ 1874 cpu_abort(cs, "Instruction address breakpoint exception " 1875 "not handled\n"); 1876 break; 1877 case POWERPC_EXCP_SMI: /* System management interrupt */ 1878 cpu_abort(cs, "System management interrupt while in user mode. " 1879 "Aborting\n"); 1880 break; 1881 case POWERPC_EXCP_THERM: /* Thermal interrupt */ 1882 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " 1883 "Aborting\n"); 1884 break; 1885 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ 1886 cpu_abort(cs, "Performance monitor exception not handled\n"); 1887 break; 1888 case POWERPC_EXCP_VPUA: /* Vector assist exception */ 1889 cpu_abort(cs, "Vector assist exception not handled\n"); 1890 break; 1891 case POWERPC_EXCP_SOFTP: /* Soft patch exception */ 1892 cpu_abort(cs, "Soft patch exception not handled\n"); 1893 break; 1894 case POWERPC_EXCP_MAINT: /* Maintenance exception */ 1895 cpu_abort(cs, "Maintenance exception while in user mode. " 1896 "Aborting\n"); 1897 break; 1898 case POWERPC_EXCP_STOP: /* stop translation */ 1899 /* We did invalidate the instruction cache. Go on */ 1900 break; 1901 case POWERPC_EXCP_BRANCH: /* branch instruction: */ 1902 /* We just stopped because of a branch. Go on */ 1903 break; 1904 case POWERPC_EXCP_SYSCALL_USER: 1905 /* system call in user-mode emulation */ 1906 /* WARNING: 1907 * PPC ABI uses overflow flag in cr0 to signal an error 1908 * in syscalls. 1909 */ 1910 env->crf[0] &= ~0x1; 1911 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], 1912 env->gpr[5], env->gpr[6], env->gpr[7], 1913 env->gpr[8], 0, 0); 1914 if (ret == -TARGET_ERESTARTSYS) { 1915 break; 1916 } 1917 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { 1918 /* Returning from a successful sigreturn syscall. 1919 Avoid corrupting register state. */ 1920 break; 1921 } 1922 env->nip += 4; 1923 if (ret > (target_ulong)(-515)) { 1924 env->crf[0] |= 0x1; 1925 ret = -ret; 1926 } 1927 env->gpr[3] = ret; 1928 break; 1929 case POWERPC_EXCP_STCX: 1930 if (do_store_exclusive(env)) { 1931 info.si_signo = TARGET_SIGSEGV; 1932 info.si_errno = 0; 1933 info.si_code = TARGET_SEGV_MAPERR; 1934 info._sifields._sigfault._addr = env->nip; 1935 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1936 } 1937 break; 1938 case EXCP_DEBUG: 1939 { 1940 int sig; 1941 1942 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 1943 if (sig) { 1944 info.si_signo = sig; 1945 info.si_errno = 0; 1946 info.si_code = TARGET_TRAP_BRKPT; 1947 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 1948 } 1949 } 1950 break; 1951 case EXCP_INTERRUPT: 1952 /* just indicate that signals should be handled asap */ 1953 break; 1954 default: 1955 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr); 1956 break; 1957 } 1958 process_pending_signals(env); 1959 } 1960 } 1961 #endif 1962 1963 #ifdef TARGET_MIPS 1964 1965 # ifdef TARGET_ABI_MIPSO32 1966 # define MIPS_SYS(name, args) args, 1967 static const uint8_t mips_syscall_args[] = { 1968 MIPS_SYS(sys_syscall , 8) /* 4000 */ 1969 MIPS_SYS(sys_exit , 1) 1970 MIPS_SYS(sys_fork , 0) 1971 MIPS_SYS(sys_read , 3) 1972 MIPS_SYS(sys_write , 3) 1973 MIPS_SYS(sys_open , 3) /* 4005 */ 1974 MIPS_SYS(sys_close , 1) 1975 MIPS_SYS(sys_waitpid , 3) 1976 MIPS_SYS(sys_creat , 2) 1977 MIPS_SYS(sys_link , 2) 1978 MIPS_SYS(sys_unlink , 1) /* 4010 */ 1979 MIPS_SYS(sys_execve , 0) 1980 MIPS_SYS(sys_chdir , 1) 1981 MIPS_SYS(sys_time , 1) 1982 MIPS_SYS(sys_mknod , 3) 1983 MIPS_SYS(sys_chmod , 2) /* 4015 */ 1984 MIPS_SYS(sys_lchown , 3) 1985 MIPS_SYS(sys_ni_syscall , 0) 1986 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ 1987 MIPS_SYS(sys_lseek , 3) 1988 MIPS_SYS(sys_getpid , 0) /* 4020 */ 1989 MIPS_SYS(sys_mount , 5) 1990 MIPS_SYS(sys_umount , 1) 1991 MIPS_SYS(sys_setuid , 1) 1992 MIPS_SYS(sys_getuid , 0) 1993 MIPS_SYS(sys_stime , 1) /* 4025 */ 1994 MIPS_SYS(sys_ptrace , 4) 1995 MIPS_SYS(sys_alarm , 1) 1996 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ 1997 MIPS_SYS(sys_pause , 0) 1998 MIPS_SYS(sys_utime , 2) /* 4030 */ 1999 MIPS_SYS(sys_ni_syscall , 0) 2000 MIPS_SYS(sys_ni_syscall , 0) 2001 MIPS_SYS(sys_access , 2) 2002 MIPS_SYS(sys_nice , 1) 2003 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ 2004 MIPS_SYS(sys_sync , 0) 2005 MIPS_SYS(sys_kill , 2) 2006 MIPS_SYS(sys_rename , 2) 2007 MIPS_SYS(sys_mkdir , 2) 2008 MIPS_SYS(sys_rmdir , 1) /* 4040 */ 2009 MIPS_SYS(sys_dup , 1) 2010 MIPS_SYS(sys_pipe , 0) 2011 MIPS_SYS(sys_times , 1) 2012 MIPS_SYS(sys_ni_syscall , 0) 2013 MIPS_SYS(sys_brk , 1) /* 4045 */ 2014 MIPS_SYS(sys_setgid , 1) 2015 MIPS_SYS(sys_getgid , 0) 2016 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ 2017 MIPS_SYS(sys_geteuid , 0) 2018 MIPS_SYS(sys_getegid , 0) /* 4050 */ 2019 MIPS_SYS(sys_acct , 0) 2020 MIPS_SYS(sys_umount2 , 2) 2021 MIPS_SYS(sys_ni_syscall , 0) 2022 MIPS_SYS(sys_ioctl , 3) 2023 MIPS_SYS(sys_fcntl , 3) /* 4055 */ 2024 MIPS_SYS(sys_ni_syscall , 2) 2025 MIPS_SYS(sys_setpgid , 2) 2026 MIPS_SYS(sys_ni_syscall , 0) 2027 MIPS_SYS(sys_olduname , 1) 2028 MIPS_SYS(sys_umask , 1) /* 4060 */ 2029 MIPS_SYS(sys_chroot , 1) 2030 MIPS_SYS(sys_ustat , 2) 2031 MIPS_SYS(sys_dup2 , 2) 2032 MIPS_SYS(sys_getppid , 0) 2033 MIPS_SYS(sys_getpgrp , 0) /* 4065 */ 2034 MIPS_SYS(sys_setsid , 0) 2035 MIPS_SYS(sys_sigaction , 3) 2036 MIPS_SYS(sys_sgetmask , 0) 2037 MIPS_SYS(sys_ssetmask , 1) 2038 MIPS_SYS(sys_setreuid , 2) /* 4070 */ 2039 MIPS_SYS(sys_setregid , 2) 2040 MIPS_SYS(sys_sigsuspend , 0) 2041 MIPS_SYS(sys_sigpending , 1) 2042 MIPS_SYS(sys_sethostname , 2) 2043 MIPS_SYS(sys_setrlimit , 2) /* 4075 */ 2044 MIPS_SYS(sys_getrlimit , 2) 2045 MIPS_SYS(sys_getrusage , 2) 2046 MIPS_SYS(sys_gettimeofday, 2) 2047 MIPS_SYS(sys_settimeofday, 2) 2048 MIPS_SYS(sys_getgroups , 2) /* 4080 */ 2049 MIPS_SYS(sys_setgroups , 2) 2050 MIPS_SYS(sys_ni_syscall , 0) /* old_select */ 2051 MIPS_SYS(sys_symlink , 2) 2052 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ 2053 MIPS_SYS(sys_readlink , 3) /* 4085 */ 2054 MIPS_SYS(sys_uselib , 1) 2055 MIPS_SYS(sys_swapon , 2) 2056 MIPS_SYS(sys_reboot , 3) 2057 MIPS_SYS(old_readdir , 3) 2058 MIPS_SYS(old_mmap , 6) /* 4090 */ 2059 MIPS_SYS(sys_munmap , 2) 2060 MIPS_SYS(sys_truncate , 2) 2061 MIPS_SYS(sys_ftruncate , 2) 2062 MIPS_SYS(sys_fchmod , 2) 2063 MIPS_SYS(sys_fchown , 3) /* 4095 */ 2064 MIPS_SYS(sys_getpriority , 2) 2065 MIPS_SYS(sys_setpriority , 3) 2066 MIPS_SYS(sys_ni_syscall , 0) 2067 MIPS_SYS(sys_statfs , 2) 2068 MIPS_SYS(sys_fstatfs , 2) /* 4100 */ 2069 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ 2070 MIPS_SYS(sys_socketcall , 2) 2071 MIPS_SYS(sys_syslog , 3) 2072 MIPS_SYS(sys_setitimer , 3) 2073 MIPS_SYS(sys_getitimer , 2) /* 4105 */ 2074 MIPS_SYS(sys_newstat , 2) 2075 MIPS_SYS(sys_newlstat , 2) 2076 MIPS_SYS(sys_newfstat , 2) 2077 MIPS_SYS(sys_uname , 1) 2078 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ 2079 MIPS_SYS(sys_vhangup , 0) 2080 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ 2081 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ 2082 MIPS_SYS(sys_wait4 , 4) 2083 MIPS_SYS(sys_swapoff , 1) /* 4115 */ 2084 MIPS_SYS(sys_sysinfo , 1) 2085 MIPS_SYS(sys_ipc , 6) 2086 MIPS_SYS(sys_fsync , 1) 2087 MIPS_SYS(sys_sigreturn , 0) 2088 MIPS_SYS(sys_clone , 6) /* 4120 */ 2089 MIPS_SYS(sys_setdomainname, 2) 2090 MIPS_SYS(sys_newuname , 1) 2091 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ 2092 MIPS_SYS(sys_adjtimex , 1) 2093 MIPS_SYS(sys_mprotect , 3) /* 4125 */ 2094 MIPS_SYS(sys_sigprocmask , 3) 2095 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ 2096 MIPS_SYS(sys_init_module , 5) 2097 MIPS_SYS(sys_delete_module, 1) 2098 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ 2099 MIPS_SYS(sys_quotactl , 0) 2100 MIPS_SYS(sys_getpgid , 1) 2101 MIPS_SYS(sys_fchdir , 1) 2102 MIPS_SYS(sys_bdflush , 2) 2103 MIPS_SYS(sys_sysfs , 3) /* 4135 */ 2104 MIPS_SYS(sys_personality , 1) 2105 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ 2106 MIPS_SYS(sys_setfsuid , 1) 2107 MIPS_SYS(sys_setfsgid , 1) 2108 MIPS_SYS(sys_llseek , 5) /* 4140 */ 2109 MIPS_SYS(sys_getdents , 3) 2110 MIPS_SYS(sys_select , 5) 2111 MIPS_SYS(sys_flock , 2) 2112 MIPS_SYS(sys_msync , 3) 2113 MIPS_SYS(sys_readv , 3) /* 4145 */ 2114 MIPS_SYS(sys_writev , 3) 2115 MIPS_SYS(sys_cacheflush , 3) 2116 MIPS_SYS(sys_cachectl , 3) 2117 MIPS_SYS(sys_sysmips , 4) 2118 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ 2119 MIPS_SYS(sys_getsid , 1) 2120 MIPS_SYS(sys_fdatasync , 0) 2121 MIPS_SYS(sys_sysctl , 1) 2122 MIPS_SYS(sys_mlock , 2) 2123 MIPS_SYS(sys_munlock , 2) /* 4155 */ 2124 MIPS_SYS(sys_mlockall , 1) 2125 MIPS_SYS(sys_munlockall , 0) 2126 MIPS_SYS(sys_sched_setparam, 2) 2127 MIPS_SYS(sys_sched_getparam, 2) 2128 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ 2129 MIPS_SYS(sys_sched_getscheduler, 1) 2130 MIPS_SYS(sys_sched_yield , 0) 2131 MIPS_SYS(sys_sched_get_priority_max, 1) 2132 MIPS_SYS(sys_sched_get_priority_min, 1) 2133 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ 2134 MIPS_SYS(sys_nanosleep, 2) 2135 MIPS_SYS(sys_mremap , 5) 2136 MIPS_SYS(sys_accept , 3) 2137 MIPS_SYS(sys_bind , 3) 2138 MIPS_SYS(sys_connect , 3) /* 4170 */ 2139 MIPS_SYS(sys_getpeername , 3) 2140 MIPS_SYS(sys_getsockname , 3) 2141 MIPS_SYS(sys_getsockopt , 5) 2142 MIPS_SYS(sys_listen , 2) 2143 MIPS_SYS(sys_recv , 4) /* 4175 */ 2144 MIPS_SYS(sys_recvfrom , 6) 2145 MIPS_SYS(sys_recvmsg , 3) 2146 MIPS_SYS(sys_send , 4) 2147 MIPS_SYS(sys_sendmsg , 3) 2148 MIPS_SYS(sys_sendto , 6) /* 4180 */ 2149 MIPS_SYS(sys_setsockopt , 5) 2150 MIPS_SYS(sys_shutdown , 2) 2151 MIPS_SYS(sys_socket , 3) 2152 MIPS_SYS(sys_socketpair , 4) 2153 MIPS_SYS(sys_setresuid , 3) /* 4185 */ 2154 MIPS_SYS(sys_getresuid , 3) 2155 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ 2156 MIPS_SYS(sys_poll , 3) 2157 MIPS_SYS(sys_nfsservctl , 3) 2158 MIPS_SYS(sys_setresgid , 3) /* 4190 */ 2159 MIPS_SYS(sys_getresgid , 3) 2160 MIPS_SYS(sys_prctl , 5) 2161 MIPS_SYS(sys_rt_sigreturn, 0) 2162 MIPS_SYS(sys_rt_sigaction, 4) 2163 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ 2164 MIPS_SYS(sys_rt_sigpending, 2) 2165 MIPS_SYS(sys_rt_sigtimedwait, 4) 2166 MIPS_SYS(sys_rt_sigqueueinfo, 3) 2167 MIPS_SYS(sys_rt_sigsuspend, 0) 2168 MIPS_SYS(sys_pread64 , 6) /* 4200 */ 2169 MIPS_SYS(sys_pwrite64 , 6) 2170 MIPS_SYS(sys_chown , 3) 2171 MIPS_SYS(sys_getcwd , 2) 2172 MIPS_SYS(sys_capget , 2) 2173 MIPS_SYS(sys_capset , 2) /* 4205 */ 2174 MIPS_SYS(sys_sigaltstack , 2) 2175 MIPS_SYS(sys_sendfile , 4) 2176 MIPS_SYS(sys_ni_syscall , 0) 2177 MIPS_SYS(sys_ni_syscall , 0) 2178 MIPS_SYS(sys_mmap2 , 6) /* 4210 */ 2179 MIPS_SYS(sys_truncate64 , 4) 2180 MIPS_SYS(sys_ftruncate64 , 4) 2181 MIPS_SYS(sys_stat64 , 2) 2182 MIPS_SYS(sys_lstat64 , 2) 2183 MIPS_SYS(sys_fstat64 , 2) /* 4215 */ 2184 MIPS_SYS(sys_pivot_root , 2) 2185 MIPS_SYS(sys_mincore , 3) 2186 MIPS_SYS(sys_madvise , 3) 2187 MIPS_SYS(sys_getdents64 , 3) 2188 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ 2189 MIPS_SYS(sys_ni_syscall , 0) 2190 MIPS_SYS(sys_gettid , 0) 2191 MIPS_SYS(sys_readahead , 5) 2192 MIPS_SYS(sys_setxattr , 5) 2193 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ 2194 MIPS_SYS(sys_fsetxattr , 5) 2195 MIPS_SYS(sys_getxattr , 4) 2196 MIPS_SYS(sys_lgetxattr , 4) 2197 MIPS_SYS(sys_fgetxattr , 4) 2198 MIPS_SYS(sys_listxattr , 3) /* 4230 */ 2199 MIPS_SYS(sys_llistxattr , 3) 2200 MIPS_SYS(sys_flistxattr , 3) 2201 MIPS_SYS(sys_removexattr , 2) 2202 MIPS_SYS(sys_lremovexattr, 2) 2203 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ 2204 MIPS_SYS(sys_tkill , 2) 2205 MIPS_SYS(sys_sendfile64 , 5) 2206 MIPS_SYS(sys_futex , 6) 2207 MIPS_SYS(sys_sched_setaffinity, 3) 2208 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ 2209 MIPS_SYS(sys_io_setup , 2) 2210 MIPS_SYS(sys_io_destroy , 1) 2211 MIPS_SYS(sys_io_getevents, 5) 2212 MIPS_SYS(sys_io_submit , 3) 2213 MIPS_SYS(sys_io_cancel , 3) /* 4245 */ 2214 MIPS_SYS(sys_exit_group , 1) 2215 MIPS_SYS(sys_lookup_dcookie, 3) 2216 MIPS_SYS(sys_epoll_create, 1) 2217 MIPS_SYS(sys_epoll_ctl , 4) 2218 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ 2219 MIPS_SYS(sys_remap_file_pages, 5) 2220 MIPS_SYS(sys_set_tid_address, 1) 2221 MIPS_SYS(sys_restart_syscall, 0) 2222 MIPS_SYS(sys_fadvise64_64, 7) 2223 MIPS_SYS(sys_statfs64 , 3) /* 4255 */ 2224 MIPS_SYS(sys_fstatfs64 , 2) 2225 MIPS_SYS(sys_timer_create, 3) 2226 MIPS_SYS(sys_timer_settime, 4) 2227 MIPS_SYS(sys_timer_gettime, 2) 2228 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ 2229 MIPS_SYS(sys_timer_delete, 1) 2230 MIPS_SYS(sys_clock_settime, 2) 2231 MIPS_SYS(sys_clock_gettime, 2) 2232 MIPS_SYS(sys_clock_getres, 2) 2233 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ 2234 MIPS_SYS(sys_tgkill , 3) 2235 MIPS_SYS(sys_utimes , 2) 2236 MIPS_SYS(sys_mbind , 4) 2237 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ 2238 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ 2239 MIPS_SYS(sys_mq_open , 4) 2240 MIPS_SYS(sys_mq_unlink , 1) 2241 MIPS_SYS(sys_mq_timedsend, 5) 2242 MIPS_SYS(sys_mq_timedreceive, 5) 2243 MIPS_SYS(sys_mq_notify , 2) /* 4275 */ 2244 MIPS_SYS(sys_mq_getsetattr, 3) 2245 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ 2246 MIPS_SYS(sys_waitid , 4) 2247 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ 2248 MIPS_SYS(sys_add_key , 5) 2249 MIPS_SYS(sys_request_key, 4) 2250 MIPS_SYS(sys_keyctl , 5) 2251 MIPS_SYS(sys_set_thread_area, 1) 2252 MIPS_SYS(sys_inotify_init, 0) 2253 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ 2254 MIPS_SYS(sys_inotify_rm_watch, 2) 2255 MIPS_SYS(sys_migrate_pages, 4) 2256 MIPS_SYS(sys_openat, 4) 2257 MIPS_SYS(sys_mkdirat, 3) 2258 MIPS_SYS(sys_mknodat, 4) /* 4290 */ 2259 MIPS_SYS(sys_fchownat, 5) 2260 MIPS_SYS(sys_futimesat, 3) 2261 MIPS_SYS(sys_fstatat64, 4) 2262 MIPS_SYS(sys_unlinkat, 3) 2263 MIPS_SYS(sys_renameat, 4) /* 4295 */ 2264 MIPS_SYS(sys_linkat, 5) 2265 MIPS_SYS(sys_symlinkat, 3) 2266 MIPS_SYS(sys_readlinkat, 4) 2267 MIPS_SYS(sys_fchmodat, 3) 2268 MIPS_SYS(sys_faccessat, 3) /* 4300 */ 2269 MIPS_SYS(sys_pselect6, 6) 2270 MIPS_SYS(sys_ppoll, 5) 2271 MIPS_SYS(sys_unshare, 1) 2272 MIPS_SYS(sys_splice, 6) 2273 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ 2274 MIPS_SYS(sys_tee, 4) 2275 MIPS_SYS(sys_vmsplice, 4) 2276 MIPS_SYS(sys_move_pages, 6) 2277 MIPS_SYS(sys_set_robust_list, 2) 2278 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ 2279 MIPS_SYS(sys_kexec_load, 4) 2280 MIPS_SYS(sys_getcpu, 3) 2281 MIPS_SYS(sys_epoll_pwait, 6) 2282 MIPS_SYS(sys_ioprio_set, 3) 2283 MIPS_SYS(sys_ioprio_get, 2) 2284 MIPS_SYS(sys_utimensat, 4) 2285 MIPS_SYS(sys_signalfd, 3) 2286 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ 2287 MIPS_SYS(sys_eventfd, 1) 2288 MIPS_SYS(sys_fallocate, 6) /* 4320 */ 2289 MIPS_SYS(sys_timerfd_create, 2) 2290 MIPS_SYS(sys_timerfd_gettime, 2) 2291 MIPS_SYS(sys_timerfd_settime, 4) 2292 MIPS_SYS(sys_signalfd4, 4) 2293 MIPS_SYS(sys_eventfd2, 2) /* 4325 */ 2294 MIPS_SYS(sys_epoll_create1, 1) 2295 MIPS_SYS(sys_dup3, 3) 2296 MIPS_SYS(sys_pipe2, 2) 2297 MIPS_SYS(sys_inotify_init1, 1) 2298 MIPS_SYS(sys_preadv, 5) /* 4330 */ 2299 MIPS_SYS(sys_pwritev, 5) 2300 MIPS_SYS(sys_rt_tgsigqueueinfo, 4) 2301 MIPS_SYS(sys_perf_event_open, 5) 2302 MIPS_SYS(sys_accept4, 4) 2303 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ 2304 MIPS_SYS(sys_fanotify_init, 2) 2305 MIPS_SYS(sys_fanotify_mark, 6) 2306 MIPS_SYS(sys_prlimit64, 4) 2307 MIPS_SYS(sys_name_to_handle_at, 5) 2308 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ 2309 MIPS_SYS(sys_clock_adjtime, 2) 2310 MIPS_SYS(sys_syncfs, 1) 2311 MIPS_SYS(sys_sendmmsg, 4) 2312 MIPS_SYS(sys_setns, 2) 2313 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */ 2314 MIPS_SYS(sys_process_vm_writev, 6) 2315 MIPS_SYS(sys_kcmp, 5) 2316 MIPS_SYS(sys_finit_module, 3) 2317 MIPS_SYS(sys_sched_setattr, 2) 2318 MIPS_SYS(sys_sched_getattr, 3) /* 350 */ 2319 MIPS_SYS(sys_renameat2, 5) 2320 MIPS_SYS(sys_seccomp, 3) 2321 MIPS_SYS(sys_getrandom, 3) 2322 MIPS_SYS(sys_memfd_create, 2) 2323 MIPS_SYS(sys_bpf, 3) /* 355 */ 2324 MIPS_SYS(sys_execveat, 5) 2325 MIPS_SYS(sys_userfaultfd, 1) 2326 MIPS_SYS(sys_membarrier, 2) 2327 MIPS_SYS(sys_mlock2, 3) 2328 MIPS_SYS(sys_copy_file_range, 6) /* 360 */ 2329 MIPS_SYS(sys_preadv2, 6) 2330 MIPS_SYS(sys_pwritev2, 6) 2331 }; 2332 # undef MIPS_SYS 2333 # endif /* O32 */ 2334 2335 static int do_store_exclusive(CPUMIPSState *env) 2336 { 2337 target_ulong addr; 2338 target_ulong page_addr; 2339 target_ulong val; 2340 int flags; 2341 int segv = 0; 2342 int reg; 2343 int d; 2344 2345 addr = env->lladdr; 2346 page_addr = addr & TARGET_PAGE_MASK; 2347 start_exclusive(); 2348 mmap_lock(); 2349 flags = page_get_flags(page_addr); 2350 if ((flags & PAGE_READ) == 0) { 2351 segv = 1; 2352 } else { 2353 reg = env->llreg & 0x1f; 2354 d = (env->llreg & 0x20) != 0; 2355 if (d) { 2356 segv = get_user_s64(val, addr); 2357 } else { 2358 segv = get_user_s32(val, addr); 2359 } 2360 if (!segv) { 2361 if (val != env->llval) { 2362 env->active_tc.gpr[reg] = 0; 2363 } else { 2364 if (d) { 2365 segv = put_user_u64(env->llnewval, addr); 2366 } else { 2367 segv = put_user_u32(env->llnewval, addr); 2368 } 2369 if (!segv) { 2370 env->active_tc.gpr[reg] = 1; 2371 } 2372 } 2373 } 2374 } 2375 env->lladdr = -1; 2376 if (!segv) { 2377 env->active_tc.PC += 4; 2378 } 2379 mmap_unlock(); 2380 end_exclusive(); 2381 return segv; 2382 } 2383 2384 /* Break codes */ 2385 enum { 2386 BRK_OVERFLOW = 6, 2387 BRK_DIVZERO = 7 2388 }; 2389 2390 static int do_break(CPUMIPSState *env, target_siginfo_t *info, 2391 unsigned int code) 2392 { 2393 int ret = -1; 2394 2395 switch (code) { 2396 case BRK_OVERFLOW: 2397 case BRK_DIVZERO: 2398 info->si_signo = TARGET_SIGFPE; 2399 info->si_errno = 0; 2400 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; 2401 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 2402 ret = 0; 2403 break; 2404 default: 2405 info->si_signo = TARGET_SIGTRAP; 2406 info->si_errno = 0; 2407 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info); 2408 ret = 0; 2409 break; 2410 } 2411 2412 return ret; 2413 } 2414 2415 void cpu_loop(CPUMIPSState *env) 2416 { 2417 CPUState *cs = CPU(mips_env_get_cpu(env)); 2418 target_siginfo_t info; 2419 int trapnr; 2420 abi_long ret; 2421 # ifdef TARGET_ABI_MIPSO32 2422 unsigned int syscall_num; 2423 # endif 2424 2425 for(;;) { 2426 cpu_exec_start(cs); 2427 trapnr = cpu_exec(cs); 2428 cpu_exec_end(cs); 2429 process_queued_cpu_work(cs); 2430 2431 switch(trapnr) { 2432 case EXCP_SYSCALL: 2433 env->active_tc.PC += 4; 2434 # ifdef TARGET_ABI_MIPSO32 2435 syscall_num = env->active_tc.gpr[2] - 4000; 2436 if (syscall_num >= sizeof(mips_syscall_args)) { 2437 ret = -TARGET_ENOSYS; 2438 } else { 2439 int nb_args; 2440 abi_ulong sp_reg; 2441 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; 2442 2443 nb_args = mips_syscall_args[syscall_num]; 2444 sp_reg = env->active_tc.gpr[29]; 2445 switch (nb_args) { 2446 /* these arguments are taken from the stack */ 2447 case 8: 2448 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { 2449 goto done_syscall; 2450 } 2451 case 7: 2452 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { 2453 goto done_syscall; 2454 } 2455 case 6: 2456 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { 2457 goto done_syscall; 2458 } 2459 case 5: 2460 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { 2461 goto done_syscall; 2462 } 2463 default: 2464 break; 2465 } 2466 ret = do_syscall(env, env->active_tc.gpr[2], 2467 env->active_tc.gpr[4], 2468 env->active_tc.gpr[5], 2469 env->active_tc.gpr[6], 2470 env->active_tc.gpr[7], 2471 arg5, arg6, arg7, arg8); 2472 } 2473 done_syscall: 2474 # else 2475 ret = do_syscall(env, env->active_tc.gpr[2], 2476 env->active_tc.gpr[4], env->active_tc.gpr[5], 2477 env->active_tc.gpr[6], env->active_tc.gpr[7], 2478 env->active_tc.gpr[8], env->active_tc.gpr[9], 2479 env->active_tc.gpr[10], env->active_tc.gpr[11]); 2480 # endif /* O32 */ 2481 if (ret == -TARGET_ERESTARTSYS) { 2482 env->active_tc.PC -= 4; 2483 break; 2484 } 2485 if (ret == -TARGET_QEMU_ESIGRETURN) { 2486 /* Returning from a successful sigreturn syscall. 2487 Avoid clobbering register state. */ 2488 break; 2489 } 2490 if ((abi_ulong)ret >= (abi_ulong)-1133) { 2491 env->active_tc.gpr[7] = 1; /* error flag */ 2492 ret = -ret; 2493 } else { 2494 env->active_tc.gpr[7] = 0; /* error flag */ 2495 } 2496 env->active_tc.gpr[2] = ret; 2497 break; 2498 case EXCP_TLBL: 2499 case EXCP_TLBS: 2500 case EXCP_AdEL: 2501 case EXCP_AdES: 2502 info.si_signo = TARGET_SIGSEGV; 2503 info.si_errno = 0; 2504 /* XXX: check env->error_code */ 2505 info.si_code = TARGET_SEGV_MAPERR; 2506 info._sifields._sigfault._addr = env->CP0_BadVAddr; 2507 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2508 break; 2509 case EXCP_CpU: 2510 case EXCP_RI: 2511 info.si_signo = TARGET_SIGILL; 2512 info.si_errno = 0; 2513 info.si_code = 0; 2514 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2515 break; 2516 case EXCP_INTERRUPT: 2517 /* just indicate that signals should be handled asap */ 2518 break; 2519 case EXCP_DEBUG: 2520 { 2521 int sig; 2522 2523 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2524 if (sig) 2525 { 2526 info.si_signo = sig; 2527 info.si_errno = 0; 2528 info.si_code = TARGET_TRAP_BRKPT; 2529 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2530 } 2531 } 2532 break; 2533 case EXCP_SC: 2534 if (do_store_exclusive(env)) { 2535 info.si_signo = TARGET_SIGSEGV; 2536 info.si_errno = 0; 2537 info.si_code = TARGET_SEGV_MAPERR; 2538 info._sifields._sigfault._addr = env->active_tc.PC; 2539 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2540 } 2541 break; 2542 case EXCP_DSPDIS: 2543 info.si_signo = TARGET_SIGILL; 2544 info.si_errno = 0; 2545 info.si_code = TARGET_ILL_ILLOPC; 2546 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2547 break; 2548 /* The code below was inspired by the MIPS Linux kernel trap 2549 * handling code in arch/mips/kernel/traps.c. 2550 */ 2551 case EXCP_BREAK: 2552 { 2553 abi_ulong trap_instr; 2554 unsigned int code; 2555 2556 if (env->hflags & MIPS_HFLAG_M16) { 2557 if (env->insn_flags & ASE_MICROMIPS) { 2558 /* microMIPS mode */ 2559 ret = get_user_u16(trap_instr, env->active_tc.PC); 2560 if (ret != 0) { 2561 goto error; 2562 } 2563 2564 if ((trap_instr >> 10) == 0x11) { 2565 /* 16-bit instruction */ 2566 code = trap_instr & 0xf; 2567 } else { 2568 /* 32-bit instruction */ 2569 abi_ulong instr_lo; 2570 2571 ret = get_user_u16(instr_lo, 2572 env->active_tc.PC + 2); 2573 if (ret != 0) { 2574 goto error; 2575 } 2576 trap_instr = (trap_instr << 16) | instr_lo; 2577 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2578 /* Unfortunately, microMIPS also suffers from 2579 the old assembler bug... */ 2580 if (code >= (1 << 10)) { 2581 code >>= 10; 2582 } 2583 } 2584 } else { 2585 /* MIPS16e mode */ 2586 ret = get_user_u16(trap_instr, env->active_tc.PC); 2587 if (ret != 0) { 2588 goto error; 2589 } 2590 code = (trap_instr >> 6) & 0x3f; 2591 } 2592 } else { 2593 ret = get_user_u32(trap_instr, env->active_tc.PC); 2594 if (ret != 0) { 2595 goto error; 2596 } 2597 2598 /* As described in the original Linux kernel code, the 2599 * below checks on 'code' are to work around an old 2600 * assembly bug. 2601 */ 2602 code = ((trap_instr >> 6) & ((1 << 20) - 1)); 2603 if (code >= (1 << 10)) { 2604 code >>= 10; 2605 } 2606 } 2607 2608 if (do_break(env, &info, code) != 0) { 2609 goto error; 2610 } 2611 } 2612 break; 2613 case EXCP_TRAP: 2614 { 2615 abi_ulong trap_instr; 2616 unsigned int code = 0; 2617 2618 if (env->hflags & MIPS_HFLAG_M16) { 2619 /* microMIPS mode */ 2620 abi_ulong instr[2]; 2621 2622 ret = get_user_u16(instr[0], env->active_tc.PC) || 2623 get_user_u16(instr[1], env->active_tc.PC + 2); 2624 2625 trap_instr = (instr[0] << 16) | instr[1]; 2626 } else { 2627 ret = get_user_u32(trap_instr, env->active_tc.PC); 2628 } 2629 2630 if (ret != 0) { 2631 goto error; 2632 } 2633 2634 /* The immediate versions don't provide a code. */ 2635 if (!(trap_instr & 0xFC000000)) { 2636 if (env->hflags & MIPS_HFLAG_M16) { 2637 /* microMIPS mode */ 2638 code = ((trap_instr >> 12) & ((1 << 4) - 1)); 2639 } else { 2640 code = ((trap_instr >> 6) & ((1 << 10) - 1)); 2641 } 2642 } 2643 2644 if (do_break(env, &info, code) != 0) { 2645 goto error; 2646 } 2647 } 2648 break; 2649 default: 2650 error: 2651 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 2652 abort(); 2653 } 2654 process_pending_signals(env); 2655 } 2656 } 2657 #endif 2658 2659 #ifdef TARGET_OPENRISC 2660 2661 void cpu_loop(CPUOpenRISCState *env) 2662 { 2663 CPUState *cs = CPU(openrisc_env_get_cpu(env)); 2664 int trapnr, gdbsig; 2665 abi_long ret; 2666 2667 for (;;) { 2668 cpu_exec_start(cs); 2669 trapnr = cpu_exec(cs); 2670 cpu_exec_end(cs); 2671 process_queued_cpu_work(cs); 2672 gdbsig = 0; 2673 2674 switch (trapnr) { 2675 case EXCP_RESET: 2676 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc); 2677 exit(EXIT_FAILURE); 2678 break; 2679 case EXCP_BUSERR: 2680 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc); 2681 gdbsig = TARGET_SIGBUS; 2682 break; 2683 case EXCP_DPF: 2684 case EXCP_IPF: 2685 cpu_dump_state(cs, stderr, fprintf, 0); 2686 gdbsig = TARGET_SIGSEGV; 2687 break; 2688 case EXCP_TICK: 2689 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc); 2690 break; 2691 case EXCP_ALIGN: 2692 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc); 2693 gdbsig = TARGET_SIGBUS; 2694 break; 2695 case EXCP_ILLEGAL: 2696 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc); 2697 gdbsig = TARGET_SIGILL; 2698 break; 2699 case EXCP_INT: 2700 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc); 2701 break; 2702 case EXCP_DTLBMISS: 2703 case EXCP_ITLBMISS: 2704 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n"); 2705 break; 2706 case EXCP_RANGE: 2707 qemu_log_mask(CPU_LOG_INT, "\nRange\n"); 2708 gdbsig = TARGET_SIGSEGV; 2709 break; 2710 case EXCP_SYSCALL: 2711 env->pc += 4; /* 0xc00; */ 2712 ret = do_syscall(env, 2713 env->gpr[11], /* return value */ 2714 env->gpr[3], /* r3 - r7 are params */ 2715 env->gpr[4], 2716 env->gpr[5], 2717 env->gpr[6], 2718 env->gpr[7], 2719 env->gpr[8], 0, 0); 2720 if (ret == -TARGET_ERESTARTSYS) { 2721 env->pc -= 4; 2722 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2723 env->gpr[11] = ret; 2724 } 2725 break; 2726 case EXCP_FPE: 2727 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n"); 2728 break; 2729 case EXCP_TRAP: 2730 qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); 2731 gdbsig = TARGET_SIGTRAP; 2732 break; 2733 case EXCP_NR: 2734 qemu_log_mask(CPU_LOG_INT, "\nNR\n"); 2735 break; 2736 default: 2737 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", 2738 trapnr); 2739 gdbsig = TARGET_SIGILL; 2740 break; 2741 } 2742 if (gdbsig) { 2743 gdb_handlesig(cs, gdbsig); 2744 if (gdbsig != TARGET_SIGTRAP) { 2745 exit(EXIT_FAILURE); 2746 } 2747 } 2748 2749 process_pending_signals(env); 2750 } 2751 } 2752 2753 #endif /* TARGET_OPENRISC */ 2754 2755 #ifdef TARGET_SH4 2756 void cpu_loop(CPUSH4State *env) 2757 { 2758 CPUState *cs = CPU(sh_env_get_cpu(env)); 2759 int trapnr, ret; 2760 target_siginfo_t info; 2761 2762 while (1) { 2763 cpu_exec_start(cs); 2764 trapnr = cpu_exec(cs); 2765 cpu_exec_end(cs); 2766 process_queued_cpu_work(cs); 2767 2768 switch (trapnr) { 2769 case 0x160: 2770 env->pc += 2; 2771 ret = do_syscall(env, 2772 env->gregs[3], 2773 env->gregs[4], 2774 env->gregs[5], 2775 env->gregs[6], 2776 env->gregs[7], 2777 env->gregs[0], 2778 env->gregs[1], 2779 0, 0); 2780 if (ret == -TARGET_ERESTARTSYS) { 2781 env->pc -= 2; 2782 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2783 env->gregs[0] = ret; 2784 } 2785 break; 2786 case EXCP_INTERRUPT: 2787 /* just indicate that signals should be handled asap */ 2788 break; 2789 case EXCP_DEBUG: 2790 { 2791 int sig; 2792 2793 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2794 if (sig) 2795 { 2796 info.si_signo = sig; 2797 info.si_errno = 0; 2798 info.si_code = TARGET_TRAP_BRKPT; 2799 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2800 } 2801 } 2802 break; 2803 case 0xa0: 2804 case 0xc0: 2805 info.si_signo = TARGET_SIGSEGV; 2806 info.si_errno = 0; 2807 info.si_code = TARGET_SEGV_MAPERR; 2808 info._sifields._sigfault._addr = env->tea; 2809 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2810 break; 2811 2812 default: 2813 printf ("Unhandled trap: 0x%x\n", trapnr); 2814 cpu_dump_state(cs, stderr, fprintf, 0); 2815 exit(EXIT_FAILURE); 2816 } 2817 process_pending_signals (env); 2818 } 2819 } 2820 #endif 2821 2822 #ifdef TARGET_CRIS 2823 void cpu_loop(CPUCRISState *env) 2824 { 2825 CPUState *cs = CPU(cris_env_get_cpu(env)); 2826 int trapnr, ret; 2827 target_siginfo_t info; 2828 2829 while (1) { 2830 cpu_exec_start(cs); 2831 trapnr = cpu_exec(cs); 2832 cpu_exec_end(cs); 2833 process_queued_cpu_work(cs); 2834 2835 switch (trapnr) { 2836 case 0xaa: 2837 { 2838 info.si_signo = TARGET_SIGSEGV; 2839 info.si_errno = 0; 2840 /* XXX: check env->error_code */ 2841 info.si_code = TARGET_SEGV_MAPERR; 2842 info._sifields._sigfault._addr = env->pregs[PR_EDA]; 2843 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2844 } 2845 break; 2846 case EXCP_INTERRUPT: 2847 /* just indicate that signals should be handled asap */ 2848 break; 2849 case EXCP_BREAK: 2850 ret = do_syscall(env, 2851 env->regs[9], 2852 env->regs[10], 2853 env->regs[11], 2854 env->regs[12], 2855 env->regs[13], 2856 env->pregs[7], 2857 env->pregs[11], 2858 0, 0); 2859 if (ret == -TARGET_ERESTARTSYS) { 2860 env->pc -= 2; 2861 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2862 env->regs[10] = ret; 2863 } 2864 break; 2865 case EXCP_DEBUG: 2866 { 2867 int sig; 2868 2869 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2870 if (sig) 2871 { 2872 info.si_signo = sig; 2873 info.si_errno = 0; 2874 info.si_code = TARGET_TRAP_BRKPT; 2875 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2876 } 2877 } 2878 break; 2879 default: 2880 printf ("Unhandled trap: 0x%x\n", trapnr); 2881 cpu_dump_state(cs, stderr, fprintf, 0); 2882 exit(EXIT_FAILURE); 2883 } 2884 process_pending_signals (env); 2885 } 2886 } 2887 #endif 2888 2889 #ifdef TARGET_MICROBLAZE 2890 void cpu_loop(CPUMBState *env) 2891 { 2892 CPUState *cs = CPU(mb_env_get_cpu(env)); 2893 int trapnr, ret; 2894 target_siginfo_t info; 2895 2896 while (1) { 2897 cpu_exec_start(cs); 2898 trapnr = cpu_exec(cs); 2899 cpu_exec_end(cs); 2900 process_queued_cpu_work(cs); 2901 2902 switch (trapnr) { 2903 case 0xaa: 2904 { 2905 info.si_signo = TARGET_SIGSEGV; 2906 info.si_errno = 0; 2907 /* XXX: check env->error_code */ 2908 info.si_code = TARGET_SEGV_MAPERR; 2909 info._sifields._sigfault._addr = 0; 2910 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2911 } 2912 break; 2913 case EXCP_INTERRUPT: 2914 /* just indicate that signals should be handled asap */ 2915 break; 2916 case EXCP_BREAK: 2917 /* Return address is 4 bytes after the call. */ 2918 env->regs[14] += 4; 2919 env->sregs[SR_PC] = env->regs[14]; 2920 ret = do_syscall(env, 2921 env->regs[12], 2922 env->regs[5], 2923 env->regs[6], 2924 env->regs[7], 2925 env->regs[8], 2926 env->regs[9], 2927 env->regs[10], 2928 0, 0); 2929 if (ret == -TARGET_ERESTARTSYS) { 2930 /* Wind back to before the syscall. */ 2931 env->sregs[SR_PC] -= 4; 2932 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 2933 env->regs[3] = ret; 2934 } 2935 /* All syscall exits result in guest r14 being equal to the 2936 * PC we return to, because the kernel syscall exit "rtbd" does 2937 * this. (This is true even for sigreturn(); note that r14 is 2938 * not a userspace-usable register, as the kernel may clobber it 2939 * at any point.) 2940 */ 2941 env->regs[14] = env->sregs[SR_PC]; 2942 break; 2943 case EXCP_HW_EXCP: 2944 env->regs[17] = env->sregs[SR_PC] + 4; 2945 if (env->iflags & D_FLAG) { 2946 env->sregs[SR_ESR] |= 1 << 12; 2947 env->sregs[SR_PC] -= 4; 2948 /* FIXME: if branch was immed, replay the imm as well. */ 2949 } 2950 2951 env->iflags &= ~(IMM_FLAG | D_FLAG); 2952 2953 switch (env->sregs[SR_ESR] & 31) { 2954 case ESR_EC_DIVZERO: 2955 info.si_signo = TARGET_SIGFPE; 2956 info.si_errno = 0; 2957 info.si_code = TARGET_FPE_FLTDIV; 2958 info._sifields._sigfault._addr = 0; 2959 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2960 break; 2961 case ESR_EC_FPU: 2962 info.si_signo = TARGET_SIGFPE; 2963 info.si_errno = 0; 2964 if (env->sregs[SR_FSR] & FSR_IO) { 2965 info.si_code = TARGET_FPE_FLTINV; 2966 } 2967 if (env->sregs[SR_FSR] & FSR_DZ) { 2968 info.si_code = TARGET_FPE_FLTDIV; 2969 } 2970 info._sifields._sigfault._addr = 0; 2971 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2972 break; 2973 default: 2974 printf ("Unhandled hw-exception: 0x%x\n", 2975 env->sregs[SR_ESR] & ESR_EC_MASK); 2976 cpu_dump_state(cs, stderr, fprintf, 0); 2977 exit(EXIT_FAILURE); 2978 break; 2979 } 2980 break; 2981 case EXCP_DEBUG: 2982 { 2983 int sig; 2984 2985 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 2986 if (sig) 2987 { 2988 info.si_signo = sig; 2989 info.si_errno = 0; 2990 info.si_code = TARGET_TRAP_BRKPT; 2991 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 2992 } 2993 } 2994 break; 2995 default: 2996 printf ("Unhandled trap: 0x%x\n", trapnr); 2997 cpu_dump_state(cs, stderr, fprintf, 0); 2998 exit(EXIT_FAILURE); 2999 } 3000 process_pending_signals (env); 3001 } 3002 } 3003 #endif 3004 3005 #ifdef TARGET_M68K 3006 3007 void cpu_loop(CPUM68KState *env) 3008 { 3009 CPUState *cs = CPU(m68k_env_get_cpu(env)); 3010 int trapnr; 3011 unsigned int n; 3012 target_siginfo_t info; 3013 TaskState *ts = cs->opaque; 3014 3015 for(;;) { 3016 cpu_exec_start(cs); 3017 trapnr = cpu_exec(cs); 3018 cpu_exec_end(cs); 3019 process_queued_cpu_work(cs); 3020 3021 switch(trapnr) { 3022 case EXCP_ILLEGAL: 3023 { 3024 if (ts->sim_syscalls) { 3025 uint16_t nr; 3026 get_user_u16(nr, env->pc + 2); 3027 env->pc += 4; 3028 do_m68k_simcall(env, nr); 3029 } else { 3030 goto do_sigill; 3031 } 3032 } 3033 break; 3034 case EXCP_HALT_INSN: 3035 /* Semihosing syscall. */ 3036 env->pc += 4; 3037 do_m68k_semihosting(env, env->dregs[0]); 3038 break; 3039 case EXCP_LINEA: 3040 case EXCP_LINEF: 3041 case EXCP_UNSUPPORTED: 3042 do_sigill: 3043 info.si_signo = TARGET_SIGILL; 3044 info.si_errno = 0; 3045 info.si_code = TARGET_ILL_ILLOPN; 3046 info._sifields._sigfault._addr = env->pc; 3047 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3048 break; 3049 case EXCP_TRAP0: 3050 { 3051 abi_long ret; 3052 ts->sim_syscalls = 0; 3053 n = env->dregs[0]; 3054 env->pc += 2; 3055 ret = do_syscall(env, 3056 n, 3057 env->dregs[1], 3058 env->dregs[2], 3059 env->dregs[3], 3060 env->dregs[4], 3061 env->dregs[5], 3062 env->aregs[0], 3063 0, 0); 3064 if (ret == -TARGET_ERESTARTSYS) { 3065 env->pc -= 2; 3066 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3067 env->dregs[0] = ret; 3068 } 3069 } 3070 break; 3071 case EXCP_INTERRUPT: 3072 /* just indicate that signals should be handled asap */ 3073 break; 3074 case EXCP_ACCESS: 3075 { 3076 info.si_signo = TARGET_SIGSEGV; 3077 info.si_errno = 0; 3078 /* XXX: check env->error_code */ 3079 info.si_code = TARGET_SEGV_MAPERR; 3080 info._sifields._sigfault._addr = env->mmu.ar; 3081 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3082 } 3083 break; 3084 case EXCP_DEBUG: 3085 { 3086 int sig; 3087 3088 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3089 if (sig) 3090 { 3091 info.si_signo = sig; 3092 info.si_errno = 0; 3093 info.si_code = TARGET_TRAP_BRKPT; 3094 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3095 } 3096 } 3097 break; 3098 default: 3099 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 3100 abort(); 3101 } 3102 process_pending_signals(env); 3103 } 3104 } 3105 #endif /* TARGET_M68K */ 3106 3107 #ifdef TARGET_ALPHA 3108 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) 3109 { 3110 target_ulong addr, val, tmp; 3111 target_siginfo_t info; 3112 int ret = 0; 3113 3114 addr = env->lock_addr; 3115 tmp = env->lock_st_addr; 3116 env->lock_addr = -1; 3117 env->lock_st_addr = 0; 3118 3119 start_exclusive(); 3120 mmap_lock(); 3121 3122 if (addr == tmp) { 3123 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3124 goto do_sigsegv; 3125 } 3126 3127 if (val == env->lock_value) { 3128 tmp = env->ir[reg]; 3129 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { 3130 goto do_sigsegv; 3131 } 3132 ret = 1; 3133 } 3134 } 3135 env->ir[reg] = ret; 3136 env->pc += 4; 3137 3138 mmap_unlock(); 3139 end_exclusive(); 3140 return; 3141 3142 do_sigsegv: 3143 mmap_unlock(); 3144 end_exclusive(); 3145 3146 info.si_signo = TARGET_SIGSEGV; 3147 info.si_errno = 0; 3148 info.si_code = TARGET_SEGV_MAPERR; 3149 info._sifields._sigfault._addr = addr; 3150 queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info); 3151 } 3152 3153 void cpu_loop(CPUAlphaState *env) 3154 { 3155 CPUState *cs = CPU(alpha_env_get_cpu(env)); 3156 int trapnr; 3157 target_siginfo_t info; 3158 abi_long sysret; 3159 3160 while (1) { 3161 cpu_exec_start(cs); 3162 trapnr = cpu_exec(cs); 3163 cpu_exec_end(cs); 3164 process_queued_cpu_work(cs); 3165 3166 /* All of the traps imply a transition through PALcode, which 3167 implies an REI instruction has been executed. Which means 3168 that the intr_flag should be cleared. */ 3169 env->intr_flag = 0; 3170 3171 switch (trapnr) { 3172 case EXCP_RESET: 3173 fprintf(stderr, "Reset requested. Exit\n"); 3174 exit(EXIT_FAILURE); 3175 break; 3176 case EXCP_MCHK: 3177 fprintf(stderr, "Machine check exception. Exit\n"); 3178 exit(EXIT_FAILURE); 3179 break; 3180 case EXCP_SMP_INTERRUPT: 3181 case EXCP_CLK_INTERRUPT: 3182 case EXCP_DEV_INTERRUPT: 3183 fprintf(stderr, "External interrupt. Exit\n"); 3184 exit(EXIT_FAILURE); 3185 break; 3186 case EXCP_MMFAULT: 3187 env->lock_addr = -1; 3188 info.si_signo = TARGET_SIGSEGV; 3189 info.si_errno = 0; 3190 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID 3191 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); 3192 info._sifields._sigfault._addr = env->trap_arg0; 3193 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3194 break; 3195 case EXCP_UNALIGN: 3196 env->lock_addr = -1; 3197 info.si_signo = TARGET_SIGBUS; 3198 info.si_errno = 0; 3199 info.si_code = TARGET_BUS_ADRALN; 3200 info._sifields._sigfault._addr = env->trap_arg0; 3201 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3202 break; 3203 case EXCP_OPCDEC: 3204 do_sigill: 3205 env->lock_addr = -1; 3206 info.si_signo = TARGET_SIGILL; 3207 info.si_errno = 0; 3208 info.si_code = TARGET_ILL_ILLOPC; 3209 info._sifields._sigfault._addr = env->pc; 3210 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3211 break; 3212 case EXCP_ARITH: 3213 env->lock_addr = -1; 3214 info.si_signo = TARGET_SIGFPE; 3215 info.si_errno = 0; 3216 info.si_code = TARGET_FPE_FLTINV; 3217 info._sifields._sigfault._addr = env->pc; 3218 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3219 break; 3220 case EXCP_FEN: 3221 /* No-op. Linux simply re-enables the FPU. */ 3222 break; 3223 case EXCP_CALL_PAL: 3224 env->lock_addr = -1; 3225 switch (env->error_code) { 3226 case 0x80: 3227 /* BPT */ 3228 info.si_signo = TARGET_SIGTRAP; 3229 info.si_errno = 0; 3230 info.si_code = TARGET_TRAP_BRKPT; 3231 info._sifields._sigfault._addr = env->pc; 3232 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3233 break; 3234 case 0x81: 3235 /* BUGCHK */ 3236 info.si_signo = TARGET_SIGTRAP; 3237 info.si_errno = 0; 3238 info.si_code = 0; 3239 info._sifields._sigfault._addr = env->pc; 3240 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3241 break; 3242 case 0x83: 3243 /* CALLSYS */ 3244 trapnr = env->ir[IR_V0]; 3245 sysret = do_syscall(env, trapnr, 3246 env->ir[IR_A0], env->ir[IR_A1], 3247 env->ir[IR_A2], env->ir[IR_A3], 3248 env->ir[IR_A4], env->ir[IR_A5], 3249 0, 0); 3250 if (sysret == -TARGET_ERESTARTSYS) { 3251 env->pc -= 4; 3252 break; 3253 } 3254 if (sysret == -TARGET_QEMU_ESIGRETURN) { 3255 break; 3256 } 3257 /* Syscall writes 0 to V0 to bypass error check, similar 3258 to how this is handled internal to Linux kernel. 3259 (Ab)use trapnr temporarily as boolean indicating error. */ 3260 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); 3261 env->ir[IR_V0] = (trapnr ? -sysret : sysret); 3262 env->ir[IR_A3] = trapnr; 3263 break; 3264 case 0x86: 3265 /* IMB */ 3266 /* ??? We can probably elide the code using page_unprotect 3267 that is checking for self-modifying code. Instead we 3268 could simply call tb_flush here. Until we work out the 3269 changes required to turn off the extra write protection, 3270 this can be a no-op. */ 3271 break; 3272 case 0x9E: 3273 /* RDUNIQUE */ 3274 /* Handled in the translator for usermode. */ 3275 abort(); 3276 case 0x9F: 3277 /* WRUNIQUE */ 3278 /* Handled in the translator for usermode. */ 3279 abort(); 3280 case 0xAA: 3281 /* GENTRAP */ 3282 info.si_signo = TARGET_SIGFPE; 3283 switch (env->ir[IR_A0]) { 3284 case TARGET_GEN_INTOVF: 3285 info.si_code = TARGET_FPE_INTOVF; 3286 break; 3287 case TARGET_GEN_INTDIV: 3288 info.si_code = TARGET_FPE_INTDIV; 3289 break; 3290 case TARGET_GEN_FLTOVF: 3291 info.si_code = TARGET_FPE_FLTOVF; 3292 break; 3293 case TARGET_GEN_FLTUND: 3294 info.si_code = TARGET_FPE_FLTUND; 3295 break; 3296 case TARGET_GEN_FLTINV: 3297 info.si_code = TARGET_FPE_FLTINV; 3298 break; 3299 case TARGET_GEN_FLTINE: 3300 info.si_code = TARGET_FPE_FLTRES; 3301 break; 3302 case TARGET_GEN_ROPRAND: 3303 info.si_code = 0; 3304 break; 3305 default: 3306 info.si_signo = TARGET_SIGTRAP; 3307 info.si_code = 0; 3308 break; 3309 } 3310 info.si_errno = 0; 3311 info._sifields._sigfault._addr = env->pc; 3312 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3313 break; 3314 default: 3315 goto do_sigill; 3316 } 3317 break; 3318 case EXCP_DEBUG: 3319 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); 3320 if (info.si_signo) { 3321 env->lock_addr = -1; 3322 info.si_errno = 0; 3323 info.si_code = TARGET_TRAP_BRKPT; 3324 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3325 } 3326 break; 3327 case EXCP_STL_C: 3328 case EXCP_STQ_C: 3329 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); 3330 break; 3331 case EXCP_INTERRUPT: 3332 /* Just indicate that signals should be handled asap. */ 3333 break; 3334 default: 3335 printf ("Unhandled trap: 0x%x\n", trapnr); 3336 cpu_dump_state(cs, stderr, fprintf, 0); 3337 exit(EXIT_FAILURE); 3338 } 3339 process_pending_signals (env); 3340 } 3341 } 3342 #endif /* TARGET_ALPHA */ 3343 3344 #ifdef TARGET_S390X 3345 void cpu_loop(CPUS390XState *env) 3346 { 3347 CPUState *cs = CPU(s390_env_get_cpu(env)); 3348 int trapnr, n, sig; 3349 target_siginfo_t info; 3350 target_ulong addr; 3351 abi_long ret; 3352 3353 while (1) { 3354 cpu_exec_start(cs); 3355 trapnr = cpu_exec(cs); 3356 cpu_exec_end(cs); 3357 process_queued_cpu_work(cs); 3358 3359 switch (trapnr) { 3360 case EXCP_INTERRUPT: 3361 /* Just indicate that signals should be handled asap. */ 3362 break; 3363 3364 case EXCP_SVC: 3365 n = env->int_svc_code; 3366 if (!n) { 3367 /* syscalls > 255 */ 3368 n = env->regs[1]; 3369 } 3370 env->psw.addr += env->int_svc_ilen; 3371 ret = do_syscall(env, n, env->regs[2], env->regs[3], 3372 env->regs[4], env->regs[5], 3373 env->regs[6], env->regs[7], 0, 0); 3374 if (ret == -TARGET_ERESTARTSYS) { 3375 env->psw.addr -= env->int_svc_ilen; 3376 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3377 env->regs[2] = ret; 3378 } 3379 break; 3380 3381 case EXCP_DEBUG: 3382 sig = gdb_handlesig(cs, TARGET_SIGTRAP); 3383 if (sig) { 3384 n = TARGET_TRAP_BRKPT; 3385 goto do_signal_pc; 3386 } 3387 break; 3388 case EXCP_PGM: 3389 n = env->int_pgm_code; 3390 switch (n) { 3391 case PGM_OPERATION: 3392 case PGM_PRIVILEGED: 3393 sig = TARGET_SIGILL; 3394 n = TARGET_ILL_ILLOPC; 3395 goto do_signal_pc; 3396 case PGM_PROTECTION: 3397 case PGM_ADDRESSING: 3398 sig = TARGET_SIGSEGV; 3399 /* XXX: check env->error_code */ 3400 n = TARGET_SEGV_MAPERR; 3401 addr = env->__excp_addr; 3402 goto do_signal; 3403 case PGM_EXECUTE: 3404 case PGM_SPECIFICATION: 3405 case PGM_SPECIAL_OP: 3406 case PGM_OPERAND: 3407 do_sigill_opn: 3408 sig = TARGET_SIGILL; 3409 n = TARGET_ILL_ILLOPN; 3410 goto do_signal_pc; 3411 3412 case PGM_FIXPT_OVERFLOW: 3413 sig = TARGET_SIGFPE; 3414 n = TARGET_FPE_INTOVF; 3415 goto do_signal_pc; 3416 case PGM_FIXPT_DIVIDE: 3417 sig = TARGET_SIGFPE; 3418 n = TARGET_FPE_INTDIV; 3419 goto do_signal_pc; 3420 3421 case PGM_DATA: 3422 n = (env->fpc >> 8) & 0xff; 3423 if (n == 0xff) { 3424 /* compare-and-trap */ 3425 goto do_sigill_opn; 3426 } else { 3427 /* An IEEE exception, simulated or otherwise. */ 3428 if (n & 0x80) { 3429 n = TARGET_FPE_FLTINV; 3430 } else if (n & 0x40) { 3431 n = TARGET_FPE_FLTDIV; 3432 } else if (n & 0x20) { 3433 n = TARGET_FPE_FLTOVF; 3434 } else if (n & 0x10) { 3435 n = TARGET_FPE_FLTUND; 3436 } else if (n & 0x08) { 3437 n = TARGET_FPE_FLTRES; 3438 } else { 3439 /* ??? Quantum exception; BFP, DFP error. */ 3440 goto do_sigill_opn; 3441 } 3442 sig = TARGET_SIGFPE; 3443 goto do_signal_pc; 3444 } 3445 3446 default: 3447 fprintf(stderr, "Unhandled program exception: %#x\n", n); 3448 cpu_dump_state(cs, stderr, fprintf, 0); 3449 exit(EXIT_FAILURE); 3450 } 3451 break; 3452 3453 do_signal_pc: 3454 addr = env->psw.addr; 3455 do_signal: 3456 info.si_signo = sig; 3457 info.si_errno = 0; 3458 info.si_code = n; 3459 info._sifields._sigfault._addr = addr; 3460 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3461 break; 3462 3463 default: 3464 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); 3465 cpu_dump_state(cs, stderr, fprintf, 0); 3466 exit(EXIT_FAILURE); 3467 } 3468 process_pending_signals (env); 3469 } 3470 } 3471 3472 #endif /* TARGET_S390X */ 3473 3474 #ifdef TARGET_TILEGX 3475 3476 static void gen_sigill_reg(CPUTLGState *env) 3477 { 3478 target_siginfo_t info; 3479 3480 info.si_signo = TARGET_SIGILL; 3481 info.si_errno = 0; 3482 info.si_code = TARGET_ILL_PRVREG; 3483 info._sifields._sigfault._addr = env->pc; 3484 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3485 } 3486 3487 static void do_signal(CPUTLGState *env, int signo, int sigcode) 3488 { 3489 target_siginfo_t info; 3490 3491 info.si_signo = signo; 3492 info.si_errno = 0; 3493 info._sifields._sigfault._addr = env->pc; 3494 3495 if (signo == TARGET_SIGSEGV) { 3496 /* The passed in sigcode is a dummy; check for a page mapping 3497 and pass either MAPERR or ACCERR. */ 3498 target_ulong addr = env->excaddr; 3499 info._sifields._sigfault._addr = addr; 3500 if (page_check_range(addr, 1, PAGE_VALID) < 0) { 3501 sigcode = TARGET_SEGV_MAPERR; 3502 } else { 3503 sigcode = TARGET_SEGV_ACCERR; 3504 } 3505 } 3506 info.si_code = sigcode; 3507 3508 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 3509 } 3510 3511 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) 3512 { 3513 env->excaddr = addr; 3514 do_signal(env, TARGET_SIGSEGV, 0); 3515 } 3516 3517 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) 3518 { 3519 if (unlikely(reg >= TILEGX_R_COUNT)) { 3520 switch (reg) { 3521 case TILEGX_R_SN: 3522 case TILEGX_R_ZERO: 3523 return; 3524 case TILEGX_R_IDN0: 3525 case TILEGX_R_IDN1: 3526 case TILEGX_R_UDN0: 3527 case TILEGX_R_UDN1: 3528 case TILEGX_R_UDN2: 3529 case TILEGX_R_UDN3: 3530 gen_sigill_reg(env); 3531 return; 3532 default: 3533 g_assert_not_reached(); 3534 } 3535 } 3536 env->regs[reg] = val; 3537 } 3538 3539 /* 3540 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in 3541 * memory at the address held in the first source register. If the values are 3542 * not equal, then no memory operation is performed. If the values are equal, 3543 * the 8-byte quantity from the second source register is written into memory 3544 * at the address held in the first source register. In either case, the result 3545 * of the instruction is the value read from memory. The compare and write to 3546 * memory are atomic and thus can be used for synchronization purposes. This 3547 * instruction only operates for addresses aligned to a 8-byte boundary. 3548 * Unaligned memory access causes an Unaligned Data Reference interrupt. 3549 * 3550 * Functional Description (64-bit) 3551 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); 3552 * rf[Dest] = memVal; 3553 * if (memVal == SPR[CmpValueSPR]) 3554 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); 3555 * 3556 * Functional Description (32-bit) 3557 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); 3558 * rf[Dest] = memVal; 3559 * if (memVal == signExtend32 (SPR[CmpValueSPR])) 3560 * memoryWriteWord (rf[SrcA], rf[SrcB]); 3561 * 3562 * 3563 * This function also processes exch and exch4 which need not process SPR. 3564 */ 3565 static void do_exch(CPUTLGState *env, bool quad, bool cmp) 3566 { 3567 target_ulong addr; 3568 target_long val, sprval; 3569 3570 start_exclusive(); 3571 3572 addr = env->atomic_srca; 3573 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3574 goto sigsegv_maperr; 3575 } 3576 3577 if (cmp) { 3578 if (quad) { 3579 sprval = env->spregs[TILEGX_SPR_CMPEXCH]; 3580 } else { 3581 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); 3582 } 3583 } 3584 3585 if (!cmp || val == sprval) { 3586 target_long valb = env->atomic_srcb; 3587 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3588 goto sigsegv_maperr; 3589 } 3590 } 3591 3592 set_regval(env, env->atomic_dstr, val); 3593 end_exclusive(); 3594 return; 3595 3596 sigsegv_maperr: 3597 end_exclusive(); 3598 gen_sigsegv_maperr(env, addr); 3599 } 3600 3601 static void do_fetch(CPUTLGState *env, int trapnr, bool quad) 3602 { 3603 int8_t write = 1; 3604 target_ulong addr; 3605 target_long val, valb; 3606 3607 start_exclusive(); 3608 3609 addr = env->atomic_srca; 3610 valb = env->atomic_srcb; 3611 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { 3612 goto sigsegv_maperr; 3613 } 3614 3615 switch (trapnr) { 3616 case TILEGX_EXCP_OPCODE_FETCHADD: 3617 case TILEGX_EXCP_OPCODE_FETCHADD4: 3618 valb += val; 3619 break; 3620 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3621 valb += val; 3622 if (valb < 0) { 3623 write = 0; 3624 } 3625 break; 3626 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3627 valb += val; 3628 if ((int32_t)valb < 0) { 3629 write = 0; 3630 } 3631 break; 3632 case TILEGX_EXCP_OPCODE_FETCHAND: 3633 case TILEGX_EXCP_OPCODE_FETCHAND4: 3634 valb &= val; 3635 break; 3636 case TILEGX_EXCP_OPCODE_FETCHOR: 3637 case TILEGX_EXCP_OPCODE_FETCHOR4: 3638 valb |= val; 3639 break; 3640 default: 3641 g_assert_not_reached(); 3642 } 3643 3644 if (write) { 3645 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { 3646 goto sigsegv_maperr; 3647 } 3648 } 3649 3650 set_regval(env, env->atomic_dstr, val); 3651 end_exclusive(); 3652 return; 3653 3654 sigsegv_maperr: 3655 end_exclusive(); 3656 gen_sigsegv_maperr(env, addr); 3657 } 3658 3659 void cpu_loop(CPUTLGState *env) 3660 { 3661 CPUState *cs = CPU(tilegx_env_get_cpu(env)); 3662 int trapnr; 3663 3664 while (1) { 3665 cpu_exec_start(cs); 3666 trapnr = cpu_exec(cs); 3667 cpu_exec_end(cs); 3668 process_queued_cpu_work(cs); 3669 3670 switch (trapnr) { 3671 case TILEGX_EXCP_SYSCALL: 3672 { 3673 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR], 3674 env->regs[0], env->regs[1], 3675 env->regs[2], env->regs[3], 3676 env->regs[4], env->regs[5], 3677 env->regs[6], env->regs[7]); 3678 if (ret == -TARGET_ERESTARTSYS) { 3679 env->pc -= 8; 3680 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 3681 env->regs[TILEGX_R_RE] = ret; 3682 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0; 3683 } 3684 break; 3685 } 3686 case TILEGX_EXCP_OPCODE_EXCH: 3687 do_exch(env, true, false); 3688 break; 3689 case TILEGX_EXCP_OPCODE_EXCH4: 3690 do_exch(env, false, false); 3691 break; 3692 case TILEGX_EXCP_OPCODE_CMPEXCH: 3693 do_exch(env, true, true); 3694 break; 3695 case TILEGX_EXCP_OPCODE_CMPEXCH4: 3696 do_exch(env, false, true); 3697 break; 3698 case TILEGX_EXCP_OPCODE_FETCHADD: 3699 case TILEGX_EXCP_OPCODE_FETCHADDGEZ: 3700 case TILEGX_EXCP_OPCODE_FETCHAND: 3701 case TILEGX_EXCP_OPCODE_FETCHOR: 3702 do_fetch(env, trapnr, true); 3703 break; 3704 case TILEGX_EXCP_OPCODE_FETCHADD4: 3705 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: 3706 case TILEGX_EXCP_OPCODE_FETCHAND4: 3707 case TILEGX_EXCP_OPCODE_FETCHOR4: 3708 do_fetch(env, trapnr, false); 3709 break; 3710 case TILEGX_EXCP_SIGNAL: 3711 do_signal(env, env->signo, env->sigcode); 3712 break; 3713 case TILEGX_EXCP_REG_IDN_ACCESS: 3714 case TILEGX_EXCP_REG_UDN_ACCESS: 3715 gen_sigill_reg(env); 3716 break; 3717 default: 3718 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); 3719 g_assert_not_reached(); 3720 } 3721 process_pending_signals(env); 3722 } 3723 } 3724 3725 #endif 3726 3727 THREAD CPUState *thread_cpu; 3728 3729 bool qemu_cpu_is_self(CPUState *cpu) 3730 { 3731 return thread_cpu == cpu; 3732 } 3733 3734 void qemu_cpu_kick(CPUState *cpu) 3735 { 3736 cpu_exit(cpu); 3737 } 3738 3739 void task_settid(TaskState *ts) 3740 { 3741 if (ts->ts_tid == 0) { 3742 ts->ts_tid = (pid_t)syscall(SYS_gettid); 3743 } 3744 } 3745 3746 void stop_all_tasks(void) 3747 { 3748 /* 3749 * We trust that when using NPTL, start_exclusive() 3750 * handles thread stopping correctly. 3751 */ 3752 start_exclusive(); 3753 } 3754 3755 /* Assumes contents are already zeroed. */ 3756 void init_task_state(TaskState *ts) 3757 { 3758 ts->used = 1; 3759 } 3760 3761 CPUArchState *cpu_copy(CPUArchState *env) 3762 { 3763 CPUState *cpu = ENV_GET_CPU(env); 3764 CPUState *new_cpu = cpu_init(cpu_model); 3765 CPUArchState *new_env = new_cpu->env_ptr; 3766 CPUBreakpoint *bp; 3767 CPUWatchpoint *wp; 3768 3769 /* Reset non arch specific state */ 3770 cpu_reset(new_cpu); 3771 3772 memcpy(new_env, env, sizeof(CPUArchState)); 3773 3774 /* Clone all break/watchpoints. 3775 Note: Once we support ptrace with hw-debug register access, make sure 3776 BP_CPU break/watchpoints are handled correctly on clone. */ 3777 QTAILQ_INIT(&new_cpu->breakpoints); 3778 QTAILQ_INIT(&new_cpu->watchpoints); 3779 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 3780 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); 3781 } 3782 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { 3783 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); 3784 } 3785 3786 return new_env; 3787 } 3788 3789 static void handle_arg_help(const char *arg) 3790 { 3791 usage(EXIT_SUCCESS); 3792 } 3793 3794 static void handle_arg_log(const char *arg) 3795 { 3796 int mask; 3797 3798 mask = qemu_str_to_log_mask(arg); 3799 if (!mask) { 3800 qemu_print_log_usage(stdout); 3801 exit(EXIT_FAILURE); 3802 } 3803 qemu_log_needs_buffers(); 3804 qemu_set_log(mask); 3805 } 3806 3807 static void handle_arg_log_filename(const char *arg) 3808 { 3809 qemu_set_log_filename(arg, &error_fatal); 3810 } 3811 3812 static void handle_arg_set_env(const char *arg) 3813 { 3814 char *r, *p, *token; 3815 r = p = strdup(arg); 3816 while ((token = strsep(&p, ",")) != NULL) { 3817 if (envlist_setenv(envlist, token) != 0) { 3818 usage(EXIT_FAILURE); 3819 } 3820 } 3821 free(r); 3822 } 3823 3824 static void handle_arg_unset_env(const char *arg) 3825 { 3826 char *r, *p, *token; 3827 r = p = strdup(arg); 3828 while ((token = strsep(&p, ",")) != NULL) { 3829 if (envlist_unsetenv(envlist, token) != 0) { 3830 usage(EXIT_FAILURE); 3831 } 3832 } 3833 free(r); 3834 } 3835 3836 static void handle_arg_argv0(const char *arg) 3837 { 3838 argv0 = strdup(arg); 3839 } 3840 3841 static void handle_arg_stack_size(const char *arg) 3842 { 3843 char *p; 3844 guest_stack_size = strtoul(arg, &p, 0); 3845 if (guest_stack_size == 0) { 3846 usage(EXIT_FAILURE); 3847 } 3848 3849 if (*p == 'M') { 3850 guest_stack_size *= 1024 * 1024; 3851 } else if (*p == 'k' || *p == 'K') { 3852 guest_stack_size *= 1024; 3853 } 3854 } 3855 3856 static void handle_arg_ld_prefix(const char *arg) 3857 { 3858 interp_prefix = strdup(arg); 3859 } 3860 3861 static void handle_arg_pagesize(const char *arg) 3862 { 3863 qemu_host_page_size = atoi(arg); 3864 if (qemu_host_page_size == 0 || 3865 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { 3866 fprintf(stderr, "page size must be a power of two\n"); 3867 exit(EXIT_FAILURE); 3868 } 3869 } 3870 3871 static void handle_arg_randseed(const char *arg) 3872 { 3873 unsigned long long seed; 3874 3875 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) { 3876 fprintf(stderr, "Invalid seed number: %s\n", arg); 3877 exit(EXIT_FAILURE); 3878 } 3879 srand(seed); 3880 } 3881 3882 static void handle_arg_gdb(const char *arg) 3883 { 3884 gdbstub_port = atoi(arg); 3885 } 3886 3887 static void handle_arg_uname(const char *arg) 3888 { 3889 qemu_uname_release = strdup(arg); 3890 } 3891 3892 static void handle_arg_cpu(const char *arg) 3893 { 3894 cpu_model = strdup(arg); 3895 if (cpu_model == NULL || is_help_option(cpu_model)) { 3896 /* XXX: implement xxx_cpu_list for targets that still miss it */ 3897 #if defined(cpu_list) 3898 cpu_list(stdout, &fprintf); 3899 #endif 3900 exit(EXIT_FAILURE); 3901 } 3902 } 3903 3904 static void handle_arg_guest_base(const char *arg) 3905 { 3906 guest_base = strtol(arg, NULL, 0); 3907 have_guest_base = 1; 3908 } 3909 3910 static void handle_arg_reserved_va(const char *arg) 3911 { 3912 char *p; 3913 int shift = 0; 3914 reserved_va = strtoul(arg, &p, 0); 3915 switch (*p) { 3916 case 'k': 3917 case 'K': 3918 shift = 10; 3919 break; 3920 case 'M': 3921 shift = 20; 3922 break; 3923 case 'G': 3924 shift = 30; 3925 break; 3926 } 3927 if (shift) { 3928 unsigned long unshifted = reserved_va; 3929 p++; 3930 reserved_va <<= shift; 3931 if (((reserved_va >> shift) != unshifted) 3932 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS 3933 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) 3934 #endif 3935 ) { 3936 fprintf(stderr, "Reserved virtual address too big\n"); 3937 exit(EXIT_FAILURE); 3938 } 3939 } 3940 if (*p) { 3941 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); 3942 exit(EXIT_FAILURE); 3943 } 3944 } 3945 3946 static void handle_arg_singlestep(const char *arg) 3947 { 3948 singlestep = 1; 3949 } 3950 3951 static void handle_arg_strace(const char *arg) 3952 { 3953 do_strace = 1; 3954 } 3955 3956 static void handle_arg_version(const char *arg) 3957 { 3958 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION 3959 "\n" QEMU_COPYRIGHT "\n"); 3960 exit(EXIT_SUCCESS); 3961 } 3962 3963 static char *trace_file; 3964 static void handle_arg_trace(const char *arg) 3965 { 3966 g_free(trace_file); 3967 trace_file = trace_opt_parse(arg); 3968 } 3969 3970 struct qemu_argument { 3971 const char *argv; 3972 const char *env; 3973 bool has_arg; 3974 void (*handle_opt)(const char *arg); 3975 const char *example; 3976 const char *help; 3977 }; 3978 3979 static const struct qemu_argument arg_table[] = { 3980 {"h", "", false, handle_arg_help, 3981 "", "print this help"}, 3982 {"help", "", false, handle_arg_help, 3983 "", ""}, 3984 {"g", "QEMU_GDB", true, handle_arg_gdb, 3985 "port", "wait gdb connection to 'port'"}, 3986 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, 3987 "path", "set the elf interpreter prefix to 'path'"}, 3988 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, 3989 "size", "set the stack size to 'size' bytes"}, 3990 {"cpu", "QEMU_CPU", true, handle_arg_cpu, 3991 "model", "select CPU (-cpu help for list)"}, 3992 {"E", "QEMU_SET_ENV", true, handle_arg_set_env, 3993 "var=value", "sets targets environment variable (see below)"}, 3994 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, 3995 "var", "unsets targets environment variable (see below)"}, 3996 {"0", "QEMU_ARGV0", true, handle_arg_argv0, 3997 "argv0", "forces target process argv[0] to be 'argv0'"}, 3998 {"r", "QEMU_UNAME", true, handle_arg_uname, 3999 "uname", "set qemu uname release string to 'uname'"}, 4000 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, 4001 "address", "set guest_base address to 'address'"}, 4002 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, 4003 "size", "reserve 'size' bytes for guest virtual address space"}, 4004 {"d", "QEMU_LOG", true, handle_arg_log, 4005 "item[,...]", "enable logging of specified items " 4006 "(use '-d help' for a list of items)"}, 4007 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, 4008 "logfile", "write logs to 'logfile' (default stderr)"}, 4009 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, 4010 "pagesize", "set the host page size to 'pagesize'"}, 4011 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, 4012 "", "run in singlestep mode"}, 4013 {"strace", "QEMU_STRACE", false, handle_arg_strace, 4014 "", "log system calls"}, 4015 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed, 4016 "", "Seed for pseudo-random number generator"}, 4017 {"trace", "QEMU_TRACE", true, handle_arg_trace, 4018 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"}, 4019 {"version", "QEMU_VERSION", false, handle_arg_version, 4020 "", "display version information and exit"}, 4021 {NULL, NULL, false, NULL, NULL, NULL} 4022 }; 4023 4024 static void usage(int exitcode) 4025 { 4026 const struct qemu_argument *arginfo; 4027 int maxarglen; 4028 int maxenvlen; 4029 4030 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" 4031 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" 4032 "\n" 4033 "Options and associated environment variables:\n" 4034 "\n"); 4035 4036 /* Calculate column widths. We must always have at least enough space 4037 * for the column header. 4038 */ 4039 maxarglen = strlen("Argument"); 4040 maxenvlen = strlen("Env-variable"); 4041 4042 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4043 int arglen = strlen(arginfo->argv); 4044 if (arginfo->has_arg) { 4045 arglen += strlen(arginfo->example) + 1; 4046 } 4047 if (strlen(arginfo->env) > maxenvlen) { 4048 maxenvlen = strlen(arginfo->env); 4049 } 4050 if (arglen > maxarglen) { 4051 maxarglen = arglen; 4052 } 4053 } 4054 4055 printf("%-*s %-*s Description\n", maxarglen+1, "Argument", 4056 maxenvlen, "Env-variable"); 4057 4058 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4059 if (arginfo->has_arg) { 4060 printf("-%s %-*s %-*s %s\n", arginfo->argv, 4061 (int)(maxarglen - strlen(arginfo->argv) - 1), 4062 arginfo->example, maxenvlen, arginfo->env, arginfo->help); 4063 } else { 4064 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, 4065 maxenvlen, arginfo->env, 4066 arginfo->help); 4067 } 4068 } 4069 4070 printf("\n" 4071 "Defaults:\n" 4072 "QEMU_LD_PREFIX = %s\n" 4073 "QEMU_STACK_SIZE = %ld byte\n", 4074 interp_prefix, 4075 guest_stack_size); 4076 4077 printf("\n" 4078 "You can use -E and -U options or the QEMU_SET_ENV and\n" 4079 "QEMU_UNSET_ENV environment variables to set and unset\n" 4080 "environment variables for the target process.\n" 4081 "It is possible to provide several variables by separating them\n" 4082 "by commas in getsubopt(3) style. Additionally it is possible to\n" 4083 "provide the -E and -U options multiple times.\n" 4084 "The following lines are equivalent:\n" 4085 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" 4086 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" 4087 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" 4088 "Note that if you provide several changes to a single variable\n" 4089 "the last change will stay in effect.\n"); 4090 4091 exit(exitcode); 4092 } 4093 4094 static int parse_args(int argc, char **argv) 4095 { 4096 const char *r; 4097 int optind; 4098 const struct qemu_argument *arginfo; 4099 4100 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4101 if (arginfo->env == NULL) { 4102 continue; 4103 } 4104 4105 r = getenv(arginfo->env); 4106 if (r != NULL) { 4107 arginfo->handle_opt(r); 4108 } 4109 } 4110 4111 optind = 1; 4112 for (;;) { 4113 if (optind >= argc) { 4114 break; 4115 } 4116 r = argv[optind]; 4117 if (r[0] != '-') { 4118 break; 4119 } 4120 optind++; 4121 r++; 4122 if (!strcmp(r, "-")) { 4123 break; 4124 } 4125 /* Treat --foo the same as -foo. */ 4126 if (r[0] == '-') { 4127 r++; 4128 } 4129 4130 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { 4131 if (!strcmp(r, arginfo->argv)) { 4132 if (arginfo->has_arg) { 4133 if (optind >= argc) { 4134 (void) fprintf(stderr, 4135 "qemu: missing argument for option '%s'\n", r); 4136 exit(EXIT_FAILURE); 4137 } 4138 arginfo->handle_opt(argv[optind]); 4139 optind++; 4140 } else { 4141 arginfo->handle_opt(NULL); 4142 } 4143 break; 4144 } 4145 } 4146 4147 /* no option matched the current argv */ 4148 if (arginfo->handle_opt == NULL) { 4149 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r); 4150 exit(EXIT_FAILURE); 4151 } 4152 } 4153 4154 if (optind >= argc) { 4155 (void) fprintf(stderr, "qemu: no user program specified\n"); 4156 exit(EXIT_FAILURE); 4157 } 4158 4159 filename = argv[optind]; 4160 exec_path = argv[optind]; 4161 4162 return optind; 4163 } 4164 4165 int main(int argc, char **argv, char **envp) 4166 { 4167 struct target_pt_regs regs1, *regs = ®s1; 4168 struct image_info info1, *info = &info1; 4169 struct linux_binprm bprm; 4170 TaskState *ts; 4171 CPUArchState *env; 4172 CPUState *cpu; 4173 int optind; 4174 char **target_environ, **wrk; 4175 char **target_argv; 4176 int target_argc; 4177 int i; 4178 int ret; 4179 int execfd; 4180 4181 module_call_init(MODULE_INIT_TRACE); 4182 qemu_init_cpu_list(); 4183 module_call_init(MODULE_INIT_QOM); 4184 4185 if ((envlist = envlist_create()) == NULL) { 4186 (void) fprintf(stderr, "Unable to allocate envlist\n"); 4187 exit(EXIT_FAILURE); 4188 } 4189 4190 /* add current environment into the list */ 4191 for (wrk = environ; *wrk != NULL; wrk++) { 4192 (void) envlist_setenv(envlist, *wrk); 4193 } 4194 4195 /* Read the stack limit from the kernel. If it's "unlimited", 4196 then we can do little else besides use the default. */ 4197 { 4198 struct rlimit lim; 4199 if (getrlimit(RLIMIT_STACK, &lim) == 0 4200 && lim.rlim_cur != RLIM_INFINITY 4201 && lim.rlim_cur == (target_long)lim.rlim_cur) { 4202 guest_stack_size = lim.rlim_cur; 4203 } 4204 } 4205 4206 cpu_model = NULL; 4207 4208 srand(time(NULL)); 4209 4210 qemu_add_opts(&qemu_trace_opts); 4211 4212 optind = parse_args(argc, argv); 4213 4214 if (!trace_init_backends()) { 4215 exit(1); 4216 } 4217 trace_init_file(trace_file); 4218 4219 /* Zero out regs */ 4220 memset(regs, 0, sizeof(struct target_pt_regs)); 4221 4222 /* Zero out image_info */ 4223 memset(info, 0, sizeof(struct image_info)); 4224 4225 memset(&bprm, 0, sizeof (bprm)); 4226 4227 /* Scan interp_prefix dir for replacement files. */ 4228 init_paths(interp_prefix); 4229 4230 init_qemu_uname_release(); 4231 4232 if (cpu_model == NULL) { 4233 #if defined(TARGET_I386) 4234 #ifdef TARGET_X86_64 4235 cpu_model = "qemu64"; 4236 #else 4237 cpu_model = "qemu32"; 4238 #endif 4239 #elif defined(TARGET_ARM) 4240 cpu_model = "any"; 4241 #elif defined(TARGET_UNICORE32) 4242 cpu_model = "any"; 4243 #elif defined(TARGET_M68K) 4244 cpu_model = "any"; 4245 #elif defined(TARGET_SPARC) 4246 #ifdef TARGET_SPARC64 4247 cpu_model = "TI UltraSparc II"; 4248 #else 4249 cpu_model = "Fujitsu MB86904"; 4250 #endif 4251 #elif defined(TARGET_MIPS) 4252 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) 4253 cpu_model = "5KEf"; 4254 #else 4255 cpu_model = "24Kf"; 4256 #endif 4257 #elif defined TARGET_OPENRISC 4258 cpu_model = "or1200"; 4259 #elif defined(TARGET_PPC) 4260 # ifdef TARGET_PPC64 4261 cpu_model = "POWER8"; 4262 # else 4263 cpu_model = "750"; 4264 # endif 4265 #elif defined TARGET_SH4 4266 cpu_model = TYPE_SH7785_CPU; 4267 #else 4268 cpu_model = "any"; 4269 #endif 4270 } 4271 tcg_exec_init(0); 4272 /* NOTE: we need to init the CPU at this stage to get 4273 qemu_host_page_size */ 4274 cpu = cpu_init(cpu_model); 4275 if (!cpu) { 4276 fprintf(stderr, "Unable to find CPU definition\n"); 4277 exit(EXIT_FAILURE); 4278 } 4279 env = cpu->env_ptr; 4280 cpu_reset(cpu); 4281 4282 thread_cpu = cpu; 4283 4284 if (getenv("QEMU_STRACE")) { 4285 do_strace = 1; 4286 } 4287 4288 if (getenv("QEMU_RAND_SEED")) { 4289 handle_arg_randseed(getenv("QEMU_RAND_SEED")); 4290 } 4291 4292 target_environ = envlist_to_environ(envlist, NULL); 4293 envlist_free(envlist); 4294 4295 /* 4296 * Now that page sizes are configured in cpu_init() we can do 4297 * proper page alignment for guest_base. 4298 */ 4299 guest_base = HOST_PAGE_ALIGN(guest_base); 4300 4301 if (reserved_va || have_guest_base) { 4302 guest_base = init_guest_space(guest_base, reserved_va, 0, 4303 have_guest_base); 4304 if (guest_base == (unsigned long)-1) { 4305 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " 4306 "space for use as guest address space (check your virtual " 4307 "memory ulimit setting or reserve less using -R option)\n", 4308 reserved_va); 4309 exit(EXIT_FAILURE); 4310 } 4311 4312 if (reserved_va) { 4313 mmap_next_start = reserved_va; 4314 } 4315 } 4316 4317 /* 4318 * Read in mmap_min_addr kernel parameter. This value is used 4319 * When loading the ELF image to determine whether guest_base 4320 * is needed. It is also used in mmap_find_vma. 4321 */ 4322 { 4323 FILE *fp; 4324 4325 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { 4326 unsigned long tmp; 4327 if (fscanf(fp, "%lu", &tmp) == 1) { 4328 mmap_min_addr = tmp; 4329 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr); 4330 } 4331 fclose(fp); 4332 } 4333 } 4334 4335 /* 4336 * Prepare copy of argv vector for target. 4337 */ 4338 target_argc = argc - optind; 4339 target_argv = calloc(target_argc + 1, sizeof (char *)); 4340 if (target_argv == NULL) { 4341 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); 4342 exit(EXIT_FAILURE); 4343 } 4344 4345 /* 4346 * If argv0 is specified (using '-0' switch) we replace 4347 * argv[0] pointer with the given one. 4348 */ 4349 i = 0; 4350 if (argv0 != NULL) { 4351 target_argv[i++] = strdup(argv0); 4352 } 4353 for (; i < target_argc; i++) { 4354 target_argv[i] = strdup(argv[optind + i]); 4355 } 4356 target_argv[target_argc] = NULL; 4357 4358 ts = g_new0(TaskState, 1); 4359 init_task_state(ts); 4360 /* build Task State */ 4361 ts->info = info; 4362 ts->bprm = &bprm; 4363 cpu->opaque = ts; 4364 task_settid(ts); 4365 4366 execfd = qemu_getauxval(AT_EXECFD); 4367 if (execfd == 0) { 4368 execfd = open(filename, O_RDONLY); 4369 if (execfd < 0) { 4370 printf("Error while loading %s: %s\n", filename, strerror(errno)); 4371 _exit(EXIT_FAILURE); 4372 } 4373 } 4374 4375 ret = loader_exec(execfd, filename, target_argv, target_environ, regs, 4376 info, &bprm); 4377 if (ret != 0) { 4378 printf("Error while loading %s: %s\n", filename, strerror(-ret)); 4379 _exit(EXIT_FAILURE); 4380 } 4381 4382 for (wrk = target_environ; *wrk; wrk++) { 4383 free(*wrk); 4384 } 4385 4386 free(target_environ); 4387 4388 if (qemu_loglevel_mask(CPU_LOG_PAGE)) { 4389 qemu_log("guest_base 0x%lx\n", guest_base); 4390 log_page_dump(); 4391 4392 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); 4393 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); 4394 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", 4395 info->start_code); 4396 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", 4397 info->start_data); 4398 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); 4399 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", 4400 info->start_stack); 4401 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); 4402 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); 4403 } 4404 4405 target_set_brk(info->brk); 4406 syscall_init(); 4407 signal_init(); 4408 4409 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay 4410 generating the prologue until now so that the prologue can take 4411 the real value of GUEST_BASE into account. */ 4412 tcg_prologue_init(&tcg_ctx); 4413 4414 #if defined(TARGET_I386) 4415 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; 4416 env->hflags |= HF_PE_MASK | HF_CPL_MASK; 4417 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4418 env->cr[4] |= CR4_OSFXSR_MASK; 4419 env->hflags |= HF_OSFXSR_MASK; 4420 } 4421 #ifndef TARGET_ABI32 4422 /* enable 64 bit mode if possible */ 4423 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { 4424 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); 4425 exit(EXIT_FAILURE); 4426 } 4427 env->cr[4] |= CR4_PAE_MASK; 4428 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; 4429 env->hflags |= HF_LMA_MASK; 4430 #endif 4431 4432 /* flags setup : we activate the IRQs by default as in user mode */ 4433 env->eflags |= IF_MASK; 4434 4435 /* linux register setup */ 4436 #ifndef TARGET_ABI32 4437 env->regs[R_EAX] = regs->rax; 4438 env->regs[R_EBX] = regs->rbx; 4439 env->regs[R_ECX] = regs->rcx; 4440 env->regs[R_EDX] = regs->rdx; 4441 env->regs[R_ESI] = regs->rsi; 4442 env->regs[R_EDI] = regs->rdi; 4443 env->regs[R_EBP] = regs->rbp; 4444 env->regs[R_ESP] = regs->rsp; 4445 env->eip = regs->rip; 4446 #else 4447 env->regs[R_EAX] = regs->eax; 4448 env->regs[R_EBX] = regs->ebx; 4449 env->regs[R_ECX] = regs->ecx; 4450 env->regs[R_EDX] = regs->edx; 4451 env->regs[R_ESI] = regs->esi; 4452 env->regs[R_EDI] = regs->edi; 4453 env->regs[R_EBP] = regs->ebp; 4454 env->regs[R_ESP] = regs->esp; 4455 env->eip = regs->eip; 4456 #endif 4457 4458 /* linux interrupt setup */ 4459 #ifndef TARGET_ABI32 4460 env->idt.limit = 511; 4461 #else 4462 env->idt.limit = 255; 4463 #endif 4464 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), 4465 PROT_READ|PROT_WRITE, 4466 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4467 idt_table = g2h(env->idt.base); 4468 set_idt(0, 0); 4469 set_idt(1, 0); 4470 set_idt(2, 0); 4471 set_idt(3, 3); 4472 set_idt(4, 3); 4473 set_idt(5, 0); 4474 set_idt(6, 0); 4475 set_idt(7, 0); 4476 set_idt(8, 0); 4477 set_idt(9, 0); 4478 set_idt(10, 0); 4479 set_idt(11, 0); 4480 set_idt(12, 0); 4481 set_idt(13, 0); 4482 set_idt(14, 0); 4483 set_idt(15, 0); 4484 set_idt(16, 0); 4485 set_idt(17, 0); 4486 set_idt(18, 0); 4487 set_idt(19, 0); 4488 set_idt(0x80, 3); 4489 4490 /* linux segment setup */ 4491 { 4492 uint64_t *gdt_table; 4493 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, 4494 PROT_READ|PROT_WRITE, 4495 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); 4496 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; 4497 gdt_table = g2h(env->gdt.base); 4498 #ifdef TARGET_ABI32 4499 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4500 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4501 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4502 #else 4503 /* 64 bit code segment */ 4504 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, 4505 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4506 DESC_L_MASK | 4507 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); 4508 #endif 4509 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, 4510 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | 4511 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); 4512 } 4513 cpu_x86_load_seg(env, R_CS, __USER_CS); 4514 cpu_x86_load_seg(env, R_SS, __USER_DS); 4515 #ifdef TARGET_ABI32 4516 cpu_x86_load_seg(env, R_DS, __USER_DS); 4517 cpu_x86_load_seg(env, R_ES, __USER_DS); 4518 cpu_x86_load_seg(env, R_FS, __USER_DS); 4519 cpu_x86_load_seg(env, R_GS, __USER_DS); 4520 /* This hack makes Wine work... */ 4521 env->segs[R_FS].selector = 0; 4522 #else 4523 cpu_x86_load_seg(env, R_DS, 0); 4524 cpu_x86_load_seg(env, R_ES, 0); 4525 cpu_x86_load_seg(env, R_FS, 0); 4526 cpu_x86_load_seg(env, R_GS, 0); 4527 #endif 4528 #elif defined(TARGET_AARCH64) 4529 { 4530 int i; 4531 4532 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 4533 fprintf(stderr, 4534 "The selected ARM CPU does not support 64 bit mode\n"); 4535 exit(EXIT_FAILURE); 4536 } 4537 4538 for (i = 0; i < 31; i++) { 4539 env->xregs[i] = regs->regs[i]; 4540 } 4541 env->pc = regs->pc; 4542 env->xregs[31] = regs->sp; 4543 } 4544 #elif defined(TARGET_ARM) 4545 { 4546 int i; 4547 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, 4548 CPSRWriteByInstr); 4549 for(i = 0; i < 16; i++) { 4550 env->regs[i] = regs->uregs[i]; 4551 } 4552 #ifdef TARGET_WORDS_BIGENDIAN 4553 /* Enable BE8. */ 4554 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 4555 && (info->elf_flags & EF_ARM_BE8)) { 4556 env->uncached_cpsr |= CPSR_E; 4557 env->cp15.sctlr_el[1] |= SCTLR_E0E; 4558 } else { 4559 env->cp15.sctlr_el[1] |= SCTLR_B; 4560 } 4561 #endif 4562 } 4563 #elif defined(TARGET_UNICORE32) 4564 { 4565 int i; 4566 cpu_asr_write(env, regs->uregs[32], 0xffffffff); 4567 for (i = 0; i < 32; i++) { 4568 env->regs[i] = regs->uregs[i]; 4569 } 4570 } 4571 #elif defined(TARGET_SPARC) 4572 { 4573 int i; 4574 env->pc = regs->pc; 4575 env->npc = regs->npc; 4576 env->y = regs->y; 4577 for(i = 0; i < 8; i++) 4578 env->gregs[i] = regs->u_regs[i]; 4579 for(i = 0; i < 8; i++) 4580 env->regwptr[i] = regs->u_regs[i + 8]; 4581 } 4582 #elif defined(TARGET_PPC) 4583 { 4584 int i; 4585 4586 #if defined(TARGET_PPC64) 4587 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; 4588 #if defined(TARGET_ABI32) 4589 env->msr &= ~((target_ulong)1 << flag); 4590 #else 4591 env->msr |= (target_ulong)1 << flag; 4592 #endif 4593 #endif 4594 env->nip = regs->nip; 4595 for(i = 0; i < 32; i++) { 4596 env->gpr[i] = regs->gpr[i]; 4597 } 4598 } 4599 #elif defined(TARGET_M68K) 4600 { 4601 env->pc = regs->pc; 4602 env->dregs[0] = regs->d0; 4603 env->dregs[1] = regs->d1; 4604 env->dregs[2] = regs->d2; 4605 env->dregs[3] = regs->d3; 4606 env->dregs[4] = regs->d4; 4607 env->dregs[5] = regs->d5; 4608 env->dregs[6] = regs->d6; 4609 env->dregs[7] = regs->d7; 4610 env->aregs[0] = regs->a0; 4611 env->aregs[1] = regs->a1; 4612 env->aregs[2] = regs->a2; 4613 env->aregs[3] = regs->a3; 4614 env->aregs[4] = regs->a4; 4615 env->aregs[5] = regs->a5; 4616 env->aregs[6] = regs->a6; 4617 env->aregs[7] = regs->usp; 4618 env->sr = regs->sr; 4619 ts->sim_syscalls = 1; 4620 } 4621 #elif defined(TARGET_MICROBLAZE) 4622 { 4623 env->regs[0] = regs->r0; 4624 env->regs[1] = regs->r1; 4625 env->regs[2] = regs->r2; 4626 env->regs[3] = regs->r3; 4627 env->regs[4] = regs->r4; 4628 env->regs[5] = regs->r5; 4629 env->regs[6] = regs->r6; 4630 env->regs[7] = regs->r7; 4631 env->regs[8] = regs->r8; 4632 env->regs[9] = regs->r9; 4633 env->regs[10] = regs->r10; 4634 env->regs[11] = regs->r11; 4635 env->regs[12] = regs->r12; 4636 env->regs[13] = regs->r13; 4637 env->regs[14] = regs->r14; 4638 env->regs[15] = regs->r15; 4639 env->regs[16] = regs->r16; 4640 env->regs[17] = regs->r17; 4641 env->regs[18] = regs->r18; 4642 env->regs[19] = regs->r19; 4643 env->regs[20] = regs->r20; 4644 env->regs[21] = regs->r21; 4645 env->regs[22] = regs->r22; 4646 env->regs[23] = regs->r23; 4647 env->regs[24] = regs->r24; 4648 env->regs[25] = regs->r25; 4649 env->regs[26] = regs->r26; 4650 env->regs[27] = regs->r27; 4651 env->regs[28] = regs->r28; 4652 env->regs[29] = regs->r29; 4653 env->regs[30] = regs->r30; 4654 env->regs[31] = regs->r31; 4655 env->sregs[SR_PC] = regs->pc; 4656 } 4657 #elif defined(TARGET_MIPS) 4658 { 4659 int i; 4660 4661 for(i = 0; i < 32; i++) { 4662 env->active_tc.gpr[i] = regs->regs[i]; 4663 } 4664 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; 4665 if (regs->cp0_epc & 1) { 4666 env->hflags |= MIPS_HFLAG_M16; 4667 } 4668 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != 4669 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { 4670 if ((env->active_fpu.fcr31_rw_bitmask & 4671 (1 << FCR31_NAN2008)) == 0) { 4672 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); 4673 exit(1); 4674 } 4675 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { 4676 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); 4677 } else { 4678 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); 4679 } 4680 restore_snan_bit_mode(env); 4681 } 4682 } 4683 #elif defined(TARGET_OPENRISC) 4684 { 4685 int i; 4686 4687 for (i = 0; i < 32; i++) { 4688 env->gpr[i] = regs->gpr[i]; 4689 } 4690 4691 env->sr = regs->sr; 4692 env->pc = regs->pc; 4693 } 4694 #elif defined(TARGET_SH4) 4695 { 4696 int i; 4697 4698 for(i = 0; i < 16; i++) { 4699 env->gregs[i] = regs->regs[i]; 4700 } 4701 env->pc = regs->pc; 4702 } 4703 #elif defined(TARGET_ALPHA) 4704 { 4705 int i; 4706 4707 for(i = 0; i < 28; i++) { 4708 env->ir[i] = ((abi_ulong *)regs)[i]; 4709 } 4710 env->ir[IR_SP] = regs->usp; 4711 env->pc = regs->pc; 4712 } 4713 #elif defined(TARGET_CRIS) 4714 { 4715 env->regs[0] = regs->r0; 4716 env->regs[1] = regs->r1; 4717 env->regs[2] = regs->r2; 4718 env->regs[3] = regs->r3; 4719 env->regs[4] = regs->r4; 4720 env->regs[5] = regs->r5; 4721 env->regs[6] = regs->r6; 4722 env->regs[7] = regs->r7; 4723 env->regs[8] = regs->r8; 4724 env->regs[9] = regs->r9; 4725 env->regs[10] = regs->r10; 4726 env->regs[11] = regs->r11; 4727 env->regs[12] = regs->r12; 4728 env->regs[13] = regs->r13; 4729 env->regs[14] = info->start_stack; 4730 env->regs[15] = regs->acr; 4731 env->pc = regs->erp; 4732 } 4733 #elif defined(TARGET_S390X) 4734 { 4735 int i; 4736 for (i = 0; i < 16; i++) { 4737 env->regs[i] = regs->gprs[i]; 4738 } 4739 env->psw.mask = regs->psw.mask; 4740 env->psw.addr = regs->psw.addr; 4741 } 4742 #elif defined(TARGET_TILEGX) 4743 { 4744 int i; 4745 for (i = 0; i < TILEGX_R_COUNT; i++) { 4746 env->regs[i] = regs->regs[i]; 4747 } 4748 for (i = 0; i < TILEGX_SPR_COUNT; i++) { 4749 env->spregs[i] = 0; 4750 } 4751 env->pc = regs->pc; 4752 } 4753 #else 4754 #error unsupported target CPU 4755 #endif 4756 4757 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) 4758 ts->stack_base = info->start_stack; 4759 ts->heap_base = info->brk; 4760 /* This will be filled in on the first SYS_HEAPINFO call. */ 4761 ts->heap_limit = 0; 4762 #endif 4763 4764 if (gdbstub_port) { 4765 if (gdbserver_start(gdbstub_port) < 0) { 4766 fprintf(stderr, "qemu: could not open gdbserver on port %d\n", 4767 gdbstub_port); 4768 exit(EXIT_FAILURE); 4769 } 4770 gdb_handlesig(cpu, 0); 4771 } 4772 cpu_loop(env); 4773 /* never exits */ 4774 return 0; 4775 } 4776