1 /*
2  * host-signal.h: signal info dependent on the host architecture
3  *
4  * Copyright (c) 2003-2005 Fabrice Bellard
5  * Copyright (c) 2021 Linaro Limited
6  *
7  * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
8  * See the COPYING file in the top-level directory.
9  */
10 
11 #ifndef MIPS_HOST_SIGNAL_H
12 #define MIPS_HOST_SIGNAL_H
13 
14 static inline uintptr_t host_signal_pc(ucontext_t *uc)
15 {
16     return uc->uc_mcontext.pc;
17 }
18 
19 static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc)
20 {
21     uc->uc_mcontext.pc = pc;
22 }
23 
24 static inline void *host_signal_mask(ucontext_t *uc)
25 {
26     return &uc->uc_sigmask;
27 }
28 
29 #if defined(__misp16) || defined(__mips_micromips)
30 #error "Unsupported encoding"
31 #endif
32 
33 static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
34 {
35     uint32_t insn = *(uint32_t *)host_signal_pc(uc);
36 
37     /* Detect all store instructions at program counter. */
38     switch ((insn >> 26) & 077) {
39     case 050: /* SB */
40     case 051: /* SH */
41     case 052: /* SWL */
42     case 053: /* SW */
43     case 054: /* SDL */
44     case 055: /* SDR */
45     case 056: /* SWR */
46     case 070: /* SC */
47     case 071: /* SWC1 */
48     case 074: /* SCD */
49     case 075: /* SDC1 */
50     case 077: /* SD */
51 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6
52     case 072: /* SWC2 */
53     case 076: /* SDC2 */
54 #endif
55         return true;
56     case 023: /* COP1X */
57         /*
58          * Required in all versions of MIPS64 since
59          * MIPS64r1 and subsequent versions of MIPS32r2.
60          */
61         switch (insn & 077) {
62         case 010: /* SWXC1 */
63         case 011: /* SDXC1 */
64         case 015: /* SUXC1 */
65             return true;
66         }
67         break;
68     }
69     return false;
70 }
71 
72 #endif
73