1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "cpu_loop-common.h" 23 24 #define get_user_code_u32(x, gaddr, env) \ 25 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 26 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 27 (x) = bswap32(x); \ 28 } \ 29 __r; \ 30 }) 31 32 #define get_user_code_u16(x, gaddr, env) \ 33 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 34 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 35 (x) = bswap16(x); \ 36 } \ 37 __r; \ 38 }) 39 40 #define get_user_data_u32(x, gaddr, env) \ 41 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 42 if (!__r && arm_cpu_bswap_data(env)) { \ 43 (x) = bswap32(x); \ 44 } \ 45 __r; \ 46 }) 47 48 #define get_user_data_u16(x, gaddr, env) \ 49 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 50 if (!__r && arm_cpu_bswap_data(env)) { \ 51 (x) = bswap16(x); \ 52 } \ 53 __r; \ 54 }) 55 56 #define put_user_data_u32(x, gaddr, env) \ 57 ({ typeof(x) __x = (x); \ 58 if (arm_cpu_bswap_data(env)) { \ 59 __x = bswap32(__x); \ 60 } \ 61 put_user_u32(__x, (gaddr)); \ 62 }) 63 64 #define put_user_data_u16(x, gaddr, env) \ 65 ({ typeof(x) __x = (x); \ 66 if (arm_cpu_bswap_data(env)) { \ 67 __x = bswap16(__x); \ 68 } \ 69 put_user_u16(__x, (gaddr)); \ 70 }) 71 72 /* AArch64 main loop */ 73 void cpu_loop(CPUARMState *env) 74 { 75 CPUState *cs = CPU(arm_env_get_cpu(env)); 76 int trapnr; 77 abi_long ret; 78 target_siginfo_t info; 79 80 for (;;) { 81 cpu_exec_start(cs); 82 trapnr = cpu_exec(cs); 83 cpu_exec_end(cs); 84 process_queued_cpu_work(cs); 85 86 switch (trapnr) { 87 case EXCP_SWI: 88 ret = do_syscall(env, 89 env->xregs[8], 90 env->xregs[0], 91 env->xregs[1], 92 env->xregs[2], 93 env->xregs[3], 94 env->xregs[4], 95 env->xregs[5], 96 0, 0); 97 if (ret == -TARGET_ERESTARTSYS) { 98 env->pc -= 4; 99 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 100 env->xregs[0] = ret; 101 } 102 break; 103 case EXCP_INTERRUPT: 104 /* just indicate that signals should be handled asap */ 105 break; 106 case EXCP_UDEF: 107 info.si_signo = TARGET_SIGILL; 108 info.si_errno = 0; 109 info.si_code = TARGET_ILL_ILLOPN; 110 info._sifields._sigfault._addr = env->pc; 111 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 112 break; 113 case EXCP_PREFETCH_ABORT: 114 case EXCP_DATA_ABORT: 115 info.si_signo = TARGET_SIGSEGV; 116 info.si_errno = 0; 117 /* XXX: check env->error_code */ 118 info.si_code = TARGET_SEGV_MAPERR; 119 info._sifields._sigfault._addr = env->exception.vaddress; 120 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 121 break; 122 case EXCP_DEBUG: 123 case EXCP_BKPT: 124 info.si_signo = TARGET_SIGTRAP; 125 info.si_errno = 0; 126 info.si_code = TARGET_TRAP_BRKPT; 127 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 128 break; 129 case EXCP_SEMIHOST: 130 env->xregs[0] = do_arm_semihosting(env); 131 break; 132 case EXCP_YIELD: 133 /* nothing to do here for user-mode, just resume guest code */ 134 break; 135 case EXCP_ATOMIC: 136 cpu_exec_step_atomic(cs); 137 break; 138 default: 139 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 140 abort(); 141 } 142 process_pending_signals(env); 143 /* Exception return on AArch64 always clears the exclusive monitor, 144 * so any return to running guest code implies this. 145 */ 146 env->exclusive_addr = -1; 147 } 148 } 149 150 static uint64_t arm_rand64(void) 151 { 152 int shift = 64 - clz64(RAND_MAX); 153 int i, n = 64 / shift + (64 % shift != 0); 154 uint64_t ret = 0; 155 156 for (i = 0; i < n; i++) { 157 ret = (ret << shift) | rand(); 158 } 159 return ret; 160 } 161 162 void arm_init_pauth_key(ARMPACKey *key) 163 { 164 key->lo = arm_rand64(); 165 key->hi = arm_rand64(); 166 } 167 168 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 169 { 170 ARMCPU *cpu = arm_env_get_cpu(env); 171 CPUState *cs = CPU(cpu); 172 TaskState *ts = cs->opaque; 173 struct image_info *info = ts->info; 174 int i; 175 176 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 177 fprintf(stderr, 178 "The selected ARM CPU does not support 64 bit mode\n"); 179 exit(EXIT_FAILURE); 180 } 181 182 for (i = 0; i < 31; i++) { 183 env->xregs[i] = regs->regs[i]; 184 } 185 env->pc = regs->pc; 186 env->xregs[31] = regs->sp; 187 #ifdef TARGET_WORDS_BIGENDIAN 188 env->cp15.sctlr_el[1] |= SCTLR_E0E; 189 for (i = 1; i < 4; ++i) { 190 env->cp15.sctlr_el[i] |= SCTLR_EE; 191 } 192 #endif 193 194 if (cpu_isar_feature(aa64_pauth, cpu)) { 195 arm_init_pauth_key(&env->apia_key); 196 arm_init_pauth_key(&env->apib_key); 197 arm_init_pauth_key(&env->apda_key); 198 arm_init_pauth_key(&env->apdb_key); 199 arm_init_pauth_key(&env->apga_key); 200 } 201 202 ts->stack_base = info->start_stack; 203 ts->heap_base = info->brk; 204 /* This will be filled in on the first SYS_HEAPINFO call. */ 205 ts->heap_limit = 0; 206 } 207