1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "cpu_loop-common.h" 24 #include "signal-common.h" 25 #include "qemu/guest-random.h" 26 #include "semihosting/common-semi.h" 27 #include "target/arm/syndrome.h" 28 29 #define get_user_code_u32(x, gaddr, env) \ 30 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 31 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 32 (x) = bswap32(x); \ 33 } \ 34 __r; \ 35 }) 36 37 #define get_user_code_u16(x, gaddr, env) \ 38 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 39 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 40 (x) = bswap16(x); \ 41 } \ 42 __r; \ 43 }) 44 45 #define get_user_data_u32(x, gaddr, env) \ 46 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 47 if (!__r && arm_cpu_bswap_data(env)) { \ 48 (x) = bswap32(x); \ 49 } \ 50 __r; \ 51 }) 52 53 #define get_user_data_u16(x, gaddr, env) \ 54 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 55 if (!__r && arm_cpu_bswap_data(env)) { \ 56 (x) = bswap16(x); \ 57 } \ 58 __r; \ 59 }) 60 61 #define put_user_data_u32(x, gaddr, env) \ 62 ({ typeof(x) __x = (x); \ 63 if (arm_cpu_bswap_data(env)) { \ 64 __x = bswap32(__x); \ 65 } \ 66 put_user_u32(__x, (gaddr)); \ 67 }) 68 69 #define put_user_data_u16(x, gaddr, env) \ 70 ({ typeof(x) __x = (x); \ 71 if (arm_cpu_bswap_data(env)) { \ 72 __x = bswap16(__x); \ 73 } \ 74 put_user_u16(__x, (gaddr)); \ 75 }) 76 77 /* AArch64 main loop */ 78 void cpu_loop(CPUARMState *env) 79 { 80 CPUState *cs = env_cpu(env); 81 int trapnr, ec, fsc, si_code, si_signo; 82 abi_long ret; 83 84 for (;;) { 85 cpu_exec_start(cs); 86 trapnr = cpu_exec(cs); 87 cpu_exec_end(cs); 88 process_queued_cpu_work(cs); 89 90 switch (trapnr) { 91 case EXCP_SWI: 92 /* 93 * On syscall, PSTATE.ZA is preserved, along with the ZA matrix. 94 * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. 95 */ 96 aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); 97 if (FIELD_EX64(env->svcr, SVCR, SM)) { 98 arm_rebuild_hflags(env); 99 } 100 ret = do_syscall(env, 101 env->xregs[8], 102 env->xregs[0], 103 env->xregs[1], 104 env->xregs[2], 105 env->xregs[3], 106 env->xregs[4], 107 env->xregs[5], 108 0, 0); 109 if (ret == -QEMU_ERESTARTSYS) { 110 env->pc -= 4; 111 } else if (ret != -QEMU_ESIGRETURN) { 112 env->xregs[0] = ret; 113 } 114 break; 115 case EXCP_INTERRUPT: 116 /* just indicate that signals should be handled asap */ 117 break; 118 case EXCP_UDEF: 119 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); 120 break; 121 case EXCP_PREFETCH_ABORT: 122 case EXCP_DATA_ABORT: 123 ec = syn_get_ec(env->exception.syndrome); 124 switch (ec) { 125 case EC_DATAABORT: 126 case EC_INSNABORT: 127 /* Both EC have the same format for FSC, or close enough. */ 128 fsc = extract32(env->exception.syndrome, 0, 6); 129 switch (fsc) { 130 case 0x04 ... 0x07: /* Translation fault, level {0-3} */ 131 si_signo = TARGET_SIGSEGV; 132 si_code = TARGET_SEGV_MAPERR; 133 break; 134 case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ 135 case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ 136 si_signo = TARGET_SIGSEGV; 137 si_code = TARGET_SEGV_ACCERR; 138 break; 139 case 0x11: /* Synchronous Tag Check Fault */ 140 si_signo = TARGET_SIGSEGV; 141 si_code = TARGET_SEGV_MTESERR; 142 break; 143 case 0x21: /* Alignment fault */ 144 si_signo = TARGET_SIGBUS; 145 si_code = TARGET_BUS_ADRALN; 146 break; 147 default: 148 g_assert_not_reached(); 149 } 150 break; 151 case EC_PCALIGNMENT: 152 si_signo = TARGET_SIGBUS; 153 si_code = TARGET_BUS_ADRALN; 154 break; 155 default: 156 g_assert_not_reached(); 157 } 158 force_sig_fault(si_signo, si_code, env->exception.vaddress); 159 break; 160 case EXCP_DEBUG: 161 case EXCP_BKPT: 162 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); 163 break; 164 case EXCP_SEMIHOST: 165 do_common_semihosting(cs); 166 env->pc += 4; 167 break; 168 case EXCP_YIELD: 169 /* nothing to do here for user-mode, just resume guest code */ 170 break; 171 case EXCP_ATOMIC: 172 cpu_exec_step_atomic(cs); 173 break; 174 default: 175 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 176 abort(); 177 } 178 179 /* Check for MTE asynchronous faults */ 180 if (unlikely(env->cp15.tfsr_el[0])) { 181 env->cp15.tfsr_el[0] = 0; 182 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0); 183 } 184 185 process_pending_signals(env); 186 /* Exception return on AArch64 always clears the exclusive monitor, 187 * so any return to running guest code implies this. 188 */ 189 env->exclusive_addr = -1; 190 } 191 } 192 193 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 194 { 195 ARMCPU *cpu = env_archcpu(env); 196 CPUState *cs = env_cpu(env); 197 TaskState *ts = cs->opaque; 198 struct image_info *info = ts->info; 199 int i; 200 201 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 202 fprintf(stderr, 203 "The selected ARM CPU does not support 64 bit mode\n"); 204 exit(EXIT_FAILURE); 205 } 206 207 for (i = 0; i < 31; i++) { 208 env->xregs[i] = regs->regs[i]; 209 } 210 env->pc = regs->pc; 211 env->xregs[31] = regs->sp; 212 #if TARGET_BIG_ENDIAN 213 env->cp15.sctlr_el[1] |= SCTLR_E0E; 214 for (i = 1; i < 4; ++i) { 215 env->cp15.sctlr_el[i] |= SCTLR_EE; 216 } 217 arm_rebuild_hflags(env); 218 #endif 219 220 if (cpu_isar_feature(aa64_pauth, cpu)) { 221 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys)); 222 } 223 224 ts->stack_base = info->start_stack; 225 ts->heap_base = info->brk; 226 /* This will be filled in on the first SYS_HEAPINFO call. */ 227 ts->heap_limit = 0; 228 } 229