1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu.h" 23 #include "cpu_loop-common.h" 24 #include "qemu/guest-random.h" 25 #include "hw/semihosting/common-semi.h" 26 27 #define get_user_code_u32(x, gaddr, env) \ 28 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 29 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 30 (x) = bswap32(x); \ 31 } \ 32 __r; \ 33 }) 34 35 #define get_user_code_u16(x, gaddr, env) \ 36 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 37 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 38 (x) = bswap16(x); \ 39 } \ 40 __r; \ 41 }) 42 43 #define get_user_data_u32(x, gaddr, env) \ 44 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 45 if (!__r && arm_cpu_bswap_data(env)) { \ 46 (x) = bswap32(x); \ 47 } \ 48 __r; \ 49 }) 50 51 #define get_user_data_u16(x, gaddr, env) \ 52 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 53 if (!__r && arm_cpu_bswap_data(env)) { \ 54 (x) = bswap16(x); \ 55 } \ 56 __r; \ 57 }) 58 59 #define put_user_data_u32(x, gaddr, env) \ 60 ({ typeof(x) __x = (x); \ 61 if (arm_cpu_bswap_data(env)) { \ 62 __x = bswap32(__x); \ 63 } \ 64 put_user_u32(__x, (gaddr)); \ 65 }) 66 67 #define put_user_data_u16(x, gaddr, env) \ 68 ({ typeof(x) __x = (x); \ 69 if (arm_cpu_bswap_data(env)) { \ 70 __x = bswap16(__x); \ 71 } \ 72 put_user_u16(__x, (gaddr)); \ 73 }) 74 75 /* AArch64 main loop */ 76 void cpu_loop(CPUARMState *env) 77 { 78 CPUState *cs = env_cpu(env); 79 int trapnr; 80 abi_long ret; 81 target_siginfo_t info; 82 83 for (;;) { 84 cpu_exec_start(cs); 85 trapnr = cpu_exec(cs); 86 cpu_exec_end(cs); 87 process_queued_cpu_work(cs); 88 89 switch (trapnr) { 90 case EXCP_SWI: 91 ret = do_syscall(env, 92 env->xregs[8], 93 env->xregs[0], 94 env->xregs[1], 95 env->xregs[2], 96 env->xregs[3], 97 env->xregs[4], 98 env->xregs[5], 99 0, 0); 100 if (ret == -TARGET_ERESTARTSYS) { 101 env->pc -= 4; 102 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 103 env->xregs[0] = ret; 104 } 105 break; 106 case EXCP_INTERRUPT: 107 /* just indicate that signals should be handled asap */ 108 break; 109 case EXCP_UDEF: 110 info.si_signo = TARGET_SIGILL; 111 info.si_errno = 0; 112 info.si_code = TARGET_ILL_ILLOPN; 113 info._sifields._sigfault._addr = env->pc; 114 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 115 break; 116 case EXCP_PREFETCH_ABORT: 117 case EXCP_DATA_ABORT: 118 info.si_signo = TARGET_SIGSEGV; 119 info.si_errno = 0; 120 /* XXX: check env->error_code */ 121 info.si_code = TARGET_SEGV_MAPERR; 122 info._sifields._sigfault._addr = env->exception.vaddress; 123 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 124 break; 125 case EXCP_DEBUG: 126 case EXCP_BKPT: 127 info.si_signo = TARGET_SIGTRAP; 128 info.si_errno = 0; 129 info.si_code = TARGET_TRAP_BRKPT; 130 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 131 break; 132 case EXCP_SEMIHOST: 133 env->xregs[0] = do_common_semihosting(cs); 134 env->pc += 4; 135 break; 136 case EXCP_YIELD: 137 /* nothing to do here for user-mode, just resume guest code */ 138 break; 139 case EXCP_ATOMIC: 140 cpu_exec_step_atomic(cs); 141 break; 142 default: 143 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 144 abort(); 145 } 146 process_pending_signals(env); 147 /* Exception return on AArch64 always clears the exclusive monitor, 148 * so any return to running guest code implies this. 149 */ 150 env->exclusive_addr = -1; 151 } 152 } 153 154 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 155 { 156 ARMCPU *cpu = env_archcpu(env); 157 CPUState *cs = env_cpu(env); 158 TaskState *ts = cs->opaque; 159 struct image_info *info = ts->info; 160 int i; 161 162 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 163 fprintf(stderr, 164 "The selected ARM CPU does not support 64 bit mode\n"); 165 exit(EXIT_FAILURE); 166 } 167 168 for (i = 0; i < 31; i++) { 169 env->xregs[i] = regs->regs[i]; 170 } 171 env->pc = regs->pc; 172 env->xregs[31] = regs->sp; 173 #ifdef TARGET_WORDS_BIGENDIAN 174 env->cp15.sctlr_el[1] |= SCTLR_E0E; 175 for (i = 1; i < 4; ++i) { 176 env->cp15.sctlr_el[i] |= SCTLR_EE; 177 } 178 arm_rebuild_hflags(env); 179 #endif 180 181 if (cpu_isar_feature(aa64_pauth, cpu)) { 182 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys)); 183 } 184 185 ts->stack_base = info->start_stack; 186 ts->heap_base = info->brk; 187 /* This will be filled in on the first SYS_HEAPINFO call. */ 188 ts->heap_limit = 0; 189 } 190