1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu.h" 23 #include "cpu_loop-common.h" 24 #include "qemu/guest-random.h" 25 26 #define get_user_code_u32(x, gaddr, env) \ 27 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 28 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 29 (x) = bswap32(x); \ 30 } \ 31 __r; \ 32 }) 33 34 #define get_user_code_u16(x, gaddr, env) \ 35 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 36 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 37 (x) = bswap16(x); \ 38 } \ 39 __r; \ 40 }) 41 42 #define get_user_data_u32(x, gaddr, env) \ 43 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 44 if (!__r && arm_cpu_bswap_data(env)) { \ 45 (x) = bswap32(x); \ 46 } \ 47 __r; \ 48 }) 49 50 #define get_user_data_u16(x, gaddr, env) \ 51 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 52 if (!__r && arm_cpu_bswap_data(env)) { \ 53 (x) = bswap16(x); \ 54 } \ 55 __r; \ 56 }) 57 58 #define put_user_data_u32(x, gaddr, env) \ 59 ({ typeof(x) __x = (x); \ 60 if (arm_cpu_bswap_data(env)) { \ 61 __x = bswap32(__x); \ 62 } \ 63 put_user_u32(__x, (gaddr)); \ 64 }) 65 66 #define put_user_data_u16(x, gaddr, env) \ 67 ({ typeof(x) __x = (x); \ 68 if (arm_cpu_bswap_data(env)) { \ 69 __x = bswap16(__x); \ 70 } \ 71 put_user_u16(__x, (gaddr)); \ 72 }) 73 74 /* AArch64 main loop */ 75 void cpu_loop(CPUARMState *env) 76 { 77 CPUState *cs = env_cpu(env); 78 int trapnr; 79 abi_long ret; 80 target_siginfo_t info; 81 82 for (;;) { 83 cpu_exec_start(cs); 84 trapnr = cpu_exec(cs); 85 cpu_exec_end(cs); 86 process_queued_cpu_work(cs); 87 88 switch (trapnr) { 89 case EXCP_SWI: 90 ret = do_syscall(env, 91 env->xregs[8], 92 env->xregs[0], 93 env->xregs[1], 94 env->xregs[2], 95 env->xregs[3], 96 env->xregs[4], 97 env->xregs[5], 98 0, 0); 99 if (ret == -TARGET_ERESTARTSYS) { 100 env->pc -= 4; 101 } else if (ret != -TARGET_QEMU_ESIGRETURN) { 102 env->xregs[0] = ret; 103 } 104 break; 105 case EXCP_INTERRUPT: 106 /* just indicate that signals should be handled asap */ 107 break; 108 case EXCP_UDEF: 109 info.si_signo = TARGET_SIGILL; 110 info.si_errno = 0; 111 info.si_code = TARGET_ILL_ILLOPN; 112 info._sifields._sigfault._addr = env->pc; 113 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 114 break; 115 case EXCP_PREFETCH_ABORT: 116 case EXCP_DATA_ABORT: 117 info.si_signo = TARGET_SIGSEGV; 118 info.si_errno = 0; 119 /* XXX: check env->error_code */ 120 info.si_code = TARGET_SEGV_MAPERR; 121 info._sifields._sigfault._addr = env->exception.vaddress; 122 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 123 break; 124 case EXCP_DEBUG: 125 case EXCP_BKPT: 126 info.si_signo = TARGET_SIGTRAP; 127 info.si_errno = 0; 128 info.si_code = TARGET_TRAP_BRKPT; 129 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); 130 break; 131 case EXCP_SEMIHOST: 132 env->xregs[0] = do_arm_semihosting(env); 133 env->pc += 4; 134 break; 135 case EXCP_YIELD: 136 /* nothing to do here for user-mode, just resume guest code */ 137 break; 138 case EXCP_ATOMIC: 139 cpu_exec_step_atomic(cs); 140 break; 141 default: 142 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 143 abort(); 144 } 145 process_pending_signals(env); 146 /* Exception return on AArch64 always clears the exclusive monitor, 147 * so any return to running guest code implies this. 148 */ 149 env->exclusive_addr = -1; 150 } 151 } 152 153 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 154 { 155 ARMCPU *cpu = env_archcpu(env); 156 CPUState *cs = env_cpu(env); 157 TaskState *ts = cs->opaque; 158 struct image_info *info = ts->info; 159 int i; 160 161 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 162 fprintf(stderr, 163 "The selected ARM CPU does not support 64 bit mode\n"); 164 exit(EXIT_FAILURE); 165 } 166 167 for (i = 0; i < 31; i++) { 168 env->xregs[i] = regs->regs[i]; 169 } 170 env->pc = regs->pc; 171 env->xregs[31] = regs->sp; 172 #ifdef TARGET_WORDS_BIGENDIAN 173 env->cp15.sctlr_el[1] |= SCTLR_E0E; 174 for (i = 1; i < 4; ++i) { 175 env->cp15.sctlr_el[i] |= SCTLR_EE; 176 } 177 arm_rebuild_hflags(env); 178 #endif 179 180 if (cpu_isar_feature(aa64_pauth, cpu)) { 181 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys)); 182 } 183 184 ts->stack_base = info->start_stack; 185 ts->heap_base = info->brk; 186 /* This will be filled in on the first SYS_HEAPINFO call. */ 187 ts->heap_limit = 0; 188 } 189