1 /* 2 * qemu user cpu loop 3 * 4 * Copyright (c) 2003-2008 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu.h" 22 #include "user-internals.h" 23 #include "cpu_loop-common.h" 24 #include "signal-common.h" 25 #include "qemu/guest-random.h" 26 #include "semihosting/common-semi.h" 27 #include "target/arm/syndrome.h" 28 29 #define get_user_code_u32(x, gaddr, env) \ 30 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 31 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 32 (x) = bswap32(x); \ 33 } \ 34 __r; \ 35 }) 36 37 #define get_user_code_u16(x, gaddr, env) \ 38 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 39 if (!__r && bswap_code(arm_sctlr_b(env))) { \ 40 (x) = bswap16(x); \ 41 } \ 42 __r; \ 43 }) 44 45 #define get_user_data_u32(x, gaddr, env) \ 46 ({ abi_long __r = get_user_u32((x), (gaddr)); \ 47 if (!__r && arm_cpu_bswap_data(env)) { \ 48 (x) = bswap32(x); \ 49 } \ 50 __r; \ 51 }) 52 53 #define get_user_data_u16(x, gaddr, env) \ 54 ({ abi_long __r = get_user_u16((x), (gaddr)); \ 55 if (!__r && arm_cpu_bswap_data(env)) { \ 56 (x) = bswap16(x); \ 57 } \ 58 __r; \ 59 }) 60 61 #define put_user_data_u32(x, gaddr, env) \ 62 ({ typeof(x) __x = (x); \ 63 if (arm_cpu_bswap_data(env)) { \ 64 __x = bswap32(__x); \ 65 } \ 66 put_user_u32(__x, (gaddr)); \ 67 }) 68 69 #define put_user_data_u16(x, gaddr, env) \ 70 ({ typeof(x) __x = (x); \ 71 if (arm_cpu_bswap_data(env)) { \ 72 __x = bswap16(__x); \ 73 } \ 74 put_user_u16(__x, (gaddr)); \ 75 }) 76 77 /* AArch64 main loop */ 78 void cpu_loop(CPUARMState *env) 79 { 80 CPUState *cs = env_cpu(env); 81 int trapnr, ec, fsc, si_code, si_signo; 82 abi_long ret; 83 84 for (;;) { 85 cpu_exec_start(cs); 86 trapnr = cpu_exec(cs); 87 cpu_exec_end(cs); 88 process_queued_cpu_work(cs); 89 90 switch (trapnr) { 91 case EXCP_SWI: 92 /* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */ 93 aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); 94 ret = do_syscall(env, 95 env->xregs[8], 96 env->xregs[0], 97 env->xregs[1], 98 env->xregs[2], 99 env->xregs[3], 100 env->xregs[4], 101 env->xregs[5], 102 0, 0); 103 if (ret == -QEMU_ERESTARTSYS) { 104 env->pc -= 4; 105 } else if (ret != -QEMU_ESIGRETURN) { 106 env->xregs[0] = ret; 107 } 108 break; 109 case EXCP_INTERRUPT: 110 /* just indicate that signals should be handled asap */ 111 break; 112 case EXCP_UDEF: 113 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); 114 break; 115 case EXCP_PREFETCH_ABORT: 116 case EXCP_DATA_ABORT: 117 ec = syn_get_ec(env->exception.syndrome); 118 switch (ec) { 119 case EC_DATAABORT: 120 case EC_INSNABORT: 121 /* Both EC have the same format for FSC, or close enough. */ 122 fsc = extract32(env->exception.syndrome, 0, 6); 123 switch (fsc) { 124 case 0x04 ... 0x07: /* Translation fault, level {0-3} */ 125 si_signo = TARGET_SIGSEGV; 126 si_code = TARGET_SEGV_MAPERR; 127 break; 128 case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ 129 case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ 130 si_signo = TARGET_SIGSEGV; 131 si_code = TARGET_SEGV_ACCERR; 132 break; 133 case 0x11: /* Synchronous Tag Check Fault */ 134 si_signo = TARGET_SIGSEGV; 135 si_code = TARGET_SEGV_MTESERR; 136 break; 137 case 0x21: /* Alignment fault */ 138 si_signo = TARGET_SIGBUS; 139 si_code = TARGET_BUS_ADRALN; 140 break; 141 default: 142 g_assert_not_reached(); 143 } 144 break; 145 case EC_PCALIGNMENT: 146 si_signo = TARGET_SIGBUS; 147 si_code = TARGET_BUS_ADRALN; 148 break; 149 default: 150 g_assert_not_reached(); 151 } 152 force_sig_fault(si_signo, si_code, env->exception.vaddress); 153 break; 154 case EXCP_DEBUG: 155 case EXCP_BKPT: 156 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); 157 break; 158 case EXCP_SEMIHOST: 159 do_common_semihosting(cs); 160 env->pc += 4; 161 break; 162 case EXCP_YIELD: 163 /* nothing to do here for user-mode, just resume guest code */ 164 break; 165 case EXCP_ATOMIC: 166 cpu_exec_step_atomic(cs); 167 break; 168 default: 169 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); 170 abort(); 171 } 172 173 /* Check for MTE asynchronous faults */ 174 if (unlikely(env->cp15.tfsr_el[0])) { 175 env->cp15.tfsr_el[0] = 0; 176 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0); 177 } 178 179 process_pending_signals(env); 180 /* Exception return on AArch64 always clears the exclusive monitor, 181 * so any return to running guest code implies this. 182 */ 183 env->exclusive_addr = -1; 184 } 185 } 186 187 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) 188 { 189 ARMCPU *cpu = env_archcpu(env); 190 CPUState *cs = env_cpu(env); 191 TaskState *ts = cs->opaque; 192 struct image_info *info = ts->info; 193 int i; 194 195 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { 196 fprintf(stderr, 197 "The selected ARM CPU does not support 64 bit mode\n"); 198 exit(EXIT_FAILURE); 199 } 200 201 for (i = 0; i < 31; i++) { 202 env->xregs[i] = regs->regs[i]; 203 } 204 env->pc = regs->pc; 205 env->xregs[31] = regs->sp; 206 #if TARGET_BIG_ENDIAN 207 env->cp15.sctlr_el[1] |= SCTLR_E0E; 208 for (i = 1; i < 4; ++i) { 209 env->cp15.sctlr_el[i] |= SCTLR_EE; 210 } 211 arm_rebuild_hflags(env); 212 #endif 213 214 if (cpu_isar_feature(aa64_pauth, cpu)) { 215 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys)); 216 } 217 218 ts->stack_base = info->start_stack; 219 ts->heap_base = info->brk; 220 /* This will be filled in on the first SYS_HEAPINFO call. */ 221 ts->heap_limit = 0; 222 } 223