1 #ifndef _ASM_X86_KVM_H 2 #define _ASM_X86_KVM_H 3 4 /* 5 * KVM x86 specific structures and definitions 6 * 7 */ 8 9 #include <linux/types.h> 10 #include <linux/ioctl.h> 11 12 #define KVM_PIO_PAGE_OFFSET 1 13 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 14 15 #define DE_VECTOR 0 16 #define DB_VECTOR 1 17 #define BP_VECTOR 3 18 #define OF_VECTOR 4 19 #define BR_VECTOR 5 20 #define UD_VECTOR 6 21 #define NM_VECTOR 7 22 #define DF_VECTOR 8 23 #define TS_VECTOR 10 24 #define NP_VECTOR 11 25 #define SS_VECTOR 12 26 #define GP_VECTOR 13 27 #define PF_VECTOR 14 28 #define MF_VECTOR 16 29 #define AC_VECTOR 17 30 #define MC_VECTOR 18 31 #define XM_VECTOR 19 32 #define VE_VECTOR 20 33 34 /* Select x86 specific features in <linux/kvm.h> */ 35 #define __KVM_HAVE_PIT 36 #define __KVM_HAVE_IOAPIC 37 #define __KVM_HAVE_IRQ_LINE 38 #define __KVM_HAVE_MSI 39 #define __KVM_HAVE_USER_NMI 40 #define __KVM_HAVE_GUEST_DEBUG 41 #define __KVM_HAVE_MSIX 42 #define __KVM_HAVE_MCE 43 #define __KVM_HAVE_PIT_STATE2 44 #define __KVM_HAVE_XEN_HVM 45 #define __KVM_HAVE_VCPU_EVENTS 46 #define __KVM_HAVE_DEBUGREGS 47 #define __KVM_HAVE_XSAVE 48 #define __KVM_HAVE_XCRS 49 #define __KVM_HAVE_READONLY_MEM 50 51 /* Architectural interrupt line count. */ 52 #define KVM_NR_INTERRUPTS 256 53 54 struct kvm_memory_alias { 55 __u32 slot; /* this has a different namespace than memory slots */ 56 __u32 flags; 57 __u64 guest_phys_addr; 58 __u64 memory_size; 59 __u64 target_phys_addr; 60 }; 61 62 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ 63 struct kvm_pic_state { 64 __u8 last_irr; /* edge detection */ 65 __u8 irr; /* interrupt request register */ 66 __u8 imr; /* interrupt mask register */ 67 __u8 isr; /* interrupt service register */ 68 __u8 priority_add; /* highest irq priority */ 69 __u8 irq_base; 70 __u8 read_reg_select; 71 __u8 poll; 72 __u8 special_mask; 73 __u8 init_state; 74 __u8 auto_eoi; 75 __u8 rotate_on_auto_eoi; 76 __u8 special_fully_nested_mode; 77 __u8 init4; /* true if 4 byte init */ 78 __u8 elcr; /* PIIX edge/trigger selection */ 79 __u8 elcr_mask; 80 }; 81 82 #define KVM_IOAPIC_NUM_PINS 24 83 struct kvm_ioapic_state { 84 __u64 base_address; 85 __u32 ioregsel; 86 __u32 id; 87 __u32 irr; 88 __u32 pad; 89 union { 90 __u64 bits; 91 struct { 92 __u8 vector; 93 __u8 delivery_mode:3; 94 __u8 dest_mode:1; 95 __u8 delivery_status:1; 96 __u8 polarity:1; 97 __u8 remote_irr:1; 98 __u8 trig_mode:1; 99 __u8 mask:1; 100 __u8 reserve:7; 101 __u8 reserved[4]; 102 __u8 dest_id; 103 } fields; 104 } redirtbl[KVM_IOAPIC_NUM_PINS]; 105 }; 106 107 #define KVM_IRQCHIP_PIC_MASTER 0 108 #define KVM_IRQCHIP_PIC_SLAVE 1 109 #define KVM_IRQCHIP_IOAPIC 2 110 #define KVM_NR_IRQCHIPS 3 111 112 #define KVM_RUN_X86_SMM (1 << 0) 113 114 /* for KVM_GET_REGS and KVM_SET_REGS */ 115 struct kvm_regs { 116 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 117 __u64 rax, rbx, rcx, rdx; 118 __u64 rsi, rdi, rsp, rbp; 119 __u64 r8, r9, r10, r11; 120 __u64 r12, r13, r14, r15; 121 __u64 rip, rflags; 122 }; 123 124 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ 125 #define KVM_APIC_REG_SIZE 0x400 126 struct kvm_lapic_state { 127 char regs[KVM_APIC_REG_SIZE]; 128 }; 129 130 struct kvm_segment { 131 __u64 base; 132 __u32 limit; 133 __u16 selector; 134 __u8 type; 135 __u8 present, dpl, db, s, l, g, avl; 136 __u8 unusable; 137 __u8 padding; 138 }; 139 140 struct kvm_dtable { 141 __u64 base; 142 __u16 limit; 143 __u16 padding[3]; 144 }; 145 146 147 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 148 struct kvm_sregs { 149 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ 150 struct kvm_segment cs, ds, es, fs, gs, ss; 151 struct kvm_segment tr, ldt; 152 struct kvm_dtable gdt, idt; 153 __u64 cr0, cr2, cr3, cr4, cr8; 154 __u64 efer; 155 __u64 apic_base; 156 __u64 interrupt_bitmap[DIV_ROUND_UP(KVM_NR_INTERRUPTS, 64)]; 157 }; 158 159 /* for KVM_GET_FPU and KVM_SET_FPU */ 160 struct kvm_fpu { 161 __u8 fpr[8][16]; 162 __u16 fcw; 163 __u16 fsw; 164 __u8 ftwx; /* in fxsave format */ 165 __u8 pad1; 166 __u16 last_opcode; 167 __u64 last_ip; 168 __u64 last_dp; 169 __u8 xmm[16][16]; 170 __u32 mxcsr; 171 __u32 pad2; 172 }; 173 174 struct kvm_msr_entry { 175 __u32 index; 176 __u32 reserved; 177 __u64 data; 178 }; 179 180 /* for KVM_GET_MSRS and KVM_SET_MSRS */ 181 struct kvm_msrs { 182 __u32 nmsrs; /* number of msrs in entries */ 183 __u32 pad; 184 185 struct kvm_msr_entry entries[0]; 186 }; 187 188 /* for KVM_GET_MSR_INDEX_LIST */ 189 struct kvm_msr_list { 190 __u32 nmsrs; /* number of msrs in entries */ 191 __u32 indices[0]; 192 }; 193 194 195 struct kvm_cpuid_entry { 196 __u32 function; 197 __u32 eax; 198 __u32 ebx; 199 __u32 ecx; 200 __u32 edx; 201 __u32 padding; 202 }; 203 204 /* for KVM_SET_CPUID */ 205 struct kvm_cpuid { 206 __u32 nent; 207 __u32 padding; 208 struct kvm_cpuid_entry entries[0]; 209 }; 210 211 struct kvm_cpuid_entry2 { 212 __u32 function; 213 __u32 index; 214 __u32 flags; 215 __u32 eax; 216 __u32 ebx; 217 __u32 ecx; 218 __u32 edx; 219 __u32 padding[3]; 220 }; 221 222 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) 223 #define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) 224 #define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) 225 226 /* for KVM_SET_CPUID2 */ 227 struct kvm_cpuid2 { 228 __u32 nent; 229 __u32 padding; 230 struct kvm_cpuid_entry2 entries[0]; 231 }; 232 233 /* for KVM_GET_PIT and KVM_SET_PIT */ 234 struct kvm_pit_channel_state { 235 __u32 count; /* can be 65536 */ 236 __u16 latched_count; 237 __u8 count_latched; 238 __u8 status_latched; 239 __u8 status; 240 __u8 read_state; 241 __u8 write_state; 242 __u8 write_latch; 243 __u8 rw_mode; 244 __u8 mode; 245 __u8 bcd; 246 __u8 gate; 247 __s64 count_load_time; 248 }; 249 250 struct kvm_debug_exit_arch { 251 __u32 exception; 252 __u32 pad; 253 __u64 pc; 254 __u64 dr6; 255 __u64 dr7; 256 }; 257 258 #define KVM_GUESTDBG_USE_SW_BP 0x00010000 259 #define KVM_GUESTDBG_USE_HW_BP 0x00020000 260 #define KVM_GUESTDBG_INJECT_DB 0x00040000 261 #define KVM_GUESTDBG_INJECT_BP 0x00080000 262 263 /* for KVM_SET_GUEST_DEBUG */ 264 struct kvm_guest_debug_arch { 265 __u64 debugreg[8]; 266 }; 267 268 struct kvm_pit_state { 269 struct kvm_pit_channel_state channels[3]; 270 }; 271 272 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 273 274 struct kvm_pit_state2 { 275 struct kvm_pit_channel_state channels[3]; 276 __u32 flags; 277 __u32 reserved[9]; 278 }; 279 280 struct kvm_reinject_control { 281 __u8 pit_reinject; 282 __u8 reserved[31]; 283 }; 284 285 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ 286 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 287 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 288 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 289 #define KVM_VCPUEVENT_VALID_SMM 0x00000008 290 291 /* Interrupt shadow states */ 292 #define KVM_X86_SHADOW_INT_MOV_SS 0x01 293 #define KVM_X86_SHADOW_INT_STI 0x02 294 295 /* for KVM_GET/SET_VCPU_EVENTS */ 296 struct kvm_vcpu_events { 297 struct { 298 __u8 injected; 299 __u8 nr; 300 __u8 has_error_code; 301 __u8 pad; 302 __u32 error_code; 303 } exception; 304 struct { 305 __u8 injected; 306 __u8 nr; 307 __u8 soft; 308 __u8 shadow; 309 } interrupt; 310 struct { 311 __u8 injected; 312 __u8 pending; 313 __u8 masked; 314 __u8 pad; 315 } nmi; 316 __u32 sipi_vector; 317 __u32 flags; 318 struct { 319 __u8 smm; 320 __u8 pending; 321 __u8 smm_inside_nmi; 322 __u8 latched_init; 323 } smi; 324 __u32 reserved[9]; 325 }; 326 327 /* for KVM_GET/SET_DEBUGREGS */ 328 struct kvm_debugregs { 329 __u64 db[4]; 330 __u64 dr6; 331 __u64 dr7; 332 __u64 flags; 333 __u64 reserved[9]; 334 }; 335 336 /* for KVM_CAP_XSAVE */ 337 struct kvm_xsave { 338 __u32 region[1024]; 339 }; 340 341 #define KVM_MAX_XCRS 16 342 343 struct kvm_xcr { 344 __u32 xcr; 345 __u32 reserved; 346 __u64 value; 347 }; 348 349 struct kvm_xcrs { 350 __u32 nr_xcrs; 351 __u32 flags; 352 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 353 __u64 padding[16]; 354 }; 355 356 /* definition of registers in kvm_run */ 357 struct kvm_sync_regs { 358 }; 359 360 #define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) 361 #define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) 362 363 #endif /* _ASM_X86_KVM_H */ 364