1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2019 Western Digital Corporation or its affiliates. 4 * 5 * Authors: 6 * Anup Patel <anup.patel@wdc.com> 7 */ 8 9 #ifndef __LINUX_KVM_RISCV_H 10 #define __LINUX_KVM_RISCV_H 11 12 #ifndef __ASSEMBLY__ 13 14 #include <linux/types.h> 15 #include <asm/bitsperlong.h> 16 #include <asm/ptrace.h> 17 18 #define __KVM_HAVE_IRQ_LINE 19 #define __KVM_HAVE_READONLY_MEM 20 21 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 22 23 #define KVM_INTERRUPT_SET -1U 24 #define KVM_INTERRUPT_UNSET -2U 25 26 /* for KVM_GET_REGS and KVM_SET_REGS */ 27 struct kvm_regs { 28 }; 29 30 /* for KVM_GET_FPU and KVM_SET_FPU */ 31 struct kvm_fpu { 32 }; 33 34 /* KVM Debug exit structure */ 35 struct kvm_debug_exit_arch { 36 }; 37 38 /* for KVM_SET_GUEST_DEBUG */ 39 struct kvm_guest_debug_arch { 40 }; 41 42 /* definition of registers in kvm_run */ 43 struct kvm_sync_regs { 44 }; 45 46 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 47 struct kvm_sregs { 48 }; 49 50 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 51 struct kvm_riscv_config { 52 unsigned long isa; 53 unsigned long zicbom_block_size; 54 unsigned long mvendorid; 55 unsigned long marchid; 56 unsigned long mimpid; 57 unsigned long zicboz_block_size; 58 unsigned long satp_mode; 59 }; 60 61 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 62 struct kvm_riscv_core { 63 struct user_regs_struct regs; 64 unsigned long mode; 65 }; 66 67 /* Possible privilege modes for kvm_riscv_core */ 68 #define KVM_RISCV_MODE_S 1 69 #define KVM_RISCV_MODE_U 0 70 71 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 72 struct kvm_riscv_csr { 73 unsigned long sstatus; 74 unsigned long sie; 75 unsigned long stvec; 76 unsigned long sscratch; 77 unsigned long sepc; 78 unsigned long scause; 79 unsigned long stval; 80 unsigned long sip; 81 unsigned long satp; 82 unsigned long scounteren; 83 unsigned long senvcfg; 84 }; 85 86 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 87 struct kvm_riscv_aia_csr { 88 unsigned long siselect; 89 unsigned long iprio1; 90 unsigned long iprio2; 91 unsigned long sieh; 92 unsigned long siph; 93 unsigned long iprio1h; 94 unsigned long iprio2h; 95 }; 96 97 /* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 98 struct kvm_riscv_smstateen_csr { 99 unsigned long sstateen0; 100 }; 101 102 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ 103 struct kvm_riscv_timer { 104 __u64 frequency; 105 __u64 time; 106 __u64 compare; 107 __u64 state; 108 }; 109 110 /* 111 * ISA extension IDs specific to KVM. This is not the same as the host ISA 112 * extension IDs as that is internal to the host and should not be exposed 113 * to the guest. This should always be contiguous to keep the mapping simple 114 * in KVM implementation. 115 */ 116 enum KVM_RISCV_ISA_EXT_ID { 117 KVM_RISCV_ISA_EXT_A = 0, 118 KVM_RISCV_ISA_EXT_C, 119 KVM_RISCV_ISA_EXT_D, 120 KVM_RISCV_ISA_EXT_F, 121 KVM_RISCV_ISA_EXT_H, 122 KVM_RISCV_ISA_EXT_I, 123 KVM_RISCV_ISA_EXT_M, 124 KVM_RISCV_ISA_EXT_SVPBMT, 125 KVM_RISCV_ISA_EXT_SSTC, 126 KVM_RISCV_ISA_EXT_SVINVAL, 127 KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 128 KVM_RISCV_ISA_EXT_ZICBOM, 129 KVM_RISCV_ISA_EXT_ZICBOZ, 130 KVM_RISCV_ISA_EXT_ZBB, 131 KVM_RISCV_ISA_EXT_SSAIA, 132 KVM_RISCV_ISA_EXT_V, 133 KVM_RISCV_ISA_EXT_SVNAPOT, 134 KVM_RISCV_ISA_EXT_ZBA, 135 KVM_RISCV_ISA_EXT_ZBS, 136 KVM_RISCV_ISA_EXT_ZICNTR, 137 KVM_RISCV_ISA_EXT_ZICSR, 138 KVM_RISCV_ISA_EXT_ZIFENCEI, 139 KVM_RISCV_ISA_EXT_ZIHPM, 140 KVM_RISCV_ISA_EXT_SMSTATEEN, 141 KVM_RISCV_ISA_EXT_ZICOND, 142 KVM_RISCV_ISA_EXT_MAX, 143 }; 144 145 /* 146 * SBI extension IDs specific to KVM. This is not the same as the SBI 147 * extension IDs defined by the RISC-V SBI specification. 148 */ 149 enum KVM_RISCV_SBI_EXT_ID { 150 KVM_RISCV_SBI_EXT_V01 = 0, 151 KVM_RISCV_SBI_EXT_TIME, 152 KVM_RISCV_SBI_EXT_IPI, 153 KVM_RISCV_SBI_EXT_RFENCE, 154 KVM_RISCV_SBI_EXT_SRST, 155 KVM_RISCV_SBI_EXT_HSM, 156 KVM_RISCV_SBI_EXT_PMU, 157 KVM_RISCV_SBI_EXT_EXPERIMENTAL, 158 KVM_RISCV_SBI_EXT_VENDOR, 159 KVM_RISCV_SBI_EXT_DBCN, 160 KVM_RISCV_SBI_EXT_MAX, 161 }; 162 163 /* Possible states for kvm_riscv_timer */ 164 #define KVM_RISCV_TIMER_STATE_OFF 0 165 #define KVM_RISCV_TIMER_STATE_ON 1 166 167 #define KVM_REG_SIZE(id) \ 168 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 169 170 /* If you need to interpret the index values, here is the key: */ 171 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 172 #define KVM_REG_RISCV_TYPE_SHIFT 24 173 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 174 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 175 176 /* Config registers are mapped as type 1 */ 177 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 178 #define KVM_REG_RISCV_CONFIG_REG(name) \ 179 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 180 181 /* Core registers are mapped as type 2 */ 182 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 183 #define KVM_REG_RISCV_CORE_REG(name) \ 184 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 185 186 /* Control and status registers are mapped as type 3 */ 187 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 188 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 189 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 190 #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 191 #define KVM_REG_RISCV_CSR_REG(name) \ 192 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 193 #define KVM_REG_RISCV_CSR_AIA_REG(name) \ 194 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 195 #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ 196 (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) 197 198 /* Timer registers are mapped as type 4 */ 199 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 200 #define KVM_REG_RISCV_TIMER_REG(name) \ 201 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 202 203 /* F extension registers are mapped as type 5 */ 204 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 205 #define KVM_REG_RISCV_FP_F_REG(name) \ 206 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 207 208 /* D extension registers are mapped as type 6 */ 209 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 210 #define KVM_REG_RISCV_FP_D_REG(name) \ 211 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 212 213 /* ISA Extension registers are mapped as type 7 */ 214 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 215 #define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 216 #define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 217 #define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 218 #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \ 219 ((__ext_id) / __BITS_PER_LONG) 220 #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \ 221 (1UL << ((__ext_id) % __BITS_PER_LONG)) 222 #define KVM_REG_RISCV_ISA_MULTI_REG_LAST \ 223 KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1) 224 225 /* SBI extension registers are mapped as type 8 */ 226 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 227 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 228 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 229 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 230 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ 231 ((__ext_id) / __BITS_PER_LONG) 232 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ 233 (1UL << ((__ext_id) % __BITS_PER_LONG)) 234 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ 235 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 236 237 /* V extension registers are mapped as type 9 */ 238 #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 239 #define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ 240 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 241 #define KVM_REG_RISCV_VECTOR_REG(n) \ 242 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 243 244 /* Device Control API: RISC-V AIA */ 245 #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 246 #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 247 #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 248 #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 249 #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 250 251 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 252 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 253 #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 254 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 255 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 256 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 257 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 258 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 259 260 /* 261 * Modes of RISC-V AIA device: 262 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC 263 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files 264 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever 265 * available otherwise fallback to trap-n-emulation 266 */ 267 #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 268 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 269 #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 270 271 #define KVM_DEV_RISCV_AIA_IDS_MIN 63 272 #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 273 #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 274 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 275 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 276 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 277 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 278 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 279 280 #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 281 #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 282 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 283 #define KVM_DEV_RISCV_AIA_ADDR_MAX \ 284 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 285 286 #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 287 #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 288 289 /* 290 * The device attribute type contains the memory mapped offset of the 291 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned. 292 */ 293 #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 294 295 /* 296 * The lower 12-bits of the device attribute type contains the iselect 297 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order 298 * bits contains the VCPU id. 299 */ 300 #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 301 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 302 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \ 303 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 304 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \ 305 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \ 306 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 307 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \ 308 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 309 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \ 310 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 311 312 /* One single KVM irqchip, ie. the AIA */ 313 #define KVM_NR_IRQCHIPS 1 314 315 #endif 316 317 #endif /* __LINUX_KVM_RISCV_H */ 318