1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20 #ifndef __LINUX_KVM_POWERPC_H 21 #define __LINUX_KVM_POWERPC_H 22 23 #include <linux/types.h> 24 25 /* Select powerpc specific features in <linux/kvm.h> */ 26 #define __KVM_HAVE_SPAPR_TCE 27 #define __KVM_HAVE_PPC_SMT 28 29 struct kvm_regs { 30 __u64 pc; 31 __u64 cr; 32 __u64 ctr; 33 __u64 lr; 34 __u64 xer; 35 __u64 msr; 36 __u64 srr0; 37 __u64 srr1; 38 __u64 pid; 39 40 __u64 sprg0; 41 __u64 sprg1; 42 __u64 sprg2; 43 __u64 sprg3; 44 __u64 sprg4; 45 __u64 sprg5; 46 __u64 sprg6; 47 __u64 sprg7; 48 49 __u64 gpr[32]; 50 }; 51 52 #define KVM_SREGS_E_IMPL_NONE 0 53 #define KVM_SREGS_E_IMPL_FSL 1 54 55 #define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */ 56 57 /* 58 * Feature bits indicate which sections of the sregs struct are valid, 59 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers 60 * corresponding to unset feature bits will not be modified. This allows 61 * restoring a checkpoint made without that feature, while keeping the 62 * default values of the new registers. 63 * 64 * KVM_SREGS_E_BASE contains: 65 * CSRR0/1 (refers to SRR2/3 on 40x) 66 * ESR 67 * DEAR 68 * MCSR 69 * TSR 70 * TCR 71 * DEC 72 * TB 73 * VRSAVE (USPRG0) 74 */ 75 #define KVM_SREGS_E_BASE (1 << 0) 76 77 /* 78 * KVM_SREGS_E_ARCH206 contains: 79 * 80 * PIR 81 * MCSRR0/1 82 * DECAR 83 * IVPR 84 */ 85 #define KVM_SREGS_E_ARCH206 (1 << 1) 86 87 /* 88 * Contains EPCR, plus the upper half of 64-bit registers 89 * that are 32-bit on 32-bit implementations. 90 */ 91 #define KVM_SREGS_E_64 (1 << 2) 92 93 #define KVM_SREGS_E_SPRG8 (1 << 3) 94 #define KVM_SREGS_E_MCIVPR (1 << 4) 95 96 /* 97 * IVORs are used -- contains IVOR0-15, plus additional IVORs 98 * in combination with an appropriate feature bit. 99 */ 100 #define KVM_SREGS_E_IVOR (1 << 5) 101 102 /* 103 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG. 104 * Also TLBnPS if MMUCFG[MAVN] = 1. 105 */ 106 #define KVM_SREGS_E_ARCH206_MMU (1 << 6) 107 108 /* DBSR, DBCR, IAC, DAC, DVC */ 109 #define KVM_SREGS_E_DEBUG (1 << 7) 110 111 /* Enhanced debug -- DSRR0/1, SPRG9 */ 112 #define KVM_SREGS_E_ED (1 << 8) 113 114 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */ 115 #define KVM_SREGS_E_SPE (1 << 9) 116 117 /* 118 * DEPRECATED! USE ONE_REG FOR THIS ONE! 119 * External Proxy (EXP) -- EPR 120 */ 121 #define KVM_SREGS_EXP (1 << 10) 122 123 /* External PID (E.PD) -- EPSC/EPLC */ 124 #define KVM_SREGS_E_PD (1 << 11) 125 126 /* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */ 127 #define KVM_SREGS_E_PC (1 << 12) 128 129 /* Page table (E.PT) -- EPTCFG */ 130 #define KVM_SREGS_E_PT (1 << 13) 131 132 /* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */ 133 #define KVM_SREGS_E_PM (1 << 14) 134 135 /* 136 * Special updates: 137 * 138 * Some registers may change even while a vcpu is not running. 139 * To avoid losing these changes, by default these registers are 140 * not updated by KVM_SET_SREGS. To force an update, set the bit 141 * in u.e.update_special corresponding to the register to be updated. 142 * 143 * The update_special field is zero on return from KVM_GET_SREGS. 144 * 145 * When restoring a checkpoint, the caller can set update_special 146 * to 0xffffffff to ensure that everything is restored, even new features 147 * that the caller doesn't know about. 148 */ 149 #define KVM_SREGS_E_UPDATE_MCSR (1 << 0) 150 #define KVM_SREGS_E_UPDATE_TSR (1 << 1) 151 #define KVM_SREGS_E_UPDATE_DEC (1 << 2) 152 #define KVM_SREGS_E_UPDATE_DBSR (1 << 3) 153 154 /* 155 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a 156 * previous KVM_GET_REGS. 157 * 158 * Unless otherwise indicated, setting any register with KVM_SET_SREGS 159 * directly sets its value. It does not trigger any special semantics such 160 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct 161 * just received from KVM_GET_SREGS is always a no-op. 162 */ 163 struct kvm_sregs { 164 __u32 pvr; 165 union { 166 struct { 167 __u64 sdr1; 168 struct { 169 struct { 170 __u64 slbe; 171 __u64 slbv; 172 } slb[64]; 173 } ppc64; 174 struct { 175 __u32 sr[16]; 176 __u64 ibat[8]; 177 __u64 dbat[8]; 178 } ppc32; 179 } s; 180 struct { 181 union { 182 struct { /* KVM_SREGS_E_IMPL_FSL */ 183 __u32 features; /* KVM_SREGS_E_FSL_ */ 184 __u32 svr; 185 __u64 mcar; 186 __u32 hid0; 187 188 /* KVM_SREGS_E_FSL_PIDn */ 189 __u32 pid1, pid2; 190 } fsl; 191 __u8 pad[256]; 192 } impl; 193 194 __u32 features; /* KVM_SREGS_E_ */ 195 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */ 196 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */ 197 __u32 pir; /* read-only */ 198 __u64 sprg8; 199 __u64 sprg9; /* E.ED */ 200 __u64 csrr0; 201 __u64 dsrr0; /* E.ED */ 202 __u64 mcsrr0; 203 __u32 csrr1; 204 __u32 dsrr1; /* E.ED */ 205 __u32 mcsrr1; 206 __u32 esr; 207 __u64 dear; 208 __u64 ivpr; 209 __u64 mcivpr; 210 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */ 211 212 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */ 213 __u32 tcr; 214 __u32 decar; 215 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */ 216 217 /* 218 * Userspace can read TB directly, but the 219 * value reported here is consistent with "dec". 220 * 221 * Read-only. 222 */ 223 __u64 tb; 224 225 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */ 226 __u32 dbcr[3]; 227 /* 228 * iac/dac registers are 64bit wide, while this API 229 * interface provides only lower 32 bits on 64 bit 230 * processors. ONE_REG interface is added for 64bit 231 * iac/dac registers. 232 */ 233 __u32 iac[4]; 234 __u32 dac[2]; 235 __u32 dvc[2]; 236 __u8 num_iac; /* read-only */ 237 __u8 num_dac; /* read-only */ 238 __u8 num_dvc; /* read-only */ 239 __u8 pad; 240 241 __u32 epr; /* EXP */ 242 __u32 vrsave; /* a.k.a. USPRG0 */ 243 __u32 epcr; /* KVM_SREGS_E_64 */ 244 245 __u32 mas0; 246 __u32 mas1; 247 __u64 mas2; 248 __u64 mas7_3; 249 __u32 mas4; 250 __u32 mas6; 251 252 __u32 ivor_low[16]; /* IVOR0-15 */ 253 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */ 254 255 __u32 mmucfg; /* read-only */ 256 __u32 eptcfg; /* E.PT, read-only */ 257 __u32 tlbcfg[4];/* read-only */ 258 __u32 tlbps[4]; /* read-only */ 259 260 __u32 eplc, epsc; /* E.PD */ 261 } e; 262 __u8 pad[1020]; 263 } u; 264 }; 265 266 struct kvm_fpu { 267 __u64 fpr[32]; 268 }; 269 270 struct kvm_debug_exit_arch { 271 }; 272 273 /* for KVM_SET_GUEST_DEBUG */ 274 struct kvm_guest_debug_arch { 275 }; 276 277 /* definition of registers in kvm_run */ 278 struct kvm_sync_regs { 279 }; 280 281 #define KVM_INTERRUPT_SET -1U 282 #define KVM_INTERRUPT_UNSET -2U 283 #define KVM_INTERRUPT_SET_LEVEL -3U 284 285 #define KVM_CPU_440 1 286 #define KVM_CPU_E500V2 2 287 #define KVM_CPU_3S_32 3 288 #define KVM_CPU_3S_64 4 289 #define KVM_CPU_E500MC 5 290 291 /* for KVM_CAP_SPAPR_TCE */ 292 struct kvm_create_spapr_tce { 293 __u64 liobn; 294 __u32 window_size; 295 }; 296 297 /* for KVM_ALLOCATE_RMA */ 298 struct kvm_allocate_rma { 299 __u64 rma_size; 300 }; 301 302 struct kvm_book3e_206_tlb_entry { 303 __u32 mas8; 304 __u32 mas1; 305 __u64 mas2; 306 __u64 mas7_3; 307 }; 308 309 struct kvm_book3e_206_tlb_params { 310 /* 311 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV: 312 * 313 * - The number of ways of TLB0 must be a power of two between 2 and 314 * 16. 315 * - TLB1 must be fully associative. 316 * - The size of TLB0 must be a multiple of the number of ways, and 317 * the number of sets must be a power of two. 318 * - The size of TLB1 may not exceed 64 entries. 319 * - TLB0 supports 4 KiB pages. 320 * - The page sizes supported by TLB1 are as indicated by 321 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1) 322 * as returned by KVM_GET_SREGS. 323 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[] 324 * and tlb_ways[] must be zero. 325 * 326 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative. 327 * 328 * KVM will adjust TLBnCFG based on the sizes configured here, 329 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY] 330 * set to zero. 331 */ 332 __u32 tlb_sizes[4]; 333 __u32 tlb_ways[4]; 334 __u32 reserved[8]; 335 }; 336 337 /* For KVM_PPC_GET_HTAB_FD */ 338 struct kvm_get_htab_fd { 339 __u64 flags; 340 __u64 start_index; 341 __u64 reserved[2]; 342 }; 343 344 /* Values for kvm_get_htab_fd.flags */ 345 #define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) 346 #define KVM_GET_HTAB_WRITE ((__u64)0x2) 347 348 /* 349 * Data read on the file descriptor is formatted as a series of 350 * records, each consisting of a header followed by a series of 351 * `n_valid' HPTEs (16 bytes each), which are all valid. Following 352 * those valid HPTEs there are `n_invalid' invalid HPTEs, which 353 * are not represented explicitly in the stream. The same format 354 * is used for writing. 355 */ 356 struct kvm_get_htab_header { 357 __u32 index; 358 __u16 n_valid; 359 __u16 n_invalid; 360 }; 361 362 #define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1) 363 #define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2) 364 #define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3) 365 #define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4) 366 #define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5) 367 #define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6) 368 #define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7) 369 #define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8) 370 #define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9) 371 #define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa) 372 #define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb) 373 #define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc) 374 #define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd) 375 #define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe) 376 #define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf) 377 378 #define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10) 379 #define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11) 380 #define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12) 381 382 #define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18) 383 #define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19) 384 #define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a) 385 #define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b) 386 #define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c) 387 #define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d) 388 #define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e) 389 #define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f) 390 391 /* 32 floating-point registers */ 392 #define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20) 393 #define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n)) 394 #define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f) 395 396 /* 32 VMX/Altivec vector registers */ 397 #define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40) 398 #define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n)) 399 #define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f) 400 401 /* 32 double-width FP registers for VSX */ 402 /* High-order halves overlap with FP regs */ 403 #define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60) 404 #define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n)) 405 #define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f) 406 407 /* FP and vector status/control registers */ 408 #define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) 409 #define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) 410 411 /* Virtual processor areas */ 412 /* For SLB & DTL, address in high (first) half, length in low half */ 413 #define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82) 414 #define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83) 415 #define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84) 416 417 #define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85) 418 #define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86) 419 420 /* Timer Status Register OR/CLEAR interface */ 421 #define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87) 422 #define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88) 423 #define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89) 424 #define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a) 425 #endif /* __LINUX_KVM_POWERPC_H */ 426