1 /*
2  * This program is free software; you can redistribute it and/or modify
3  * it under the terms of the GNU General Public License, version 2, as
4  * published by the Free Software Foundation.
5  *
6  * This program is distributed in the hope that it will be useful,
7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9  * GNU General Public License for more details.
10  *
11  * You should have received a copy of the GNU General Public License
12  * along with this program; if not, write to the Free Software
13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
14  *
15  * Copyright IBM Corp. 2007
16  *
17  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18  */
19 
20 #ifndef __LINUX_KVM_POWERPC_H
21 #define __LINUX_KVM_POWERPC_H
22 
23 #include <linux/types.h>
24 
25 /* Select powerpc specific features in <linux/kvm.h> */
26 #define __KVM_HAVE_SPAPR_TCE
27 #define __KVM_HAVE_PPC_SMT
28 #define __KVM_HAVE_IRQCHIP
29 #define __KVM_HAVE_IRQ_LINE
30 #define __KVM_HAVE_GUEST_DEBUG
31 
32 /* Not always available, but if it is, this is the correct offset.  */
33 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
34 
35 struct kvm_regs {
36 	__u64 pc;
37 	__u64 cr;
38 	__u64 ctr;
39 	__u64 lr;
40 	__u64 xer;
41 	__u64 msr;
42 	__u64 srr0;
43 	__u64 srr1;
44 	__u64 pid;
45 
46 	__u64 sprg0;
47 	__u64 sprg1;
48 	__u64 sprg2;
49 	__u64 sprg3;
50 	__u64 sprg4;
51 	__u64 sprg5;
52 	__u64 sprg6;
53 	__u64 sprg7;
54 
55 	__u64 gpr[32];
56 };
57 
58 #define KVM_SREGS_E_IMPL_NONE	0
59 #define KVM_SREGS_E_IMPL_FSL	1
60 
61 #define KVM_SREGS_E_FSL_PIDn	(1 << 0) /* PID1/PID2 */
62 
63 /* flags for kvm_run.flags */
64 #define KVM_RUN_PPC_NMI_DISP_MASK		(3 << 0)
65 #define   KVM_RUN_PPC_NMI_DISP_FULLY_RECOV	(1 << 0)
66 #define   KVM_RUN_PPC_NMI_DISP_LIMITED_RECOV	(2 << 0)
67 #define   KVM_RUN_PPC_NMI_DISP_NOT_RECOV	(3 << 0)
68 
69 /*
70  * Feature bits indicate which sections of the sregs struct are valid,
71  * both in KVM_GET_SREGS and KVM_SET_SREGS.  On KVM_SET_SREGS, registers
72  * corresponding to unset feature bits will not be modified.  This allows
73  * restoring a checkpoint made without that feature, while keeping the
74  * default values of the new registers.
75  *
76  * KVM_SREGS_E_BASE contains:
77  * CSRR0/1 (refers to SRR2/3 on 40x)
78  * ESR
79  * DEAR
80  * MCSR
81  * TSR
82  * TCR
83  * DEC
84  * TB
85  * VRSAVE (USPRG0)
86  */
87 #define KVM_SREGS_E_BASE		(1 << 0)
88 
89 /*
90  * KVM_SREGS_E_ARCH206 contains:
91  *
92  * PIR
93  * MCSRR0/1
94  * DECAR
95  * IVPR
96  */
97 #define KVM_SREGS_E_ARCH206		(1 << 1)
98 
99 /*
100  * Contains EPCR, plus the upper half of 64-bit registers
101  * that are 32-bit on 32-bit implementations.
102  */
103 #define KVM_SREGS_E_64			(1 << 2)
104 
105 #define KVM_SREGS_E_SPRG8		(1 << 3)
106 #define KVM_SREGS_E_MCIVPR		(1 << 4)
107 
108 /*
109  * IVORs are used -- contains IVOR0-15, plus additional IVORs
110  * in combination with an appropriate feature bit.
111  */
112 #define KVM_SREGS_E_IVOR		(1 << 5)
113 
114 /*
115  * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
116  * Also TLBnPS if MMUCFG[MAVN] = 1.
117  */
118 #define KVM_SREGS_E_ARCH206_MMU		(1 << 6)
119 
120 /* DBSR, DBCR, IAC, DAC, DVC */
121 #define KVM_SREGS_E_DEBUG		(1 << 7)
122 
123 /* Enhanced debug -- DSRR0/1, SPRG9 */
124 #define KVM_SREGS_E_ED			(1 << 8)
125 
126 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
127 #define KVM_SREGS_E_SPE			(1 << 9)
128 
129 /*
130  * DEPRECATED! USE ONE_REG FOR THIS ONE!
131  * External Proxy (EXP) -- EPR
132  */
133 #define KVM_SREGS_EXP			(1 << 10)
134 
135 /* External PID (E.PD) -- EPSC/EPLC */
136 #define KVM_SREGS_E_PD			(1 << 11)
137 
138 /* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
139 #define KVM_SREGS_E_PC			(1 << 12)
140 
141 /* Page table (E.PT) -- EPTCFG */
142 #define KVM_SREGS_E_PT			(1 << 13)
143 
144 /* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
145 #define KVM_SREGS_E_PM			(1 << 14)
146 
147 /*
148  * Special updates:
149  *
150  * Some registers may change even while a vcpu is not running.
151  * To avoid losing these changes, by default these registers are
152  * not updated by KVM_SET_SREGS.  To force an update, set the bit
153  * in u.e.update_special corresponding to the register to be updated.
154  *
155  * The update_special field is zero on return from KVM_GET_SREGS.
156  *
157  * When restoring a checkpoint, the caller can set update_special
158  * to 0xffffffff to ensure that everything is restored, even new features
159  * that the caller doesn't know about.
160  */
161 #define KVM_SREGS_E_UPDATE_MCSR		(1 << 0)
162 #define KVM_SREGS_E_UPDATE_TSR		(1 << 1)
163 #define KVM_SREGS_E_UPDATE_DEC		(1 << 2)
164 #define KVM_SREGS_E_UPDATE_DBSR		(1 << 3)
165 
166 /*
167  * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
168  * previous KVM_GET_REGS.
169  *
170  * Unless otherwise indicated, setting any register with KVM_SET_SREGS
171  * directly sets its value.  It does not trigger any special semantics such
172  * as write-one-to-clear.  Calling KVM_SET_SREGS on an unmodified struct
173  * just received from KVM_GET_SREGS is always a no-op.
174  */
175 struct kvm_sregs {
176 	__u32 pvr;
177 	union {
178 		struct {
179 			__u64 sdr1;
180 			struct {
181 				struct {
182 					__u64 slbe;
183 					__u64 slbv;
184 				} slb[64];
185 			} ppc64;
186 			struct {
187 				__u32 sr[16];
188 				__u64 ibat[8];
189 				__u64 dbat[8];
190 			} ppc32;
191 		} s;
192 		struct {
193 			union {
194 				struct { /* KVM_SREGS_E_IMPL_FSL */
195 					__u32 features; /* KVM_SREGS_E_FSL_ */
196 					__u32 svr;
197 					__u64 mcar;
198 					__u32 hid0;
199 
200 					/* KVM_SREGS_E_FSL_PIDn */
201 					__u32 pid1, pid2;
202 				} fsl;
203 				__u8 pad[256];
204 			} impl;
205 
206 			__u32 features; /* KVM_SREGS_E_ */
207 			__u32 impl_id;	/* KVM_SREGS_E_IMPL_ */
208 			__u32 update_special; /* KVM_SREGS_E_UPDATE_ */
209 			__u32 pir;	/* read-only */
210 			__u64 sprg8;
211 			__u64 sprg9;	/* E.ED */
212 			__u64 csrr0;
213 			__u64 dsrr0;	/* E.ED */
214 			__u64 mcsrr0;
215 			__u32 csrr1;
216 			__u32 dsrr1;	/* E.ED */
217 			__u32 mcsrr1;
218 			__u32 esr;
219 			__u64 dear;
220 			__u64 ivpr;
221 			__u64 mcivpr;
222 			__u64 mcsr;	/* KVM_SREGS_E_UPDATE_MCSR */
223 
224 			__u32 tsr;	/* KVM_SREGS_E_UPDATE_TSR */
225 			__u32 tcr;
226 			__u32 decar;
227 			__u32 dec;	/* KVM_SREGS_E_UPDATE_DEC */
228 
229 			/*
230 			 * Userspace can read TB directly, but the
231 			 * value reported here is consistent with "dec".
232 			 *
233 			 * Read-only.
234 			 */
235 			__u64 tb;
236 
237 			__u32 dbsr;	/* KVM_SREGS_E_UPDATE_DBSR */
238 			__u32 dbcr[3];
239 			/*
240 			 * iac/dac registers are 64bit wide, while this API
241 			 * interface provides only lower 32 bits on 64 bit
242 			 * processors. ONE_REG interface is added for 64bit
243 			 * iac/dac registers.
244 			 */
245 			__u32 iac[4];
246 			__u32 dac[2];
247 			__u32 dvc[2];
248 			__u8 num_iac;	/* read-only */
249 			__u8 num_dac;	/* read-only */
250 			__u8 num_dvc;	/* read-only */
251 			__u8 pad;
252 
253 			__u32 epr;	/* EXP */
254 			__u32 vrsave;	/* a.k.a. USPRG0 */
255 			__u32 epcr;	/* KVM_SREGS_E_64 */
256 
257 			__u32 mas0;
258 			__u32 mas1;
259 			__u64 mas2;
260 			__u64 mas7_3;
261 			__u32 mas4;
262 			__u32 mas6;
263 
264 			__u32 ivor_low[16]; /* IVOR0-15 */
265 			__u32 ivor_high[18]; /* IVOR32+, plus room to expand */
266 
267 			__u32 mmucfg;	/* read-only */
268 			__u32 eptcfg;	/* E.PT, read-only */
269 			__u32 tlbcfg[4];/* read-only */
270 			__u32 tlbps[4]; /* read-only */
271 
272 			__u32 eplc, epsc; /* E.PD */
273 		} e;
274 		__u8 pad[1020];
275 	} u;
276 };
277 
278 struct kvm_fpu {
279 	__u64 fpr[32];
280 };
281 
282 /*
283  * Defines for h/w breakpoint, watchpoint (read, write or both) and
284  * software breakpoint.
285  * These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status"
286  * for KVM_DEBUG_EXIT.
287  */
288 #define KVMPPC_DEBUG_NONE		0x0
289 #define KVMPPC_DEBUG_BREAKPOINT		(1UL << 1)
290 #define KVMPPC_DEBUG_WATCH_WRITE	(1UL << 2)
291 #define KVMPPC_DEBUG_WATCH_READ		(1UL << 3)
292 struct kvm_debug_exit_arch {
293 	__u64 address;
294 	/*
295 	 * exiting to userspace because of h/w breakpoint, watchpoint
296 	 * (read, write or both) and software breakpoint.
297 	 */
298 	__u32 status;
299 	__u32 reserved;
300 };
301 
302 /* for KVM_SET_GUEST_DEBUG */
303 struct kvm_guest_debug_arch {
304 	struct {
305 		/* H/W breakpoint/watchpoint address */
306 		__u64 addr;
307 		/*
308 		 * Type denotes h/w breakpoint, read watchpoint, write
309 		 * watchpoint or watchpoint (both read and write).
310 		 */
311 		__u32 type;
312 		__u32 reserved;
313 	} bp[16];
314 };
315 
316 /* Debug related defines */
317 /*
318  * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
319  * and upper 16 bits are architecture specific. Architecture specific defines
320  * that ioctl is for setting hardware breakpoint or software breakpoint.
321  */
322 #define KVM_GUESTDBG_USE_SW_BP		0x00010000
323 #define KVM_GUESTDBG_USE_HW_BP		0x00020000
324 
325 /* definition of registers in kvm_run */
326 struct kvm_sync_regs {
327 };
328 
329 #define KVM_INTERRUPT_SET	-1U
330 #define KVM_INTERRUPT_UNSET	-2U
331 #define KVM_INTERRUPT_SET_LEVEL	-3U
332 
333 #define KVM_CPU_440		1
334 #define KVM_CPU_E500V2		2
335 #define KVM_CPU_3S_32		3
336 #define KVM_CPU_3S_64		4
337 #define KVM_CPU_E500MC		5
338 
339 /* for KVM_CAP_SPAPR_TCE */
340 struct kvm_create_spapr_tce {
341 	__u64 liobn;
342 	__u32 window_size;
343 };
344 
345 /* for KVM_CAP_SPAPR_TCE_64 */
346 struct kvm_create_spapr_tce_64 {
347 	__u64 liobn;
348 	__u32 page_shift;
349 	__u32 flags;
350 	__u64 offset;	/* in pages */
351 	__u64 size;	/* in pages */
352 };
353 
354 /* for KVM_ALLOCATE_RMA */
355 struct kvm_allocate_rma {
356 	__u64 rma_size;
357 };
358 
359 /* for KVM_CAP_PPC_RTAS */
360 struct kvm_rtas_token_args {
361 	char name[120];
362 	__u64 token;	/* Use a token of 0 to undefine a mapping */
363 };
364 
365 struct kvm_book3e_206_tlb_entry {
366 	__u32 mas8;
367 	__u32 mas1;
368 	__u64 mas2;
369 	__u64 mas7_3;
370 };
371 
372 struct kvm_book3e_206_tlb_params {
373 	/*
374 	 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
375 	 *
376 	 * - The number of ways of TLB0 must be a power of two between 2 and
377 	 *   16.
378 	 * - TLB1 must be fully associative.
379 	 * - The size of TLB0 must be a multiple of the number of ways, and
380 	 *   the number of sets must be a power of two.
381 	 * - The size of TLB1 may not exceed 64 entries.
382 	 * - TLB0 supports 4 KiB pages.
383 	 * - The page sizes supported by TLB1 are as indicated by
384 	 *   TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
385 	 *   as returned by KVM_GET_SREGS.
386 	 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
387 	 *   and tlb_ways[] must be zero.
388 	 *
389 	 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
390 	 *
391 	 * KVM will adjust TLBnCFG based on the sizes configured here,
392 	 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
393 	 * set to zero.
394 	 */
395 	__u32 tlb_sizes[4];
396 	__u32 tlb_ways[4];
397 	__u32 reserved[8];
398 };
399 
400 /* For KVM_PPC_GET_HTAB_FD */
401 struct kvm_get_htab_fd {
402 	__u64	flags;
403 	__u64	start_index;
404 	__u64	reserved[2];
405 };
406 
407 /* Values for kvm_get_htab_fd.flags */
408 #define KVM_GET_HTAB_BOLTED_ONLY	((__u64)0x1)
409 #define KVM_GET_HTAB_WRITE		((__u64)0x2)
410 
411 /*
412  * Data read on the file descriptor is formatted as a series of
413  * records, each consisting of a header followed by a series of
414  * `n_valid' HPTEs (16 bytes each), which are all valid.  Following
415  * those valid HPTEs there are `n_invalid' invalid HPTEs, which
416  * are not represented explicitly in the stream.  The same format
417  * is used for writing.
418  */
419 struct kvm_get_htab_header {
420 	__u32	index;
421 	__u16	n_valid;
422 	__u16	n_invalid;
423 };
424 
425 /* For KVM_PPC_CONFIGURE_V3_MMU */
426 struct kvm_ppc_mmuv3_cfg {
427 	__u64	flags;
428 	__u64	process_table;	/* second doubleword of partition table entry */
429 };
430 
431 /* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
432 #define KVM_PPC_MMUV3_RADIX	1	/* 1 = radix mode, 0 = HPT */
433 #define KVM_PPC_MMUV3_GTSE	2	/* global translation shootdown enb. */
434 
435 /* For KVM_PPC_GET_RMMU_INFO */
436 struct kvm_ppc_rmmu_info {
437 	struct kvm_ppc_radix_geom {
438 		__u8	page_shift;
439 		__u8	level_bits[4];
440 		__u8	pad[3];
441 	}	geometries[8];
442 	__u32	ap_encodings[8];
443 };
444 
445 /* Per-vcpu XICS interrupt controller state */
446 #define KVM_REG_PPC_ICP_STATE	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
447 
448 #define  KVM_REG_PPC_ICP_CPPR_SHIFT	56	/* current proc priority */
449 #define  KVM_REG_PPC_ICP_CPPR_MASK	0xff
450 #define  KVM_REG_PPC_ICP_XISR_SHIFT	32	/* interrupt status field */
451 #define  KVM_REG_PPC_ICP_XISR_MASK	0xffffff
452 #define  KVM_REG_PPC_ICP_MFRR_SHIFT	24	/* pending IPI priority */
453 #define  KVM_REG_PPC_ICP_MFRR_MASK	0xff
454 #define  KVM_REG_PPC_ICP_PPRI_SHIFT	16	/* pending irq priority */
455 #define  KVM_REG_PPC_ICP_PPRI_MASK	0xff
456 
457 /* Device control API: PPC-specific devices */
458 #define KVM_DEV_MPIC_GRP_MISC		1
459 #define   KVM_DEV_MPIC_BASE_ADDR	0	/* 64-bit */
460 
461 #define KVM_DEV_MPIC_GRP_REGISTER	2	/* 32-bit */
462 #define KVM_DEV_MPIC_GRP_IRQ_ACTIVE	3	/* 32-bit */
463 
464 /* One-Reg API: PPC-specific registers */
465 #define KVM_REG_PPC_HIOR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
466 #define KVM_REG_PPC_IAC1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
467 #define KVM_REG_PPC_IAC2	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
468 #define KVM_REG_PPC_IAC3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4)
469 #define KVM_REG_PPC_IAC4	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5)
470 #define KVM_REG_PPC_DAC1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6)
471 #define KVM_REG_PPC_DAC2	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7)
472 #define KVM_REG_PPC_DABR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8)
473 #define KVM_REG_PPC_DSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9)
474 #define KVM_REG_PPC_PURR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa)
475 #define KVM_REG_PPC_SPURR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb)
476 #define KVM_REG_PPC_DAR		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc)
477 #define KVM_REG_PPC_DSISR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd)
478 #define KVM_REG_PPC_AMR		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe)
479 #define KVM_REG_PPC_UAMOR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf)
480 
481 #define KVM_REG_PPC_MMCR0	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
482 #define KVM_REG_PPC_MMCR1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
483 #define KVM_REG_PPC_MMCRA	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
484 #define KVM_REG_PPC_MMCR2	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
485 #define KVM_REG_PPC_MMCRS	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14)
486 #define KVM_REG_PPC_SIAR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15)
487 #define KVM_REG_PPC_SDAR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16)
488 #define KVM_REG_PPC_SIER	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17)
489 
490 #define KVM_REG_PPC_PMC1	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
491 #define KVM_REG_PPC_PMC2	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
492 #define KVM_REG_PPC_PMC3	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a)
493 #define KVM_REG_PPC_PMC4	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b)
494 #define KVM_REG_PPC_PMC5	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c)
495 #define KVM_REG_PPC_PMC6	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d)
496 #define KVM_REG_PPC_PMC7	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e)
497 #define KVM_REG_PPC_PMC8	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f)
498 
499 /* 32 floating-point registers */
500 #define KVM_REG_PPC_FPR0	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20)
501 #define KVM_REG_PPC_FPR(n)	(KVM_REG_PPC_FPR0 + (n))
502 #define KVM_REG_PPC_FPR31	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f)
503 
504 /* 32 VMX/Altivec vector registers */
505 #define KVM_REG_PPC_VR0		(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40)
506 #define KVM_REG_PPC_VR(n)	(KVM_REG_PPC_VR0 + (n))
507 #define KVM_REG_PPC_VR31	(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f)
508 
509 /* 32 double-width FP registers for VSX */
510 /* High-order halves overlap with FP regs */
511 #define KVM_REG_PPC_VSR0	(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60)
512 #define KVM_REG_PPC_VSR(n)	(KVM_REG_PPC_VSR0 + (n))
513 #define KVM_REG_PPC_VSR31	(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f)
514 
515 /* FP and vector status/control registers */
516 #define KVM_REG_PPC_FPSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
517 /*
518  * VSCR register is documented as a 32-bit register in the ISA, but it can
519  * only be accesses via a vector register. Expose VSCR as a 32-bit register
520  * even though the kernel represents it as a 128-bit vector.
521  */
522 #define KVM_REG_PPC_VSCR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
523 
524 /* Virtual processor areas */
525 /* For SLB & DTL, address in high (first) half, length in low half */
526 #define KVM_REG_PPC_VPA_ADDR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
527 #define KVM_REG_PPC_VPA_SLB	(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
528 #define KVM_REG_PPC_VPA_DTL	(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
529 
530 #define KVM_REG_PPC_EPCR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
531 #define KVM_REG_PPC_EPR		(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
532 
533 /* Timer Status Register OR/CLEAR interface */
534 #define KVM_REG_PPC_OR_TSR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
535 #define KVM_REG_PPC_CLEAR_TSR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
536 #define KVM_REG_PPC_TCR		(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
537 #define KVM_REG_PPC_TSR		(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
538 
539 /* Debugging: Special instruction for software breakpoint */
540 #define KVM_REG_PPC_DEBUG_INST	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
541 
542 /* MMU registers */
543 #define KVM_REG_PPC_MAS0	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
544 #define KVM_REG_PPC_MAS1	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
545 #define KVM_REG_PPC_MAS2	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
546 #define KVM_REG_PPC_MAS7_3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
547 #define KVM_REG_PPC_MAS4	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
548 #define KVM_REG_PPC_MAS6	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
549 #define KVM_REG_PPC_MMUCFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
550 /*
551  * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
552  * KVM_CAP_SW_TLB ioctl
553  */
554 #define KVM_REG_PPC_TLB0CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
555 #define KVM_REG_PPC_TLB1CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
556 #define KVM_REG_PPC_TLB2CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
557 #define KVM_REG_PPC_TLB3CFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
558 #define KVM_REG_PPC_TLB0PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
559 #define KVM_REG_PPC_TLB1PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
560 #define KVM_REG_PPC_TLB2PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
561 #define KVM_REG_PPC_TLB3PS	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
562 #define KVM_REG_PPC_EPTCFG	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
563 
564 /* Timebase offset */
565 #define KVM_REG_PPC_TB_OFFSET	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c)
566 
567 /* POWER8 registers */
568 #define KVM_REG_PPC_SPMC1	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d)
569 #define KVM_REG_PPC_SPMC2	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e)
570 #define KVM_REG_PPC_IAMR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f)
571 #define KVM_REG_PPC_TFHAR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0)
572 #define KVM_REG_PPC_TFIAR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1)
573 #define KVM_REG_PPC_TEXASR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2)
574 #define KVM_REG_PPC_FSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3)
575 #define KVM_REG_PPC_PSPB	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4)
576 #define KVM_REG_PPC_EBBHR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5)
577 #define KVM_REG_PPC_EBBRR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6)
578 #define KVM_REG_PPC_BESCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7)
579 #define KVM_REG_PPC_TAR		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8)
580 #define KVM_REG_PPC_DPDES	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9)
581 #define KVM_REG_PPC_DAWR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa)
582 #define KVM_REG_PPC_DAWRX	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab)
583 #define KVM_REG_PPC_CIABR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac)
584 #define KVM_REG_PPC_IC		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad)
585 #define KVM_REG_PPC_VTB		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae)
586 #define KVM_REG_PPC_CSIGR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf)
587 #define KVM_REG_PPC_TACR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0)
588 #define KVM_REG_PPC_TCSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
589 #define KVM_REG_PPC_PID		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
590 #define KVM_REG_PPC_ACOP	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
591 
592 #define KVM_REG_PPC_VRSAVE	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
593 #define KVM_REG_PPC_LPCR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
594 #define KVM_REG_PPC_LPCR_64	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5)
595 #define KVM_REG_PPC_PPR		(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6)
596 
597 /* Architecture compatibility level */
598 #define KVM_REG_PPC_ARCH_COMPAT	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
599 
600 #define KVM_REG_PPC_DABRX	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
601 #define KVM_REG_PPC_WORT	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9)
602 #define KVM_REG_PPC_SPRG9	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
603 #define KVM_REG_PPC_DBSR	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
604 
605 /* POWER9 registers */
606 #define KVM_REG_PPC_TIDR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
607 #define KVM_REG_PPC_PSSCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
608 
609 /* Transactional Memory checkpointed state:
610  * This is all GPRs, all VSX regs and a subset of SPRs
611  */
612 #define KVM_REG_PPC_TM		(KVM_REG_PPC | 0x80000000)
613 /* TM GPRs */
614 #define KVM_REG_PPC_TM_GPR0	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0)
615 #define KVM_REG_PPC_TM_GPR(n)	(KVM_REG_PPC_TM_GPR0 + (n))
616 #define KVM_REG_PPC_TM_GPR31	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f)
617 /* TM VSX */
618 #define KVM_REG_PPC_TM_VSR0	(KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20)
619 #define KVM_REG_PPC_TM_VSR(n)	(KVM_REG_PPC_TM_VSR0 + (n))
620 #define KVM_REG_PPC_TM_VSR63	(KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f)
621 /* TM SPRS */
622 #define KVM_REG_PPC_TM_CR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60)
623 #define KVM_REG_PPC_TM_LR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61)
624 #define KVM_REG_PPC_TM_CTR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62)
625 #define KVM_REG_PPC_TM_FPSCR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63)
626 #define KVM_REG_PPC_TM_AMR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64)
627 #define KVM_REG_PPC_TM_PPR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65)
628 #define KVM_REG_PPC_TM_VRSAVE	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66)
629 #define KVM_REG_PPC_TM_VSCR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
630 #define KVM_REG_PPC_TM_DSCR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
631 #define KVM_REG_PPC_TM_TAR	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
632 #define KVM_REG_PPC_TM_XER	(KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
633 
634 /* PPC64 eXternal Interrupt Controller Specification */
635 #define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */
636 
637 /* Layout of 64-bit source attribute values */
638 #define  KVM_XICS_DESTINATION_SHIFT	0
639 #define  KVM_XICS_DESTINATION_MASK	0xffffffffULL
640 #define  KVM_XICS_PRIORITY_SHIFT	32
641 #define  KVM_XICS_PRIORITY_MASK		0xff
642 #define  KVM_XICS_LEVEL_SENSITIVE	(1ULL << 40)
643 #define  KVM_XICS_MASKED		(1ULL << 41)
644 #define  KVM_XICS_PENDING		(1ULL << 42)
645 #define  KVM_XICS_PRESENTED		(1ULL << 43)
646 #define  KVM_XICS_QUEUED		(1ULL << 44)
647 
648 #endif /* __LINUX_KVM_POWERPC_H */
649