1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __ARM_KVM_H__ 24 #define __ARM_KVM_H__ 25 26 #define KVM_SPSR_EL1 0 27 #define KVM_SPSR_SVC KVM_SPSR_EL1 28 #define KVM_SPSR_ABT 1 29 #define KVM_SPSR_UND 2 30 #define KVM_SPSR_IRQ 3 31 #define KVM_SPSR_FIQ 4 32 #define KVM_NR_SPSR 5 33 34 #ifndef __ASSEMBLY__ 35 #include <linux/psci.h> 36 #include <linux/types.h> 37 #include <asm/ptrace.h> 38 #include <asm/sve_context.h> 39 40 #define __KVM_HAVE_GUEST_DEBUG 41 #define __KVM_HAVE_IRQ_LINE 42 #define __KVM_HAVE_READONLY_MEM 43 #define __KVM_HAVE_VCPU_EVENTS 44 45 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 46 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 47 48 #define KVM_REG_SIZE(id) \ 49 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 50 51 struct kvm_regs { 52 struct user_pt_regs regs; /* sp = sp_el0 */ 53 54 __u64 sp_el1; 55 __u64 elr_el1; 56 57 __u64 spsr[KVM_NR_SPSR]; 58 59 struct user_fpsimd_state fp_regs; 60 }; 61 62 /* 63 * Supported CPU Targets - Adding a new target type is not recommended, 64 * unless there are some special registers not supported by the 65 * genericv8 syreg table. 66 */ 67 #define KVM_ARM_TARGET_AEM_V8 0 68 #define KVM_ARM_TARGET_FOUNDATION_V8 1 69 #define KVM_ARM_TARGET_CORTEX_A57 2 70 #define KVM_ARM_TARGET_XGENE_POTENZA 3 71 #define KVM_ARM_TARGET_CORTEX_A53 4 72 /* Generic ARM v8 target */ 73 #define KVM_ARM_TARGET_GENERIC_V8 5 74 75 #define KVM_ARM_NUM_TARGETS 6 76 77 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 78 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 79 #define KVM_ARM_DEVICE_TYPE_MASK GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ 80 KVM_ARM_DEVICE_TYPE_SHIFT) 81 #define KVM_ARM_DEVICE_ID_SHIFT 16 82 #define KVM_ARM_DEVICE_ID_MASK GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ 83 KVM_ARM_DEVICE_ID_SHIFT) 84 85 /* Supported device IDs */ 86 #define KVM_ARM_DEVICE_VGIC_V2 0 87 88 /* Supported VGIC address types */ 89 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 90 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 91 92 #define KVM_VGIC_V2_DIST_SIZE 0x1000 93 #define KVM_VGIC_V2_CPU_SIZE 0x2000 94 95 /* Supported VGICv3 address types */ 96 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 97 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 98 #define KVM_VGIC_ITS_ADDR_TYPE 4 99 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 100 101 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 102 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 103 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 104 105 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 106 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 107 #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 108 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 109 #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 110 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 111 #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 112 #define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ 113 114 struct kvm_vcpu_init { 115 __u32 target; 116 __u32 features[7]; 117 }; 118 119 struct kvm_sregs { 120 }; 121 122 struct kvm_fpu { 123 }; 124 125 /* 126 * See v8 ARM ARM D7.3: Debug Registers 127 * 128 * The architectural limit is 16 debug registers of each type although 129 * in practice there are usually less (see ID_AA64DFR0_EL1). 130 * 131 * Although the control registers are architecturally defined as 32 132 * bits wide we use a 64 bit structure here to keep parity with 133 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 134 * 64 bit values. It also allows for the possibility of the 135 * architecture expanding the control registers without having to 136 * change the userspace ABI. 137 */ 138 #define KVM_ARM_MAX_DBG_REGS 16 139 struct kvm_guest_debug_arch { 140 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 141 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 142 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 143 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 144 }; 145 146 #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 147 struct kvm_debug_exit_arch { 148 __u32 hsr; 149 __u32 hsr_high; /* ESR_EL2[61:32] */ 150 __u64 far; /* used for watchpoints */ 151 }; 152 153 /* 154 * Architecture specific defines for kvm_guest_debug->control 155 */ 156 157 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 158 #define KVM_GUESTDBG_USE_HW (1 << 17) 159 160 struct kvm_sync_regs { 161 /* Used with KVM_CAP_ARM_USER_IRQ */ 162 __u64 device_irq_level; 163 }; 164 165 /* 166 * PMU filter structure. Describe a range of events with a particular 167 * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER. 168 */ 169 struct kvm_pmu_event_filter { 170 __u16 base_event; 171 __u16 nevents; 172 173 #define KVM_PMU_EVENT_ALLOW 0 174 #define KVM_PMU_EVENT_DENY 1 175 176 __u8 action; 177 __u8 pad[3]; 178 }; 179 180 /* for KVM_GET/SET_VCPU_EVENTS */ 181 struct kvm_vcpu_events { 182 struct { 183 __u8 serror_pending; 184 __u8 serror_has_esr; 185 __u8 ext_dabt_pending; 186 /* Align it to 8 bytes */ 187 __u8 pad[5]; 188 __u64 serror_esr; 189 } exception; 190 __u32 reserved[12]; 191 }; 192 193 struct kvm_arm_copy_mte_tags { 194 __u64 guest_ipa; 195 __u64 length; 196 void *addr; 197 __u64 flags; 198 __u64 reserved[2]; 199 }; 200 201 /* 202 * Counter/Timer offset structure. Describe the virtual/physical offset. 203 * To be used with KVM_ARM_SET_COUNTER_OFFSET. 204 */ 205 struct kvm_arm_counter_offset { 206 __u64 counter_offset; 207 __u64 reserved; 208 }; 209 210 #define KVM_ARM_TAGS_TO_GUEST 0 211 #define KVM_ARM_TAGS_FROM_GUEST 1 212 213 /* If you need to interpret the index values, here is the key: */ 214 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 215 #define KVM_REG_ARM_COPROC_SHIFT 16 216 217 /* Normal registers are mapped as coprocessor 16. */ 218 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 219 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 220 221 /* Some registers need more space to represent values. */ 222 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 223 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 224 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 225 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 226 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 227 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 228 229 /* AArch64 system registers */ 230 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 231 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 232 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 233 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 234 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 235 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 236 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 237 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 238 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 239 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 240 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 241 242 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 243 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 244 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 245 246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 247 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 248 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 249 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 250 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 251 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 252 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 253 254 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 255 256 /* Physical Timer EL0 Registers */ 257 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 258 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 259 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 260 261 /* 262 * EL0 Virtual Timer Registers 263 * 264 * WARNING: 265 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 266 * with the appropriate register encodings. Their values have been 267 * accidentally swapped. As this is set API, the definitions here 268 * must be used, rather than ones derived from the encodings. 269 */ 270 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 271 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 272 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 273 274 /* KVM-as-firmware specific pseudo-registers */ 275 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 276 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 277 KVM_REG_ARM_FW | ((r) & 0xffff)) 278 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 279 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 280 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 281 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 282 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 283 284 /* 285 * Only two states can be presented by the host kernel: 286 * - NOT_REQUIRED: the guest doesn't need to do anything 287 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available) 288 * 289 * All the other values are deprecated. The host still accepts all 290 * values (they are ABI), but will narrow them to the above two. 291 */ 292 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 293 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 294 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 295 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 296 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 297 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 298 299 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 300 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 301 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 302 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 303 304 /* SVE registers */ 305 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 306 307 /* Z- and P-regs occupy blocks at the following offsets within this range: */ 308 #define KVM_REG_ARM64_SVE_ZREG_BASE 0 309 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 310 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 311 312 #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 313 #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 314 315 #define KVM_ARM64_SVE_MAX_SLICES 32 316 317 #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 318 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 319 KVM_REG_SIZE_U2048 | \ 320 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 321 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 322 323 #define KVM_REG_ARM64_SVE_PREG(n, i) \ 324 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 325 KVM_REG_SIZE_U256 | \ 326 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 327 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 328 329 #define KVM_REG_ARM64_SVE_FFR(i) \ 330 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 331 KVM_REG_SIZE_U256 | \ 332 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 333 334 /* 335 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 336 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 337 * invariant layout which differs from the layout used for the FPSIMD 338 * V-registers on big-endian systems: see sigcontext.h for more explanation. 339 */ 340 341 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 342 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 343 344 /* Vector lengths pseudo-register: */ 345 #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 346 KVM_REG_SIZE_U512 | 0xffff) 347 #define KVM_ARM64_SVE_VLS_WORDS \ 348 ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 349 350 /* Bitmap feature firmware registers */ 351 #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 352 #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 353 KVM_REG_ARM_FW_FEAT_BMAP | \ 354 ((r) & 0xffff)) 355 356 #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 357 358 enum { 359 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 360 }; 361 362 #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 363 364 enum { 365 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 366 }; 367 368 #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 369 370 enum { 371 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 372 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 373 }; 374 375 /* Device Control API on vm fd */ 376 #define KVM_ARM_VM_SMCCC_CTRL 0 377 #define KVM_ARM_VM_SMCCC_FILTER 0 378 379 /* Device Control API: ARM VGIC */ 380 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 381 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 382 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 383 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 384 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 385 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 386 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 387 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 388 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 389 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 390 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 391 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 392 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 393 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 394 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 395 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 396 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 397 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 398 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 399 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 400 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 401 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 402 403 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 404 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 405 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 406 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 407 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 408 409 /* Device Control API on vcpu fd */ 410 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 411 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 412 #define KVM_ARM_VCPU_PMU_V3_INIT 1 413 #define KVM_ARM_VCPU_PMU_V3_FILTER 2 414 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 415 #define KVM_ARM_VCPU_TIMER_CTRL 1 416 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 417 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 418 #define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 419 #define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 420 #define KVM_ARM_VCPU_PVTIME_CTRL 2 421 #define KVM_ARM_VCPU_PVTIME_IPA 0 422 423 /* KVM_IRQ_LINE irq field index values */ 424 #define KVM_ARM_IRQ_VCPU2_SHIFT 28 425 #define KVM_ARM_IRQ_VCPU2_MASK 0xf 426 #define KVM_ARM_IRQ_TYPE_SHIFT 24 427 #define KVM_ARM_IRQ_TYPE_MASK 0xf 428 #define KVM_ARM_IRQ_VCPU_SHIFT 16 429 #define KVM_ARM_IRQ_VCPU_MASK 0xff 430 #define KVM_ARM_IRQ_NUM_SHIFT 0 431 #define KVM_ARM_IRQ_NUM_MASK 0xffff 432 433 /* irq_type field */ 434 #define KVM_ARM_IRQ_TYPE_CPU 0 435 #define KVM_ARM_IRQ_TYPE_SPI 1 436 #define KVM_ARM_IRQ_TYPE_PPI 2 437 438 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 439 #define KVM_ARM_IRQ_CPU_IRQ 0 440 #define KVM_ARM_IRQ_CPU_FIQ 1 441 442 /* 443 * This used to hold the highest supported SPI, but it is now obsolete 444 * and only here to provide source code level compatibility with older 445 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 446 */ 447 #define KVM_ARM_IRQ_GIC_MAX 127 448 449 /* One single KVM irqchip, ie. the VGIC */ 450 #define KVM_NR_IRQCHIPS 1 451 452 /* PSCI interface */ 453 #define KVM_PSCI_FN_BASE 0x95c1ba5e 454 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 455 456 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 457 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 458 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 459 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 460 461 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 462 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 463 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 464 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 465 466 /* arm64-specific kvm_run::system_event flags */ 467 /* 468 * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call. 469 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET. 470 */ 471 #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 472 473 /* run->fail_entry.hardware_entry_failure_reason codes. */ 474 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 475 476 enum kvm_smccc_filter_action { 477 KVM_SMCCC_FILTER_HANDLE = 0, 478 KVM_SMCCC_FILTER_DENY, 479 KVM_SMCCC_FILTER_FWD_TO_USER, 480 481 }; 482 483 struct kvm_smccc_filter { 484 __u32 base; 485 __u32 nr_functions; 486 __u8 action; 487 __u8 pad[15]; 488 }; 489 490 /* arm64-specific KVM_EXIT_HYPERCALL flags */ 491 #define KVM_HYPERCALL_EXIT_SMC (1U << 0) 492 #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) 493 494 /* 495 * Get feature ID registers userspace writable mask. 496 * 497 * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model 498 * Feature Register 2"): 499 * 500 * "The Feature ID space is defined as the System register space in 501 * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, 502 * op2=={0-7}." 503 * 504 * This covers all currently known R/O registers that indicate 505 * anything useful feature wise, including the ID registers. 506 * 507 * If we ever need to introduce a new range, it will be described as 508 * such in the range field. 509 */ 510 #define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ 511 ({ \ 512 __u64 __op1 = (op1) & 3; \ 513 __op1 -= (__op1 == 3); \ 514 (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ 515 }) 516 517 #define KVM_ARM_FEATURE_ID_RANGE 0 518 #define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) 519 520 struct reg_mask_range { 521 __u64 addr; /* Pointer to mask array */ 522 __u32 range; /* Requested range */ 523 __u32 reserved[13]; 524 }; 525 526 #endif 527 528 #endif /* __ARM_KVM_H__ */ 529