1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __ARM_KVM_H__ 24 #define __ARM_KVM_H__ 25 26 #define KVM_SPSR_EL1 0 27 #define KVM_SPSR_SVC KVM_SPSR_EL1 28 #define KVM_SPSR_ABT 1 29 #define KVM_SPSR_UND 2 30 #define KVM_SPSR_IRQ 3 31 #define KVM_SPSR_FIQ 4 32 #define KVM_NR_SPSR 5 33 34 #ifndef __ASSEMBLY__ 35 #include <linux/psci.h> 36 #include <linux/types.h> 37 #include <asm/ptrace.h> 38 #include <asm/sve_context.h> 39 40 #define __KVM_HAVE_GUEST_DEBUG 41 #define __KVM_HAVE_IRQ_LINE 42 #define __KVM_HAVE_READONLY_MEM 43 #define __KVM_HAVE_VCPU_EVENTS 44 45 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 46 47 #define KVM_REG_SIZE(id) \ 48 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 49 50 struct kvm_regs { 51 struct user_pt_regs regs; /* sp = sp_el0 */ 52 53 __u64 sp_el1; 54 __u64 elr_el1; 55 56 __u64 spsr[KVM_NR_SPSR]; 57 58 struct user_fpsimd_state fp_regs; 59 }; 60 61 /* 62 * Supported CPU Targets - Adding a new target type is not recommended, 63 * unless there are some special registers not supported by the 64 * genericv8 syreg table. 65 */ 66 #define KVM_ARM_TARGET_AEM_V8 0 67 #define KVM_ARM_TARGET_FOUNDATION_V8 1 68 #define KVM_ARM_TARGET_CORTEX_A57 2 69 #define KVM_ARM_TARGET_XGENE_POTENZA 3 70 #define KVM_ARM_TARGET_CORTEX_A53 4 71 /* Generic ARM v8 target */ 72 #define KVM_ARM_TARGET_GENERIC_V8 5 73 74 #define KVM_ARM_NUM_TARGETS 6 75 76 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 77 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 78 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 79 #define KVM_ARM_DEVICE_ID_SHIFT 16 80 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 81 82 /* Supported device IDs */ 83 #define KVM_ARM_DEVICE_VGIC_V2 0 84 85 /* Supported VGIC address types */ 86 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 87 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 88 89 #define KVM_VGIC_V2_DIST_SIZE 0x1000 90 #define KVM_VGIC_V2_CPU_SIZE 0x2000 91 92 /* Supported VGICv3 address types */ 93 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 94 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 95 #define KVM_VGIC_ITS_ADDR_TYPE 4 96 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 97 98 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 99 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 100 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 101 102 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 103 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 104 #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 105 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 106 #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 107 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 108 #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 109 110 struct kvm_vcpu_init { 111 __u32 target; 112 __u32 features[7]; 113 }; 114 115 struct kvm_sregs { 116 }; 117 118 struct kvm_fpu { 119 }; 120 121 /* 122 * See v8 ARM ARM D7.3: Debug Registers 123 * 124 * The architectural limit is 16 debug registers of each type although 125 * in practice there are usually less (see ID_AA64DFR0_EL1). 126 * 127 * Although the control registers are architecturally defined as 32 128 * bits wide we use a 64 bit structure here to keep parity with 129 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 130 * 64 bit values. It also allows for the possibility of the 131 * architecture expanding the control registers without having to 132 * change the userspace ABI. 133 */ 134 #define KVM_ARM_MAX_DBG_REGS 16 135 struct kvm_guest_debug_arch { 136 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 137 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 138 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 139 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 140 }; 141 142 struct kvm_debug_exit_arch { 143 __u32 hsr; 144 __u64 far; /* used for watchpoints */ 145 }; 146 147 /* 148 * Architecture specific defines for kvm_guest_debug->control 149 */ 150 151 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 152 #define KVM_GUESTDBG_USE_HW (1 << 17) 153 154 struct kvm_sync_regs { 155 /* Used with KVM_CAP_ARM_USER_IRQ */ 156 __u64 device_irq_level; 157 }; 158 159 struct kvm_arch_memory_slot { 160 }; 161 162 /* for KVM_GET/SET_VCPU_EVENTS */ 163 struct kvm_vcpu_events { 164 struct { 165 __u8 serror_pending; 166 __u8 serror_has_esr; 167 /* Align it to 8 bytes */ 168 __u8 pad[6]; 169 __u64 serror_esr; 170 } exception; 171 __u32 reserved[12]; 172 }; 173 174 /* If you need to interpret the index values, here is the key: */ 175 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 176 #define KVM_REG_ARM_COPROC_SHIFT 16 177 178 /* Normal registers are mapped as coprocessor 16. */ 179 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 180 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 181 182 /* Some registers need more space to represent values. */ 183 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 184 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 185 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 186 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 187 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 188 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 189 190 /* AArch64 system registers */ 191 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 192 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 193 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 194 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 195 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 196 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 197 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 198 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 199 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 200 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 201 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 202 203 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 204 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 205 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 206 207 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 208 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 209 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 210 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 211 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 212 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 213 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 214 215 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 216 217 /* Physical Timer EL0 Registers */ 218 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 219 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 220 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 221 222 /* EL0 Virtual Timer Registers */ 223 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 224 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 225 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 226 227 /* KVM-as-firmware specific pseudo-registers */ 228 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 229 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 230 KVM_REG_ARM_FW | ((r) & 0xffff)) 231 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 232 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 233 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 234 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 235 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 236 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 237 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 238 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 239 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 240 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 241 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 242 243 /* SVE registers */ 244 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 245 246 /* Z- and P-regs occupy blocks at the following offsets within this range: */ 247 #define KVM_REG_ARM64_SVE_ZREG_BASE 0 248 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 249 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 250 251 #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 252 #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 253 254 #define KVM_ARM64_SVE_MAX_SLICES 32 255 256 #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 257 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 258 KVM_REG_SIZE_U2048 | \ 259 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 260 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 261 262 #define KVM_REG_ARM64_SVE_PREG(n, i) \ 263 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 264 KVM_REG_SIZE_U256 | \ 265 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 266 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 267 268 #define KVM_REG_ARM64_SVE_FFR(i) \ 269 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 270 KVM_REG_SIZE_U256 | \ 271 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 272 273 /* 274 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 275 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 276 * invariant layout which differs from the layout used for the FPSIMD 277 * V-registers on big-endian systems: see sigcontext.h for more explanation. 278 */ 279 280 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 281 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 282 283 /* Vector lengths pseudo-register: */ 284 #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 285 KVM_REG_SIZE_U512 | 0xffff) 286 #define KVM_ARM64_SVE_VLS_WORDS \ 287 ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 288 289 /* Device Control API: ARM VGIC */ 290 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 291 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 292 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 293 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 294 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 295 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 296 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 297 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 298 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 299 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 300 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 301 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 302 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 303 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 304 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 305 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 306 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 307 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 308 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 309 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 310 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 311 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 312 313 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 314 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 315 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 316 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 317 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 318 319 /* Device Control API on vcpu fd */ 320 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 321 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 322 #define KVM_ARM_VCPU_PMU_V3_INIT 1 323 #define KVM_ARM_VCPU_TIMER_CTRL 1 324 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 325 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 326 327 /* KVM_IRQ_LINE irq field index values */ 328 #define KVM_ARM_IRQ_VCPU2_SHIFT 28 329 #define KVM_ARM_IRQ_VCPU2_MASK 0xf 330 #define KVM_ARM_IRQ_TYPE_SHIFT 24 331 #define KVM_ARM_IRQ_TYPE_MASK 0xf 332 #define KVM_ARM_IRQ_VCPU_SHIFT 16 333 #define KVM_ARM_IRQ_VCPU_MASK 0xff 334 #define KVM_ARM_IRQ_NUM_SHIFT 0 335 #define KVM_ARM_IRQ_NUM_MASK 0xffff 336 337 /* irq_type field */ 338 #define KVM_ARM_IRQ_TYPE_CPU 0 339 #define KVM_ARM_IRQ_TYPE_SPI 1 340 #define KVM_ARM_IRQ_TYPE_PPI 2 341 342 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 343 #define KVM_ARM_IRQ_CPU_IRQ 0 344 #define KVM_ARM_IRQ_CPU_FIQ 1 345 346 /* 347 * This used to hold the highest supported SPI, but it is now obsolete 348 * and only here to provide source code level compatibility with older 349 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 350 */ 351 #define KVM_ARM_IRQ_GIC_MAX 127 352 353 /* One single KVM irqchip, ie. the VGIC */ 354 #define KVM_NR_IRQCHIPS 1 355 356 /* PSCI interface */ 357 #define KVM_PSCI_FN_BASE 0x95c1ba5e 358 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 359 360 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 361 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 362 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 363 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 364 365 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 366 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 367 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 368 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 369 370 #endif 371 372 #endif /* __ARM_KVM_H__ */ 373