1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __ARM_KVM_H__ 24 #define __ARM_KVM_H__ 25 26 #define KVM_SPSR_EL1 0 27 #define KVM_SPSR_SVC KVM_SPSR_EL1 28 #define KVM_SPSR_ABT 1 29 #define KVM_SPSR_UND 2 30 #define KVM_SPSR_IRQ 3 31 #define KVM_SPSR_FIQ 4 32 #define KVM_NR_SPSR 5 33 34 #ifndef __ASSEMBLY__ 35 #include <linux/psci.h> 36 #include <linux/types.h> 37 #include <asm/ptrace.h> 38 39 #define __KVM_HAVE_GUEST_DEBUG 40 #define __KVM_HAVE_IRQ_LINE 41 #define __KVM_HAVE_READONLY_MEM 42 #define __KVM_HAVE_VCPU_EVENTS 43 44 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 45 46 #define KVM_REG_SIZE(id) \ 47 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 48 49 struct kvm_regs { 50 struct user_pt_regs regs; /* sp = sp_el0 */ 51 52 __u64 sp_el1; 53 __u64 elr_el1; 54 55 __u64 spsr[KVM_NR_SPSR]; 56 57 struct user_fpsimd_state fp_regs; 58 }; 59 60 /* 61 * Supported CPU Targets - Adding a new target type is not recommended, 62 * unless there are some special registers not supported by the 63 * genericv8 syreg table. 64 */ 65 #define KVM_ARM_TARGET_AEM_V8 0 66 #define KVM_ARM_TARGET_FOUNDATION_V8 1 67 #define KVM_ARM_TARGET_CORTEX_A57 2 68 #define KVM_ARM_TARGET_XGENE_POTENZA 3 69 #define KVM_ARM_TARGET_CORTEX_A53 4 70 /* Generic ARM v8 target */ 71 #define KVM_ARM_TARGET_GENERIC_V8 5 72 73 #define KVM_ARM_NUM_TARGETS 6 74 75 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 76 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 77 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT) 78 #define KVM_ARM_DEVICE_ID_SHIFT 16 79 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT) 80 81 /* Supported device IDs */ 82 #define KVM_ARM_DEVICE_VGIC_V2 0 83 84 /* Supported VGIC address types */ 85 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 86 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 87 88 #define KVM_VGIC_V2_DIST_SIZE 0x1000 89 #define KVM_VGIC_V2_CPU_SIZE 0x2000 90 91 /* Supported VGICv3 address types */ 92 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 93 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 94 #define KVM_VGIC_ITS_ADDR_TYPE 4 95 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 96 97 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 98 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 99 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 100 101 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 102 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 103 #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 104 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 105 106 struct kvm_vcpu_init { 107 __u32 target; 108 __u32 features[7]; 109 }; 110 111 struct kvm_sregs { 112 }; 113 114 struct kvm_fpu { 115 }; 116 117 /* 118 * See v8 ARM ARM D7.3: Debug Registers 119 * 120 * The architectural limit is 16 debug registers of each type although 121 * in practice there are usually less (see ID_AA64DFR0_EL1). 122 * 123 * Although the control registers are architecturally defined as 32 124 * bits wide we use a 64 bit structure here to keep parity with 125 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 126 * 64 bit values. It also allows for the possibility of the 127 * architecture expanding the control registers without having to 128 * change the userspace ABI. 129 */ 130 #define KVM_ARM_MAX_DBG_REGS 16 131 struct kvm_guest_debug_arch { 132 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 133 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 134 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 135 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 136 }; 137 138 struct kvm_debug_exit_arch { 139 __u32 hsr; 140 __u64 far; /* used for watchpoints */ 141 }; 142 143 /* 144 * Architecture specific defines for kvm_guest_debug->control 145 */ 146 147 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 148 #define KVM_GUESTDBG_USE_HW (1 << 17) 149 150 struct kvm_sync_regs { 151 /* Used with KVM_CAP_ARM_USER_IRQ */ 152 __u64 device_irq_level; 153 }; 154 155 struct kvm_arch_memory_slot { 156 }; 157 158 /* for KVM_GET/SET_VCPU_EVENTS */ 159 struct kvm_vcpu_events { 160 struct { 161 __u8 serror_pending; 162 __u8 serror_has_esr; 163 /* Align it to 8 bytes */ 164 __u8 pad[6]; 165 __u64 serror_esr; 166 } exception; 167 __u32 reserved[12]; 168 }; 169 170 /* If you need to interpret the index values, here is the key: */ 171 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 172 #define KVM_REG_ARM_COPROC_SHIFT 16 173 174 /* Normal registers are mapped as coprocessor 16. */ 175 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 176 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 177 178 /* Some registers need more space to represent values. */ 179 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 180 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 181 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 182 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 183 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 184 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 185 186 /* AArch64 system registers */ 187 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 188 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 189 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 190 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 191 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 192 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 193 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 194 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 195 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 196 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 197 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 198 199 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 200 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 201 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 202 203 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 204 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 205 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 206 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 207 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 208 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 209 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 210 211 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 212 213 /* Physical Timer EL0 Registers */ 214 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 215 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 216 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 217 218 /* EL0 Virtual Timer Registers */ 219 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 220 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 221 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 222 223 /* KVM-as-firmware specific pseudo-registers */ 224 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 225 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 226 KVM_REG_ARM_FW | ((r) & 0xffff)) 227 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 228 229 /* Device Control API: ARM VGIC */ 230 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 231 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 232 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 233 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 234 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 235 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 236 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 237 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 238 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 239 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 240 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 241 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 242 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 243 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 244 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 245 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 246 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 247 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 248 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 249 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 250 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 251 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 252 253 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 254 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 255 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 256 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 257 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 258 259 /* Device Control API on vcpu fd */ 260 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 261 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 262 #define KVM_ARM_VCPU_PMU_V3_INIT 1 263 #define KVM_ARM_VCPU_TIMER_CTRL 1 264 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 265 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 266 267 /* KVM_IRQ_LINE irq field index values */ 268 #define KVM_ARM_IRQ_TYPE_SHIFT 24 269 #define KVM_ARM_IRQ_TYPE_MASK 0xff 270 #define KVM_ARM_IRQ_VCPU_SHIFT 16 271 #define KVM_ARM_IRQ_VCPU_MASK 0xff 272 #define KVM_ARM_IRQ_NUM_SHIFT 0 273 #define KVM_ARM_IRQ_NUM_MASK 0xffff 274 275 /* irq_type field */ 276 #define KVM_ARM_IRQ_TYPE_CPU 0 277 #define KVM_ARM_IRQ_TYPE_SPI 1 278 #define KVM_ARM_IRQ_TYPE_PPI 2 279 280 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 281 #define KVM_ARM_IRQ_CPU_IRQ 0 282 #define KVM_ARM_IRQ_CPU_FIQ 1 283 284 /* 285 * This used to hold the highest supported SPI, but it is now obsolete 286 * and only here to provide source code level compatibility with older 287 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 288 */ 289 #define KVM_ARM_IRQ_GIC_MAX 127 290 291 /* One single KVM irqchip, ie. the VGIC */ 292 #define KVM_NR_IRQCHIPS 1 293 294 /* PSCI interface */ 295 #define KVM_PSCI_FN_BASE 0x95c1ba5e 296 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 297 298 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 299 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 300 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 301 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 302 303 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 304 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 305 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 306 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 307 308 #endif 309 310 #endif /* __ARM_KVM_H__ */ 311