1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 38 /* XXX: make safe guess about sizes */ 39 #define MAX_OP_PER_INSTR 266 40 41 #define MAX_CALL_IARGS 7 42 43 #define CPU_TEMP_BUF_NLONGS 128 44 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 45 46 /* Default target word size to pointer size. */ 47 #ifndef TCG_TARGET_REG_BITS 48 # if UINTPTR_MAX == UINT32_MAX 49 # define TCG_TARGET_REG_BITS 32 50 # elif UINTPTR_MAX == UINT64_MAX 51 # define TCG_TARGET_REG_BITS 64 52 # else 53 # error Unknown pointer size for tcg target 54 # endif 55 #endif 56 57 #if TCG_TARGET_REG_BITS == 32 58 typedef int32_t tcg_target_long; 59 typedef uint32_t tcg_target_ulong; 60 #define TCG_PRIlx PRIx32 61 #define TCG_PRIld PRId32 62 #elif TCG_TARGET_REG_BITS == 64 63 typedef int64_t tcg_target_long; 64 typedef uint64_t tcg_target_ulong; 65 #define TCG_PRIlx PRIx64 66 #define TCG_PRIld PRId64 67 #else 68 #error unsupported 69 #endif 70 71 /* Oversized TCG guests make things like MTTCG hard 72 * as we can't use atomics for cputlb updates. 73 */ 74 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 75 #define TCG_OVERSIZED_GUEST 1 76 #else 77 #define TCG_OVERSIZED_GUEST 0 78 #endif 79 80 #if TCG_TARGET_NB_REGS <= 32 81 typedef uint32_t TCGRegSet; 82 #elif TCG_TARGET_NB_REGS <= 64 83 typedef uint64_t TCGRegSet; 84 #else 85 #error unsupported 86 #endif 87 88 #if TCG_TARGET_REG_BITS == 32 89 /* Turn some undef macros into false macros. */ 90 #define TCG_TARGET_HAS_extrl_i64_i32 0 91 #define TCG_TARGET_HAS_extrh_i64_i32 0 92 #define TCG_TARGET_HAS_div_i64 0 93 #define TCG_TARGET_HAS_rem_i64 0 94 #define TCG_TARGET_HAS_div2_i64 0 95 #define TCG_TARGET_HAS_rot_i64 0 96 #define TCG_TARGET_HAS_ext8s_i64 0 97 #define TCG_TARGET_HAS_ext16s_i64 0 98 #define TCG_TARGET_HAS_ext32s_i64 0 99 #define TCG_TARGET_HAS_ext8u_i64 0 100 #define TCG_TARGET_HAS_ext16u_i64 0 101 #define TCG_TARGET_HAS_ext32u_i64 0 102 #define TCG_TARGET_HAS_bswap16_i64 0 103 #define TCG_TARGET_HAS_bswap32_i64 0 104 #define TCG_TARGET_HAS_bswap64_i64 0 105 #define TCG_TARGET_HAS_neg_i64 0 106 #define TCG_TARGET_HAS_not_i64 0 107 #define TCG_TARGET_HAS_andc_i64 0 108 #define TCG_TARGET_HAS_orc_i64 0 109 #define TCG_TARGET_HAS_eqv_i64 0 110 #define TCG_TARGET_HAS_nand_i64 0 111 #define TCG_TARGET_HAS_nor_i64 0 112 #define TCG_TARGET_HAS_clz_i64 0 113 #define TCG_TARGET_HAS_ctz_i64 0 114 #define TCG_TARGET_HAS_ctpop_i64 0 115 #define TCG_TARGET_HAS_deposit_i64 0 116 #define TCG_TARGET_HAS_extract_i64 0 117 #define TCG_TARGET_HAS_sextract_i64 0 118 #define TCG_TARGET_HAS_extract2_i64 0 119 #define TCG_TARGET_HAS_movcond_i64 0 120 #define TCG_TARGET_HAS_add2_i64 0 121 #define TCG_TARGET_HAS_sub2_i64 0 122 #define TCG_TARGET_HAS_mulu2_i64 0 123 #define TCG_TARGET_HAS_muls2_i64 0 124 #define TCG_TARGET_HAS_muluh_i64 0 125 #define TCG_TARGET_HAS_mulsh_i64 0 126 /* Turn some undef macros into true macros. */ 127 #define TCG_TARGET_HAS_add2_i32 1 128 #define TCG_TARGET_HAS_sub2_i32 1 129 #endif 130 131 #ifndef TCG_TARGET_deposit_i32_valid 132 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 133 #endif 134 #ifndef TCG_TARGET_deposit_i64_valid 135 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 136 #endif 137 #ifndef TCG_TARGET_extract_i32_valid 138 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 139 #endif 140 #ifndef TCG_TARGET_extract_i64_valid 141 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 142 #endif 143 144 /* Only one of DIV or DIV2 should be defined. */ 145 #if defined(TCG_TARGET_HAS_div_i32) 146 #define TCG_TARGET_HAS_div2_i32 0 147 #elif defined(TCG_TARGET_HAS_div2_i32) 148 #define TCG_TARGET_HAS_div_i32 0 149 #define TCG_TARGET_HAS_rem_i32 0 150 #endif 151 #if defined(TCG_TARGET_HAS_div_i64) 152 #define TCG_TARGET_HAS_div2_i64 0 153 #elif defined(TCG_TARGET_HAS_div2_i64) 154 #define TCG_TARGET_HAS_div_i64 0 155 #define TCG_TARGET_HAS_rem_i64 0 156 #endif 157 158 #if !defined(TCG_TARGET_HAS_v64) \ 159 && !defined(TCG_TARGET_HAS_v128) \ 160 && !defined(TCG_TARGET_HAS_v256) 161 #define TCG_TARGET_MAYBE_vec 0 162 #define TCG_TARGET_HAS_abs_vec 0 163 #define TCG_TARGET_HAS_neg_vec 0 164 #define TCG_TARGET_HAS_not_vec 0 165 #define TCG_TARGET_HAS_andc_vec 0 166 #define TCG_TARGET_HAS_orc_vec 0 167 #define TCG_TARGET_HAS_nand_vec 0 168 #define TCG_TARGET_HAS_nor_vec 0 169 #define TCG_TARGET_HAS_eqv_vec 0 170 #define TCG_TARGET_HAS_roti_vec 0 171 #define TCG_TARGET_HAS_rots_vec 0 172 #define TCG_TARGET_HAS_rotv_vec 0 173 #define TCG_TARGET_HAS_shi_vec 0 174 #define TCG_TARGET_HAS_shs_vec 0 175 #define TCG_TARGET_HAS_shv_vec 0 176 #define TCG_TARGET_HAS_mul_vec 0 177 #define TCG_TARGET_HAS_sat_vec 0 178 #define TCG_TARGET_HAS_minmax_vec 0 179 #define TCG_TARGET_HAS_bitsel_vec 0 180 #define TCG_TARGET_HAS_cmpsel_vec 0 181 #else 182 #define TCG_TARGET_MAYBE_vec 1 183 #endif 184 #ifndef TCG_TARGET_HAS_v64 185 #define TCG_TARGET_HAS_v64 0 186 #endif 187 #ifndef TCG_TARGET_HAS_v128 188 #define TCG_TARGET_HAS_v128 0 189 #endif 190 #ifndef TCG_TARGET_HAS_v256 191 #define TCG_TARGET_HAS_v256 0 192 #endif 193 194 #ifndef TARGET_INSN_START_EXTRA_WORDS 195 # define TARGET_INSN_START_WORDS 1 196 #else 197 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 198 #endif 199 200 typedef enum TCGOpcode { 201 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 202 #include "tcg/tcg-opc.h" 203 #undef DEF 204 NB_OPS, 205 } TCGOpcode; 206 207 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 208 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 209 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 210 211 #ifndef TCG_TARGET_INSN_UNIT_SIZE 212 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 213 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 214 typedef uint8_t tcg_insn_unit; 215 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 216 typedef uint16_t tcg_insn_unit; 217 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 218 typedef uint32_t tcg_insn_unit; 219 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 220 typedef uint64_t tcg_insn_unit; 221 #else 222 /* The port better have done this. */ 223 #endif 224 225 226 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS 227 # define tcg_debug_assert(X) do { assert(X); } while (0) 228 #else 229 # define tcg_debug_assert(X) \ 230 do { if (!(X)) { __builtin_unreachable(); } } while (0) 231 #endif 232 233 typedef struct TCGRelocation TCGRelocation; 234 struct TCGRelocation { 235 QSIMPLEQ_ENTRY(TCGRelocation) next; 236 tcg_insn_unit *ptr; 237 intptr_t addend; 238 int type; 239 }; 240 241 typedef struct TCGLabel TCGLabel; 242 struct TCGLabel { 243 unsigned present : 1; 244 unsigned has_value : 1; 245 unsigned id : 14; 246 unsigned refs : 16; 247 union { 248 uintptr_t value; 249 const tcg_insn_unit *value_ptr; 250 } u; 251 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 252 QSIMPLEQ_ENTRY(TCGLabel) next; 253 }; 254 255 typedef struct TCGPool { 256 struct TCGPool *next; 257 int size; 258 uint8_t data[] __attribute__ ((aligned)); 259 } TCGPool; 260 261 #define TCG_POOL_CHUNK_SIZE 32768 262 263 #define TCG_MAX_TEMPS 512 264 #define TCG_MAX_INSNS 512 265 266 /* when the size of the arguments of a called function is smaller than 267 this value, they are statically allocated in the TB stack frame */ 268 #define TCG_STATIC_CALL_ARGS_SIZE 128 269 270 typedef enum TCGType { 271 TCG_TYPE_I32, 272 TCG_TYPE_I64, 273 274 TCG_TYPE_V64, 275 TCG_TYPE_V128, 276 TCG_TYPE_V256, 277 278 /* Number of different types (integer not enum) */ 279 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 280 281 /* An alias for the size of the host register. */ 282 #if TCG_TARGET_REG_BITS == 32 283 TCG_TYPE_REG = TCG_TYPE_I32, 284 #else 285 TCG_TYPE_REG = TCG_TYPE_I64, 286 #endif 287 288 /* An alias for the size of the native pointer. */ 289 #if UINTPTR_MAX == UINT32_MAX 290 TCG_TYPE_PTR = TCG_TYPE_I32, 291 #else 292 TCG_TYPE_PTR = TCG_TYPE_I64, 293 #endif 294 295 /* An alias for the size of the target "long", aka register. */ 296 #if TARGET_LONG_BITS == 64 297 TCG_TYPE_TL = TCG_TYPE_I64, 298 #else 299 TCG_TYPE_TL = TCG_TYPE_I32, 300 #endif 301 } TCGType; 302 303 /** 304 * tcg_type_size 305 * @t: type 306 * 307 * Return the size of the type in bytes. 308 */ 309 static inline int tcg_type_size(TCGType t) 310 { 311 unsigned i = t; 312 if (i >= TCG_TYPE_V64) { 313 tcg_debug_assert(i < TCG_TYPE_COUNT); 314 i -= TCG_TYPE_V64 - 1; 315 } 316 return 4 << i; 317 } 318 319 /** 320 * get_alignment_bits 321 * @memop: MemOp value 322 * 323 * Extract the alignment size from the memop. 324 */ 325 static inline unsigned get_alignment_bits(MemOp memop) 326 { 327 unsigned a = memop & MO_AMASK; 328 329 if (a == MO_UNALN) { 330 /* No alignment required. */ 331 a = 0; 332 } else if (a == MO_ALIGN) { 333 /* A natural alignment requirement. */ 334 a = memop & MO_SIZE; 335 } else { 336 /* A specific alignment requirement. */ 337 a = a >> MO_ASHIFT; 338 } 339 #if defined(CONFIG_SOFTMMU) 340 /* The requested alignment cannot overlap the TLB flags. */ 341 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 342 #endif 343 return a; 344 } 345 346 typedef tcg_target_ulong TCGArg; 347 348 /* Define type and accessor macros for TCG variables. 349 350 TCG variables are the inputs and outputs of TCG ops, as described 351 in tcg/README. Target CPU front-end code uses these types to deal 352 with TCG variables as it emits TCG code via the tcg_gen_* functions. 353 They come in several flavours: 354 * TCGv_i32 : 32 bit integer type 355 * TCGv_i64 : 64 bit integer type 356 * TCGv_ptr : a host pointer type 357 * TCGv_vec : a host vector type; the exact size is not exposed 358 to the CPU front-end code. 359 * TCGv : an integer type the same size as target_ulong 360 (an alias for either TCGv_i32 or TCGv_i64) 361 The compiler's type checking will complain if you mix them 362 up and pass the wrong sized TCGv to a function. 363 364 Users of tcg_gen_* don't need to know about any of the internal 365 details of these, and should treat them as opaque types. 366 You won't be able to look inside them in a debugger either. 367 368 Internal implementation details follow: 369 370 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 371 This is deliberate, because the values we store in variables of type 372 TCGv_i32 are not really pointers-to-structures. They're just small 373 integers, but keeping them in pointer types like this means that the 374 compiler will complain if you accidentally pass a TCGv_i32 to a 375 function which takes a TCGv_i64, and so on. Only the internals of 376 TCG need to care about the actual contents of the types. */ 377 378 typedef struct TCGv_i32_d *TCGv_i32; 379 typedef struct TCGv_i64_d *TCGv_i64; 380 typedef struct TCGv_ptr_d *TCGv_ptr; 381 typedef struct TCGv_vec_d *TCGv_vec; 382 typedef TCGv_ptr TCGv_env; 383 #if TARGET_LONG_BITS == 32 384 #define TCGv TCGv_i32 385 #elif TARGET_LONG_BITS == 64 386 #define TCGv TCGv_i64 387 #else 388 #error Unhandled TARGET_LONG_BITS value 389 #endif 390 391 /* call flags */ 392 /* Helper does not read globals (either directly or through an exception). It 393 implies TCG_CALL_NO_WRITE_GLOBALS. */ 394 #define TCG_CALL_NO_READ_GLOBALS 0x0001 395 /* Helper does not write globals */ 396 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 397 /* Helper can be safely suppressed if the return value is not used. */ 398 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 399 /* Helper is G_NORETURN. */ 400 #define TCG_CALL_NO_RETURN 0x0008 401 402 /* convenience version of most used call flags */ 403 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 404 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 405 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 406 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 407 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 408 409 /* 410 * Flags for the bswap opcodes. 411 * If IZ, the input is zero-extended, otherwise unknown. 412 * If OZ or OS, the output is zero- or sign-extended respectively, 413 * otherwise the high bits are undefined. 414 */ 415 enum { 416 TCG_BSWAP_IZ = 1, 417 TCG_BSWAP_OZ = 2, 418 TCG_BSWAP_OS = 4, 419 }; 420 421 typedef enum TCGTempVal { 422 TEMP_VAL_DEAD, 423 TEMP_VAL_REG, 424 TEMP_VAL_MEM, 425 TEMP_VAL_CONST, 426 } TCGTempVal; 427 428 typedef enum TCGTempKind { 429 /* Temp is dead at the end of all basic blocks. */ 430 TEMP_NORMAL, 431 /* Temp is live across conditional branch, but dead otherwise. */ 432 TEMP_EBB, 433 /* Temp is saved across basic blocks but dead at the end of TBs. */ 434 TEMP_LOCAL, 435 /* Temp is saved across both basic blocks and translation blocks. */ 436 TEMP_GLOBAL, 437 /* Temp is in a fixed register. */ 438 TEMP_FIXED, 439 /* Temp is a fixed constant. */ 440 TEMP_CONST, 441 } TCGTempKind; 442 443 typedef struct TCGTemp { 444 TCGReg reg:8; 445 TCGTempVal val_type:8; 446 TCGType base_type:8; 447 TCGType type:8; 448 TCGTempKind kind:3; 449 unsigned int indirect_reg:1; 450 unsigned int indirect_base:1; 451 unsigned int mem_coherent:1; 452 unsigned int mem_allocated:1; 453 unsigned int temp_allocated:1; 454 unsigned int temp_subindex:1; 455 456 int64_t val; 457 struct TCGTemp *mem_base; 458 intptr_t mem_offset; 459 const char *name; 460 461 /* Pass-specific information that can be stored for a temporary. 462 One word worth of integer data, and one pointer to data 463 allocated separately. */ 464 uintptr_t state; 465 void *state_ptr; 466 } TCGTemp; 467 468 typedef struct TCGContext TCGContext; 469 470 typedef struct TCGTempSet { 471 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 472 } TCGTempSet; 473 474 /* 475 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 476 * which leaves a maximum of 28 other slots. Which is enough for 7 477 * 128-bit operands. 478 */ 479 #define DEAD_ARG (1 << 4) 480 #define SYNC_ARG (1 << 0) 481 typedef uint32_t TCGLifeData; 482 483 typedef struct TCGOp { 484 TCGOpcode opc : 8; 485 unsigned nargs : 8; 486 487 /* Parameters for this opcode. See below. */ 488 unsigned param1 : 8; 489 unsigned param2 : 8; 490 491 /* Lifetime data of the operands. */ 492 TCGLifeData life; 493 494 /* Next and previous opcodes. */ 495 QTAILQ_ENTRY(TCGOp) link; 496 497 /* Register preferences for the output(s). */ 498 TCGRegSet output_pref[2]; 499 500 /* Arguments for the opcode. */ 501 TCGArg args[]; 502 } TCGOp; 503 504 #define TCGOP_CALLI(X) (X)->param1 505 #define TCGOP_CALLO(X) (X)->param2 506 507 #define TCGOP_VECL(X) (X)->param1 508 #define TCGOP_VECE(X) (X)->param2 509 510 /* Make sure operands fit in the bitfields above. */ 511 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 512 513 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 514 { 515 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 516 } 517 518 typedef struct TCGProfile { 519 int64_t cpu_exec_time; 520 int64_t tb_count1; 521 int64_t tb_count; 522 int64_t op_count; /* total insn count */ 523 int op_count_max; /* max insn per TB */ 524 int temp_count_max; 525 int64_t temp_count; 526 int64_t del_op_count; 527 int64_t code_in_len; 528 int64_t code_out_len; 529 int64_t search_out_len; 530 int64_t interm_time; 531 int64_t code_time; 532 int64_t la_time; 533 int64_t opt_time; 534 int64_t restore_count; 535 int64_t restore_time; 536 int64_t table_op_count[NB_OPS]; 537 } TCGProfile; 538 539 struct TCGContext { 540 uint8_t *pool_cur, *pool_end; 541 TCGPool *pool_first, *pool_current, *pool_first_large; 542 int nb_labels; 543 int nb_globals; 544 int nb_temps; 545 int nb_indirects; 546 int nb_ops; 547 548 TCGRegSet reserved_regs; 549 intptr_t current_frame_offset; 550 intptr_t frame_start; 551 intptr_t frame_end; 552 TCGTemp *frame_temp; 553 554 TranslationBlock *gen_tb; /* tb for which code is being generated */ 555 tcg_insn_unit *code_buf; /* pointer for start of tb */ 556 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 557 558 #ifdef CONFIG_PROFILER 559 TCGProfile prof; 560 #endif 561 562 #ifdef CONFIG_DEBUG_TCG 563 int temps_in_use; 564 int goto_tb_issue_mask; 565 const TCGOpcode *vecop_list; 566 #endif 567 568 /* Code generation. Note that we specifically do not use tcg_insn_unit 569 here, because there's too much arithmetic throughout that relies 570 on addition and subtraction working on bytes. Rely on the GCC 571 extension that allows arithmetic on void*. */ 572 void *code_gen_buffer; 573 size_t code_gen_buffer_size; 574 void *code_gen_ptr; 575 void *data_gen_ptr; 576 577 /* Threshold to flush the translated code buffer. */ 578 void *code_gen_highwater; 579 580 /* Track which vCPU triggers events */ 581 CPUState *cpu; /* *_trans */ 582 583 /* These structures are private to tcg-target.c.inc. */ 584 #ifdef TCG_TARGET_NEED_LDST_LABELS 585 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 586 #endif 587 #ifdef TCG_TARGET_NEED_POOL_LABELS 588 struct TCGLabelPoolData *pool_labels; 589 #endif 590 591 TCGLabel *exitreq_label; 592 593 #ifdef CONFIG_PLUGIN 594 /* 595 * We keep one plugin_tb struct per TCGContext. Note that on every TB 596 * translation we clear but do not free its contents; this way we 597 * avoid a lot of malloc/free churn, since after a few TB's it's 598 * unlikely that we'll need to allocate either more instructions or more 599 * space for instructions (for variable-instruction-length ISAs). 600 */ 601 struct qemu_plugin_tb *plugin_tb; 602 603 /* descriptor of the instruction being translated */ 604 struct qemu_plugin_insn *plugin_insn; 605 #endif 606 607 GHashTable *const_table[TCG_TYPE_COUNT]; 608 TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; 609 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 610 611 QTAILQ_HEAD(, TCGOp) ops, free_ops; 612 QSIMPLEQ_HEAD(, TCGLabel) labels; 613 614 /* Tells which temporary holds a given register. 615 It does not take into account fixed registers */ 616 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 617 618 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 619 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 620 621 /* Exit to translator on overflow. */ 622 sigjmp_buf jmp_trans; 623 }; 624 625 static inline bool temp_readonly(TCGTemp *ts) 626 { 627 return ts->kind >= TEMP_FIXED; 628 } 629 630 extern __thread TCGContext *tcg_ctx; 631 extern const void *tcg_code_gen_epilogue; 632 extern uintptr_t tcg_splitwx_diff; 633 extern TCGv_env cpu_env; 634 635 bool in_code_gen_buffer(const void *p); 636 637 #ifdef CONFIG_DEBUG_TCG 638 const void *tcg_splitwx_to_rx(void *rw); 639 void *tcg_splitwx_to_rw(const void *rx); 640 #else 641 static inline const void *tcg_splitwx_to_rx(void *rw) 642 { 643 return rw ? rw + tcg_splitwx_diff : NULL; 644 } 645 646 static inline void *tcg_splitwx_to_rw(const void *rx) 647 { 648 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 649 } 650 #endif 651 652 static inline size_t temp_idx(TCGTemp *ts) 653 { 654 ptrdiff_t n = ts - tcg_ctx->temps; 655 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 656 return n; 657 } 658 659 static inline TCGArg temp_arg(TCGTemp *ts) 660 { 661 return (uintptr_t)ts; 662 } 663 664 static inline TCGTemp *arg_temp(TCGArg a) 665 { 666 return (TCGTemp *)(uintptr_t)a; 667 } 668 669 /* Using the offset of a temporary, relative to TCGContext, rather than 670 its index means that we don't use 0. That leaves offset 0 free for 671 a NULL representation without having to leave index 0 unused. */ 672 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 673 { 674 uintptr_t o = (uintptr_t)v; 675 TCGTemp *t = (void *)tcg_ctx + o; 676 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 677 return t; 678 } 679 680 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 681 { 682 return tcgv_i32_temp((TCGv_i32)v); 683 } 684 685 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 686 { 687 return tcgv_i32_temp((TCGv_i32)v); 688 } 689 690 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 691 { 692 return tcgv_i32_temp((TCGv_i32)v); 693 } 694 695 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 696 { 697 return temp_arg(tcgv_i32_temp(v)); 698 } 699 700 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 701 { 702 return temp_arg(tcgv_i64_temp(v)); 703 } 704 705 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 706 { 707 return temp_arg(tcgv_ptr_temp(v)); 708 } 709 710 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 711 { 712 return temp_arg(tcgv_vec_temp(v)); 713 } 714 715 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 716 { 717 (void)temp_idx(t); /* trigger embedded assert */ 718 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 719 } 720 721 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 722 { 723 return (TCGv_i64)temp_tcgv_i32(t); 724 } 725 726 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 727 { 728 return (TCGv_ptr)temp_tcgv_i32(t); 729 } 730 731 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 732 { 733 return (TCGv_vec)temp_tcgv_i32(t); 734 } 735 736 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 737 { 738 return op->args[arg]; 739 } 740 741 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 742 { 743 op->args[arg] = v; 744 } 745 746 static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) 747 { 748 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 749 return tcg_get_insn_param(op, arg); 750 #else 751 return tcg_get_insn_param(op, arg * 2) | 752 ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); 753 #endif 754 } 755 756 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) 757 { 758 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 759 tcg_set_insn_param(op, arg, v); 760 #else 761 tcg_set_insn_param(op, arg * 2, v); 762 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 763 #endif 764 } 765 766 /* The last op that was emitted. */ 767 static inline TCGOp *tcg_last_op(void) 768 { 769 return QTAILQ_LAST(&tcg_ctx->ops); 770 } 771 772 /* Test for whether to terminate the TB for using too many opcodes. */ 773 static inline bool tcg_op_buf_full(void) 774 { 775 /* This is not a hard limit, it merely stops translation when 776 * we have produced "enough" opcodes. We want to limit TB size 777 * such that a RISC host can reasonably use a 16-bit signed 778 * branch within the TB. We also need to be mindful of the 779 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 780 * and TCGContext.gen_insn_end_off[]. 781 */ 782 return tcg_ctx->nb_ops >= 4000; 783 } 784 785 /* pool based memory allocation */ 786 787 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 788 void *tcg_malloc_internal(TCGContext *s, int size); 789 void tcg_pool_reset(TCGContext *s); 790 TranslationBlock *tcg_tb_alloc(TCGContext *s); 791 792 void tcg_region_reset_all(void); 793 794 size_t tcg_code_size(void); 795 size_t tcg_code_capacity(void); 796 797 void tcg_tb_insert(TranslationBlock *tb); 798 void tcg_tb_remove(TranslationBlock *tb); 799 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 800 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 801 size_t tcg_nb_tbs(void); 802 803 /* user-mode: Called with mmap_lock held. */ 804 static inline void *tcg_malloc(int size) 805 { 806 TCGContext *s = tcg_ctx; 807 uint8_t *ptr, *ptr_end; 808 809 /* ??? This is a weak placeholder for minimum malloc alignment. */ 810 size = QEMU_ALIGN_UP(size, 8); 811 812 ptr = s->pool_cur; 813 ptr_end = ptr + size; 814 if (unlikely(ptr_end > s->pool_end)) { 815 return tcg_malloc_internal(tcg_ctx, size); 816 } else { 817 s->pool_cur = ptr_end; 818 return ptr; 819 } 820 } 821 822 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 823 void tcg_register_thread(void); 824 void tcg_prologue_init(TCGContext *s); 825 void tcg_func_start(TCGContext *s); 826 827 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start); 828 829 void tb_target_set_jmp_target(const TranslationBlock *, int, 830 uintptr_t, uintptr_t); 831 832 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 833 834 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 835 intptr_t, const char *); 836 TCGTemp *tcg_temp_new_internal(TCGType, bool); 837 void tcg_temp_free_internal(TCGTemp *); 838 TCGv_vec tcg_temp_new_vec(TCGType type); 839 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 840 841 static inline void tcg_temp_free_i32(TCGv_i32 arg) 842 { 843 tcg_temp_free_internal(tcgv_i32_temp(arg)); 844 } 845 846 static inline void tcg_temp_free_i64(TCGv_i64 arg) 847 { 848 tcg_temp_free_internal(tcgv_i64_temp(arg)); 849 } 850 851 static inline void tcg_temp_free_ptr(TCGv_ptr arg) 852 { 853 tcg_temp_free_internal(tcgv_ptr_temp(arg)); 854 } 855 856 static inline void tcg_temp_free_vec(TCGv_vec arg) 857 { 858 tcg_temp_free_internal(tcgv_vec_temp(arg)); 859 } 860 861 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 862 const char *name) 863 { 864 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 865 return temp_tcgv_i32(t); 866 } 867 868 static inline TCGv_i32 tcg_temp_new_i32(void) 869 { 870 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); 871 return temp_tcgv_i32(t); 872 } 873 874 static inline TCGv_i32 tcg_temp_local_new_i32(void) 875 { 876 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); 877 return temp_tcgv_i32(t); 878 } 879 880 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 881 const char *name) 882 { 883 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 884 return temp_tcgv_i64(t); 885 } 886 887 static inline TCGv_i64 tcg_temp_new_i64(void) 888 { 889 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); 890 return temp_tcgv_i64(t); 891 } 892 893 static inline TCGv_i64 tcg_temp_local_new_i64(void) 894 { 895 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); 896 return temp_tcgv_i64(t); 897 } 898 899 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 900 const char *name) 901 { 902 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 903 return temp_tcgv_ptr(t); 904 } 905 906 static inline TCGv_ptr tcg_temp_new_ptr(void) 907 { 908 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); 909 return temp_tcgv_ptr(t); 910 } 911 912 static inline TCGv_ptr tcg_temp_local_new_ptr(void) 913 { 914 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); 915 return temp_tcgv_ptr(t); 916 } 917 918 #if defined(CONFIG_DEBUG_TCG) 919 /* If you call tcg_clear_temp_count() at the start of a section of 920 * code which is not supposed to leak any TCG temporaries, then 921 * calling tcg_check_temp_count() at the end of the section will 922 * return 1 if the section did in fact leak a temporary. 923 */ 924 void tcg_clear_temp_count(void); 925 int tcg_check_temp_count(void); 926 #else 927 #define tcg_clear_temp_count() do { } while (0) 928 #define tcg_check_temp_count() 0 929 #endif 930 931 int64_t tcg_cpu_exec_time(void); 932 void tcg_dump_info(GString *buf); 933 void tcg_dump_op_count(GString *buf); 934 935 #define TCG_CT_CONST 1 /* any constant of register size */ 936 937 typedef struct TCGArgConstraint { 938 unsigned ct : 16; 939 unsigned alias_index : 4; 940 unsigned sort_index : 4; 941 unsigned pair_index : 4; 942 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 943 bool oalias : 1; 944 bool ialias : 1; 945 bool newreg : 1; 946 TCGRegSet regs; 947 } TCGArgConstraint; 948 949 #define TCG_MAX_OP_ARGS 16 950 951 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 952 enum { 953 /* Instruction exits the translation block. */ 954 TCG_OPF_BB_EXIT = 0x01, 955 /* Instruction defines the end of a basic block. */ 956 TCG_OPF_BB_END = 0x02, 957 /* Instruction clobbers call registers and potentially update globals. */ 958 TCG_OPF_CALL_CLOBBER = 0x04, 959 /* Instruction has side effects: it cannot be removed if its outputs 960 are not used, and might trigger exceptions. */ 961 TCG_OPF_SIDE_EFFECTS = 0x08, 962 /* Instruction operands are 64-bits (otherwise 32-bits). */ 963 TCG_OPF_64BIT = 0x10, 964 /* Instruction is optional and not implemented by the host, or insn 965 is generic and should not be implemened by the host. */ 966 TCG_OPF_NOT_PRESENT = 0x20, 967 /* Instruction operands are vectors. */ 968 TCG_OPF_VECTOR = 0x40, 969 /* Instruction is a conditional branch. */ 970 TCG_OPF_COND_BRANCH = 0x80 971 }; 972 973 typedef struct TCGOpDef { 974 const char *name; 975 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 976 uint8_t flags; 977 TCGArgConstraint *args_ct; 978 } TCGOpDef; 979 980 extern TCGOpDef tcg_op_defs[]; 981 extern const size_t tcg_op_defs_max; 982 983 typedef struct TCGTargetOpDef { 984 TCGOpcode op; 985 const char *args_ct_str[TCG_MAX_OP_ARGS]; 986 } TCGTargetOpDef; 987 988 #define tcg_abort() \ 989 do {\ 990 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ 991 abort();\ 992 } while (0) 993 994 bool tcg_op_supported(TCGOpcode op); 995 996 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 997 998 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 999 void tcg_op_remove(TCGContext *s, TCGOp *op); 1000 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 1001 TCGOpcode opc, unsigned nargs); 1002 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 1003 TCGOpcode opc, unsigned nargs); 1004 1005 /** 1006 * tcg_remove_ops_after: 1007 * @op: target operation 1008 * 1009 * Discard any opcodes emitted since @op. Expected usage is to save 1010 * a starting point with tcg_last_op(), speculatively emit opcodes, 1011 * then decide whether or not to keep those opcodes after the fact. 1012 */ 1013 void tcg_remove_ops_after(TCGOp *op); 1014 1015 void tcg_optimize(TCGContext *s); 1016 1017 /* Allocate a new temporary and initialize it with a constant. */ 1018 TCGv_i32 tcg_const_i32(int32_t val); 1019 TCGv_i64 tcg_const_i64(int64_t val); 1020 TCGv_i32 tcg_const_local_i32(int32_t val); 1021 TCGv_i64 tcg_const_local_i64(int64_t val); 1022 TCGv_vec tcg_const_zeros_vec(TCGType); 1023 TCGv_vec tcg_const_ones_vec(TCGType); 1024 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); 1025 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); 1026 1027 /* 1028 * Locate or create a read-only temporary that is a constant. 1029 * This kind of temporary need not be freed, but for convenience 1030 * will be silently ignored by tcg_temp_free_*. 1031 */ 1032 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 1033 1034 static inline TCGv_i32 tcg_constant_i32(int32_t val) 1035 { 1036 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 1037 } 1038 1039 static inline TCGv_i64 tcg_constant_i64(int64_t val) 1040 { 1041 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1042 } 1043 1044 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1045 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1046 1047 #if UINTPTR_MAX == UINT32_MAX 1048 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) 1049 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) 1050 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 1051 #else 1052 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) 1053 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) 1054 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1055 #endif 1056 1057 TCGLabel *gen_new_label(void); 1058 1059 /** 1060 * label_arg 1061 * @l: label 1062 * 1063 * Encode a label for storage in the TCG opcode stream. 1064 */ 1065 1066 static inline TCGArg label_arg(TCGLabel *l) 1067 { 1068 return (uintptr_t)l; 1069 } 1070 1071 /** 1072 * arg_label 1073 * @i: value 1074 * 1075 * The opposite of label_arg. Retrieve a label from the 1076 * encoding of the TCG opcode stream. 1077 */ 1078 1079 static inline TCGLabel *arg_label(TCGArg i) 1080 { 1081 return (TCGLabel *)(uintptr_t)i; 1082 } 1083 1084 /** 1085 * tcg_ptr_byte_diff 1086 * @a, @b: addresses to be differenced 1087 * 1088 * There are many places within the TCG backends where we need a byte 1089 * difference between two pointers. While this can be accomplished 1090 * with local casting, it's easy to get wrong -- especially if one is 1091 * concerned with the signedness of the result. 1092 * 1093 * This version relies on GCC's void pointer arithmetic to get the 1094 * correct result. 1095 */ 1096 1097 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1098 { 1099 return a - b; 1100 } 1101 1102 /** 1103 * tcg_pcrel_diff 1104 * @s: the tcg context 1105 * @target: address of the target 1106 * 1107 * Produce a pc-relative difference, from the current code_ptr 1108 * to the destination address. 1109 */ 1110 1111 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1112 { 1113 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1114 } 1115 1116 /** 1117 * tcg_tbrel_diff 1118 * @s: the tcg context 1119 * @target: address of the target 1120 * 1121 * Produce a difference, from the beginning of the current TB code 1122 * to the destination address. 1123 */ 1124 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1125 { 1126 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1127 } 1128 1129 /** 1130 * tcg_current_code_size 1131 * @s: the tcg context 1132 * 1133 * Compute the current code size within the translation block. 1134 * This is used to fill in qemu's data structures for goto_tb. 1135 */ 1136 1137 static inline size_t tcg_current_code_size(TCGContext *s) 1138 { 1139 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1140 } 1141 1142 /** 1143 * tcg_qemu_tb_exec: 1144 * @env: pointer to CPUArchState for the CPU 1145 * @tb_ptr: address of generated code for the TB to execute 1146 * 1147 * Start executing code from a given translation block. 1148 * Where translation blocks have been linked, execution 1149 * may proceed from the given TB into successive ones. 1150 * Control eventually returns only when some action is needed 1151 * from the top-level loop: either control must pass to a TB 1152 * which has not yet been directly linked, or an asynchronous 1153 * event such as an interrupt needs handling. 1154 * 1155 * Return: The return value is the value passed to the corresponding 1156 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1157 * The value is either zero or a 4-byte aligned pointer to that TB combined 1158 * with additional information in its two least significant bits. The 1159 * additional information is encoded as follows: 1160 * 0, 1: the link between this TB and the next is via the specified 1161 * TB index (0 or 1). That is, we left the TB via (the equivalent 1162 * of) "goto_tb <index>". The main loop uses this to determine 1163 * how to link the TB just executed to the next. 1164 * 2: we are using instruction counting code generation, and we 1165 * did not start executing this TB because the instruction counter 1166 * would hit zero midway through it. In this case the pointer 1167 * returned is the TB we were about to execute, and the caller must 1168 * arrange to execute the remaining count of instructions. 1169 * 3: we stopped because the CPU's exit_request flag was set 1170 * (usually meaning that there is an interrupt that needs to be 1171 * handled). The pointer returned is the TB we were about to execute 1172 * when we noticed the pending exit request. 1173 * 1174 * If the bottom two bits indicate an exit-via-index then the CPU 1175 * state is correctly synchronised and ready for execution of the next 1176 * TB (and in particular the guest PC is the address to execute next). 1177 * Otherwise, we gave up on execution of this TB before it started, and 1178 * the caller must fix up the CPU state by calling the CPU's 1179 * synchronize_from_tb() method with the TB pointer we return (falling 1180 * back to calling the CPU's set_pc method with tb->pb if no 1181 * synchronize_from_tb() method exists). 1182 * 1183 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1184 * to this default (which just calls the prologue.code emitted by 1185 * tcg_target_qemu_prologue()). 1186 */ 1187 #define TB_EXIT_MASK 3 1188 #define TB_EXIT_IDX0 0 1189 #define TB_EXIT_IDX1 1 1190 #define TB_EXIT_IDXMAX 1 1191 #define TB_EXIT_REQUESTED 3 1192 1193 #ifdef CONFIG_TCG_INTERPRETER 1194 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1195 #else 1196 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1197 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1198 #endif 1199 1200 void tcg_register_jit(const void *buf, size_t buf_size); 1201 1202 #if TCG_TARGET_MAYBE_vec 1203 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1204 return > 0 if it is directly supportable; 1205 return < 0 if we must call tcg_expand_vec_op. */ 1206 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1207 #else 1208 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1209 { 1210 return 0; 1211 } 1212 #endif 1213 1214 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1215 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1216 1217 /* Replicate a constant C accoring to the log2 of the element size. */ 1218 uint64_t dup_const(unsigned vece, uint64_t c); 1219 1220 #define dup_const(VECE, C) \ 1221 (__builtin_constant_p(VECE) \ 1222 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1223 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1224 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1225 : (VECE) == MO_64 ? (uint64_t)(C) \ 1226 : (qemu_build_not_reached_always(), 0)) \ 1227 : dup_const(VECE, C)) 1228 1229 #if TARGET_LONG_BITS == 64 1230 # define dup_const_tl dup_const 1231 #else 1232 # define dup_const_tl(VECE, C) \ 1233 (__builtin_constant_p(VECE) \ 1234 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1235 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1236 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1237 : (qemu_build_not_reached_always(), 0)) \ 1238 : (target_long)dup_const(VECE, C)) 1239 #endif 1240 1241 #ifdef CONFIG_DEBUG_TCG 1242 void tcg_assert_listed_vecop(TCGOpcode); 1243 #else 1244 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1245 #endif 1246 1247 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1248 { 1249 #ifdef CONFIG_DEBUG_TCG 1250 const TCGOpcode *o = tcg_ctx->vecop_list; 1251 tcg_ctx->vecop_list = n; 1252 return o; 1253 #else 1254 return NULL; 1255 #endif 1256 } 1257 1258 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1259 1260 #endif /* TCG_H */ 1261