1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 38 /* XXX: make safe guess about sizes */ 39 #define MAX_OP_PER_INSTR 266 40 41 #if HOST_LONG_BITS == 32 42 #define MAX_OPC_PARAM_PER_ARG 2 43 #else 44 #define MAX_OPC_PARAM_PER_ARG 1 45 #endif 46 #define MAX_OPC_PARAM_IARGS 6 47 #define MAX_OPC_PARAM_OARGS 1 48 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) 49 50 /* A Call op needs up to 4 + 2N parameters on 32-bit archs, 51 * and up to 4 + N parameters on 64-bit archs 52 * (N = number of input arguments + output arguments). */ 53 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) 54 55 #define CPU_TEMP_BUF_NLONGS 128 56 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 57 58 /* Default target word size to pointer size. */ 59 #ifndef TCG_TARGET_REG_BITS 60 # if UINTPTR_MAX == UINT32_MAX 61 # define TCG_TARGET_REG_BITS 32 62 # elif UINTPTR_MAX == UINT64_MAX 63 # define TCG_TARGET_REG_BITS 64 64 # else 65 # error Unknown pointer size for tcg target 66 # endif 67 #endif 68 69 #if TCG_TARGET_REG_BITS == 32 70 typedef int32_t tcg_target_long; 71 typedef uint32_t tcg_target_ulong; 72 #define TCG_PRIlx PRIx32 73 #define TCG_PRIld PRId32 74 #elif TCG_TARGET_REG_BITS == 64 75 typedef int64_t tcg_target_long; 76 typedef uint64_t tcg_target_ulong; 77 #define TCG_PRIlx PRIx64 78 #define TCG_PRIld PRId64 79 #else 80 #error unsupported 81 #endif 82 83 /* Oversized TCG guests make things like MTTCG hard 84 * as we can't use atomics for cputlb updates. 85 */ 86 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 87 #define TCG_OVERSIZED_GUEST 1 88 #else 89 #define TCG_OVERSIZED_GUEST 0 90 #endif 91 92 #if TCG_TARGET_NB_REGS <= 32 93 typedef uint32_t TCGRegSet; 94 #elif TCG_TARGET_NB_REGS <= 64 95 typedef uint64_t TCGRegSet; 96 #else 97 #error unsupported 98 #endif 99 100 #if TCG_TARGET_REG_BITS == 32 101 /* Turn some undef macros into false macros. */ 102 #define TCG_TARGET_HAS_extrl_i64_i32 0 103 #define TCG_TARGET_HAS_extrh_i64_i32 0 104 #define TCG_TARGET_HAS_div_i64 0 105 #define TCG_TARGET_HAS_rem_i64 0 106 #define TCG_TARGET_HAS_div2_i64 0 107 #define TCG_TARGET_HAS_rot_i64 0 108 #define TCG_TARGET_HAS_ext8s_i64 0 109 #define TCG_TARGET_HAS_ext16s_i64 0 110 #define TCG_TARGET_HAS_ext32s_i64 0 111 #define TCG_TARGET_HAS_ext8u_i64 0 112 #define TCG_TARGET_HAS_ext16u_i64 0 113 #define TCG_TARGET_HAS_ext32u_i64 0 114 #define TCG_TARGET_HAS_bswap16_i64 0 115 #define TCG_TARGET_HAS_bswap32_i64 0 116 #define TCG_TARGET_HAS_bswap64_i64 0 117 #define TCG_TARGET_HAS_neg_i64 0 118 #define TCG_TARGET_HAS_not_i64 0 119 #define TCG_TARGET_HAS_andc_i64 0 120 #define TCG_TARGET_HAS_orc_i64 0 121 #define TCG_TARGET_HAS_eqv_i64 0 122 #define TCG_TARGET_HAS_nand_i64 0 123 #define TCG_TARGET_HAS_nor_i64 0 124 #define TCG_TARGET_HAS_clz_i64 0 125 #define TCG_TARGET_HAS_ctz_i64 0 126 #define TCG_TARGET_HAS_ctpop_i64 0 127 #define TCG_TARGET_HAS_deposit_i64 0 128 #define TCG_TARGET_HAS_extract_i64 0 129 #define TCG_TARGET_HAS_sextract_i64 0 130 #define TCG_TARGET_HAS_extract2_i64 0 131 #define TCG_TARGET_HAS_movcond_i64 0 132 #define TCG_TARGET_HAS_add2_i64 0 133 #define TCG_TARGET_HAS_sub2_i64 0 134 #define TCG_TARGET_HAS_mulu2_i64 0 135 #define TCG_TARGET_HAS_muls2_i64 0 136 #define TCG_TARGET_HAS_muluh_i64 0 137 #define TCG_TARGET_HAS_mulsh_i64 0 138 /* Turn some undef macros into true macros. */ 139 #define TCG_TARGET_HAS_add2_i32 1 140 #define TCG_TARGET_HAS_sub2_i32 1 141 #endif 142 143 #ifndef TCG_TARGET_deposit_i32_valid 144 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 145 #endif 146 #ifndef TCG_TARGET_deposit_i64_valid 147 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 148 #endif 149 #ifndef TCG_TARGET_extract_i32_valid 150 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 151 #endif 152 #ifndef TCG_TARGET_extract_i64_valid 153 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 154 #endif 155 156 /* Only one of DIV or DIV2 should be defined. */ 157 #if defined(TCG_TARGET_HAS_div_i32) 158 #define TCG_TARGET_HAS_div2_i32 0 159 #elif defined(TCG_TARGET_HAS_div2_i32) 160 #define TCG_TARGET_HAS_div_i32 0 161 #define TCG_TARGET_HAS_rem_i32 0 162 #endif 163 #if defined(TCG_TARGET_HAS_div_i64) 164 #define TCG_TARGET_HAS_div2_i64 0 165 #elif defined(TCG_TARGET_HAS_div2_i64) 166 #define TCG_TARGET_HAS_div_i64 0 167 #define TCG_TARGET_HAS_rem_i64 0 168 #endif 169 170 /* For 32-bit targets, some sort of unsigned widening multiply is required. */ 171 #if TCG_TARGET_REG_BITS == 32 \ 172 && !(defined(TCG_TARGET_HAS_mulu2_i32) \ 173 || defined(TCG_TARGET_HAS_muluh_i32)) 174 # error "Missing unsigned widening multiply" 175 #endif 176 177 #if !defined(TCG_TARGET_HAS_v64) \ 178 && !defined(TCG_TARGET_HAS_v128) \ 179 && !defined(TCG_TARGET_HAS_v256) 180 #define TCG_TARGET_MAYBE_vec 0 181 #define TCG_TARGET_HAS_abs_vec 0 182 #define TCG_TARGET_HAS_neg_vec 0 183 #define TCG_TARGET_HAS_not_vec 0 184 #define TCG_TARGET_HAS_andc_vec 0 185 #define TCG_TARGET_HAS_orc_vec 0 186 #define TCG_TARGET_HAS_roti_vec 0 187 #define TCG_TARGET_HAS_rots_vec 0 188 #define TCG_TARGET_HAS_rotv_vec 0 189 #define TCG_TARGET_HAS_shi_vec 0 190 #define TCG_TARGET_HAS_shs_vec 0 191 #define TCG_TARGET_HAS_shv_vec 0 192 #define TCG_TARGET_HAS_mul_vec 0 193 #define TCG_TARGET_HAS_sat_vec 0 194 #define TCG_TARGET_HAS_minmax_vec 0 195 #define TCG_TARGET_HAS_bitsel_vec 0 196 #define TCG_TARGET_HAS_cmpsel_vec 0 197 #else 198 #define TCG_TARGET_MAYBE_vec 1 199 #endif 200 #ifndef TCG_TARGET_HAS_v64 201 #define TCG_TARGET_HAS_v64 0 202 #endif 203 #ifndef TCG_TARGET_HAS_v128 204 #define TCG_TARGET_HAS_v128 0 205 #endif 206 #ifndef TCG_TARGET_HAS_v256 207 #define TCG_TARGET_HAS_v256 0 208 #endif 209 210 #ifndef TARGET_INSN_START_EXTRA_WORDS 211 # define TARGET_INSN_START_WORDS 1 212 #else 213 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 214 #endif 215 216 typedef enum TCGOpcode { 217 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 218 #include "tcg/tcg-opc.h" 219 #undef DEF 220 NB_OPS, 221 } TCGOpcode; 222 223 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 224 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 225 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 226 227 #ifndef TCG_TARGET_INSN_UNIT_SIZE 228 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 229 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 230 typedef uint8_t tcg_insn_unit; 231 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 232 typedef uint16_t tcg_insn_unit; 233 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 234 typedef uint32_t tcg_insn_unit; 235 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 236 typedef uint64_t tcg_insn_unit; 237 #else 238 /* The port better have done this. */ 239 #endif 240 241 242 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS 243 # define tcg_debug_assert(X) do { assert(X); } while (0) 244 #else 245 # define tcg_debug_assert(X) \ 246 do { if (!(X)) { __builtin_unreachable(); } } while (0) 247 #endif 248 249 typedef struct TCGRelocation TCGRelocation; 250 struct TCGRelocation { 251 QSIMPLEQ_ENTRY(TCGRelocation) next; 252 tcg_insn_unit *ptr; 253 intptr_t addend; 254 int type; 255 }; 256 257 typedef struct TCGLabel TCGLabel; 258 struct TCGLabel { 259 unsigned present : 1; 260 unsigned has_value : 1; 261 unsigned id : 14; 262 unsigned refs : 16; 263 union { 264 uintptr_t value; 265 const tcg_insn_unit *value_ptr; 266 } u; 267 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 268 QSIMPLEQ_ENTRY(TCGLabel) next; 269 }; 270 271 typedef struct TCGPool { 272 struct TCGPool *next; 273 int size; 274 uint8_t data[] __attribute__ ((aligned)); 275 } TCGPool; 276 277 #define TCG_POOL_CHUNK_SIZE 32768 278 279 #define TCG_MAX_TEMPS 512 280 #define TCG_MAX_INSNS 512 281 282 /* when the size of the arguments of a called function is smaller than 283 this value, they are statically allocated in the TB stack frame */ 284 #define TCG_STATIC_CALL_ARGS_SIZE 128 285 286 typedef enum TCGType { 287 TCG_TYPE_I32, 288 TCG_TYPE_I64, 289 290 TCG_TYPE_V64, 291 TCG_TYPE_V128, 292 TCG_TYPE_V256, 293 294 TCG_TYPE_COUNT, /* number of different types */ 295 296 /* An alias for the size of the host register. */ 297 #if TCG_TARGET_REG_BITS == 32 298 TCG_TYPE_REG = TCG_TYPE_I32, 299 #else 300 TCG_TYPE_REG = TCG_TYPE_I64, 301 #endif 302 303 /* An alias for the size of the native pointer. */ 304 #if UINTPTR_MAX == UINT32_MAX 305 TCG_TYPE_PTR = TCG_TYPE_I32, 306 #else 307 TCG_TYPE_PTR = TCG_TYPE_I64, 308 #endif 309 310 /* An alias for the size of the target "long", aka register. */ 311 #if TARGET_LONG_BITS == 64 312 TCG_TYPE_TL = TCG_TYPE_I64, 313 #else 314 TCG_TYPE_TL = TCG_TYPE_I32, 315 #endif 316 } TCGType; 317 318 /** 319 * get_alignment_bits 320 * @memop: MemOp value 321 * 322 * Extract the alignment size from the memop. 323 */ 324 static inline unsigned get_alignment_bits(MemOp memop) 325 { 326 unsigned a = memop & MO_AMASK; 327 328 if (a == MO_UNALN) { 329 /* No alignment required. */ 330 a = 0; 331 } else if (a == MO_ALIGN) { 332 /* A natural alignment requirement. */ 333 a = memop & MO_SIZE; 334 } else { 335 /* A specific alignment requirement. */ 336 a = a >> MO_ASHIFT; 337 } 338 #if defined(CONFIG_SOFTMMU) 339 /* The requested alignment cannot overlap the TLB flags. */ 340 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 341 #endif 342 return a; 343 } 344 345 typedef tcg_target_ulong TCGArg; 346 347 /* Define type and accessor macros for TCG variables. 348 349 TCG variables are the inputs and outputs of TCG ops, as described 350 in tcg/README. Target CPU front-end code uses these types to deal 351 with TCG variables as it emits TCG code via the tcg_gen_* functions. 352 They come in several flavours: 353 * TCGv_i32 : 32 bit integer type 354 * TCGv_i64 : 64 bit integer type 355 * TCGv_ptr : a host pointer type 356 * TCGv_vec : a host vector type; the exact size is not exposed 357 to the CPU front-end code. 358 * TCGv : an integer type the same size as target_ulong 359 (an alias for either TCGv_i32 or TCGv_i64) 360 The compiler's type checking will complain if you mix them 361 up and pass the wrong sized TCGv to a function. 362 363 Users of tcg_gen_* don't need to know about any of the internal 364 details of these, and should treat them as opaque types. 365 You won't be able to look inside them in a debugger either. 366 367 Internal implementation details follow: 368 369 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 370 This is deliberate, because the values we store in variables of type 371 TCGv_i32 are not really pointers-to-structures. They're just small 372 integers, but keeping them in pointer types like this means that the 373 compiler will complain if you accidentally pass a TCGv_i32 to a 374 function which takes a TCGv_i64, and so on. Only the internals of 375 TCG need to care about the actual contents of the types. */ 376 377 typedef struct TCGv_i32_d *TCGv_i32; 378 typedef struct TCGv_i64_d *TCGv_i64; 379 typedef struct TCGv_ptr_d *TCGv_ptr; 380 typedef struct TCGv_vec_d *TCGv_vec; 381 typedef TCGv_ptr TCGv_env; 382 #if TARGET_LONG_BITS == 32 383 #define TCGv TCGv_i32 384 #elif TARGET_LONG_BITS == 64 385 #define TCGv TCGv_i64 386 #else 387 #error Unhandled TARGET_LONG_BITS value 388 #endif 389 390 /* call flags */ 391 /* Helper does not read globals (either directly or through an exception). It 392 implies TCG_CALL_NO_WRITE_GLOBALS. */ 393 #define TCG_CALL_NO_READ_GLOBALS 0x0001 394 /* Helper does not write globals */ 395 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 396 /* Helper can be safely suppressed if the return value is not used. */ 397 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 398 /* Helper is QEMU_NORETURN. */ 399 #define TCG_CALL_NO_RETURN 0x0008 400 401 /* convenience version of most used call flags */ 402 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 403 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 404 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 405 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 406 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 407 408 /* Used to align parameters. See the comment before tcgv_i32_temp. */ 409 #define TCG_CALL_DUMMY_ARG ((TCGArg)0) 410 411 /* 412 * Flags for the bswap opcodes. 413 * If IZ, the input is zero-extended, otherwise unknown. 414 * If OZ or OS, the output is zero- or sign-extended respectively, 415 * otherwise the high bits are undefined. 416 */ 417 enum { 418 TCG_BSWAP_IZ = 1, 419 TCG_BSWAP_OZ = 2, 420 TCG_BSWAP_OS = 4, 421 }; 422 423 typedef enum TCGTempVal { 424 TEMP_VAL_DEAD, 425 TEMP_VAL_REG, 426 TEMP_VAL_MEM, 427 TEMP_VAL_CONST, 428 } TCGTempVal; 429 430 typedef enum TCGTempKind { 431 /* Temp is dead at the end of all basic blocks. */ 432 TEMP_NORMAL, 433 /* Temp is saved across basic blocks but dead at the end of TBs. */ 434 TEMP_LOCAL, 435 /* Temp is saved across both basic blocks and translation blocks. */ 436 TEMP_GLOBAL, 437 /* Temp is in a fixed register. */ 438 TEMP_FIXED, 439 /* Temp is a fixed constant. */ 440 TEMP_CONST, 441 } TCGTempKind; 442 443 typedef struct TCGTemp { 444 TCGReg reg:8; 445 TCGTempVal val_type:8; 446 TCGType base_type:8; 447 TCGType type:8; 448 TCGTempKind kind:3; 449 unsigned int indirect_reg:1; 450 unsigned int indirect_base:1; 451 unsigned int mem_coherent:1; 452 unsigned int mem_allocated:1; 453 unsigned int temp_allocated:1; 454 455 int64_t val; 456 struct TCGTemp *mem_base; 457 intptr_t mem_offset; 458 const char *name; 459 460 /* Pass-specific information that can be stored for a temporary. 461 One word worth of integer data, and one pointer to data 462 allocated separately. */ 463 uintptr_t state; 464 void *state_ptr; 465 } TCGTemp; 466 467 typedef struct TCGContext TCGContext; 468 469 typedef struct TCGTempSet { 470 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 471 } TCGTempSet; 472 473 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, 474 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. 475 There are never more than 2 outputs, which means that we can store all 476 dead + sync data within 16 bits. */ 477 #define DEAD_ARG 4 478 #define SYNC_ARG 1 479 typedef uint16_t TCGLifeData; 480 481 /* The layout here is designed to avoid a bitfield crossing of 482 a 32-bit boundary, which would cause GCC to add extra padding. */ 483 typedef struct TCGOp { 484 TCGOpcode opc : 8; /* 8 */ 485 486 /* Parameters for this opcode. See below. */ 487 unsigned param1 : 4; /* 12 */ 488 unsigned param2 : 4; /* 16 */ 489 490 /* Lifetime data of the operands. */ 491 unsigned life : 16; /* 32 */ 492 493 /* Next and previous opcodes. */ 494 QTAILQ_ENTRY(TCGOp) link; 495 496 /* Arguments for the opcode. */ 497 TCGArg args[MAX_OPC_PARAM]; 498 499 /* Register preferences for the output(s). */ 500 TCGRegSet output_pref[2]; 501 } TCGOp; 502 503 #define TCGOP_CALLI(X) (X)->param1 504 #define TCGOP_CALLO(X) (X)->param2 505 506 #define TCGOP_VECL(X) (X)->param1 507 #define TCGOP_VECE(X) (X)->param2 508 509 /* Make sure operands fit in the bitfields above. */ 510 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 511 512 typedef struct TCGProfile { 513 int64_t cpu_exec_time; 514 int64_t tb_count1; 515 int64_t tb_count; 516 int64_t op_count; /* total insn count */ 517 int op_count_max; /* max insn per TB */ 518 int temp_count_max; 519 int64_t temp_count; 520 int64_t del_op_count; 521 int64_t code_in_len; 522 int64_t code_out_len; 523 int64_t search_out_len; 524 int64_t interm_time; 525 int64_t code_time; 526 int64_t la_time; 527 int64_t opt_time; 528 int64_t restore_count; 529 int64_t restore_time; 530 int64_t table_op_count[NB_OPS]; 531 } TCGProfile; 532 533 struct TCGContext { 534 uint8_t *pool_cur, *pool_end; 535 TCGPool *pool_first, *pool_current, *pool_first_large; 536 int nb_labels; 537 int nb_globals; 538 int nb_temps; 539 int nb_indirects; 540 int nb_ops; 541 542 /* goto_tb support */ 543 tcg_insn_unit *code_buf; 544 uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ 545 uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ 546 uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ 547 548 TCGRegSet reserved_regs; 549 uint32_t tb_cflags; /* cflags of the current TB */ 550 intptr_t current_frame_offset; 551 intptr_t frame_start; 552 intptr_t frame_end; 553 TCGTemp *frame_temp; 554 555 tcg_insn_unit *code_ptr; 556 557 #ifdef CONFIG_PROFILER 558 TCGProfile prof; 559 #endif 560 561 #ifdef CONFIG_DEBUG_TCG 562 int temps_in_use; 563 int goto_tb_issue_mask; 564 const TCGOpcode *vecop_list; 565 #endif 566 567 /* Code generation. Note that we specifically do not use tcg_insn_unit 568 here, because there's too much arithmetic throughout that relies 569 on addition and subtraction working on bytes. Rely on the GCC 570 extension that allows arithmetic on void*. */ 571 void *code_gen_buffer; 572 size_t code_gen_buffer_size; 573 void *code_gen_ptr; 574 void *data_gen_ptr; 575 576 /* Threshold to flush the translated code buffer. */ 577 void *code_gen_highwater; 578 579 /* Track which vCPU triggers events */ 580 CPUState *cpu; /* *_trans */ 581 582 /* These structures are private to tcg-target.c.inc. */ 583 #ifdef TCG_TARGET_NEED_LDST_LABELS 584 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 585 #endif 586 #ifdef TCG_TARGET_NEED_POOL_LABELS 587 struct TCGLabelPoolData *pool_labels; 588 #endif 589 590 TCGLabel *exitreq_label; 591 592 #ifdef CONFIG_PLUGIN 593 /* 594 * We keep one plugin_tb struct per TCGContext. Note that on every TB 595 * translation we clear but do not free its contents; this way we 596 * avoid a lot of malloc/free churn, since after a few TB's it's 597 * unlikely that we'll need to allocate either more instructions or more 598 * space for instructions (for variable-instruction-length ISAs). 599 */ 600 struct qemu_plugin_tb *plugin_tb; 601 602 /* descriptor of the instruction being translated */ 603 struct qemu_plugin_insn *plugin_insn; 604 #endif 605 606 GHashTable *const_table[TCG_TYPE_COUNT]; 607 TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; 608 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 609 610 QTAILQ_HEAD(, TCGOp) ops, free_ops; 611 QSIMPLEQ_HEAD(, TCGLabel) labels; 612 613 /* Tells which temporary holds a given register. 614 It does not take into account fixed registers */ 615 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 616 617 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 618 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 619 620 /* Exit to translator on overflow. */ 621 sigjmp_buf jmp_trans; 622 }; 623 624 static inline bool temp_readonly(TCGTemp *ts) 625 { 626 return ts->kind >= TEMP_FIXED; 627 } 628 629 extern __thread TCGContext *tcg_ctx; 630 extern const void *tcg_code_gen_epilogue; 631 extern uintptr_t tcg_splitwx_diff; 632 extern TCGv_env cpu_env; 633 634 bool in_code_gen_buffer(const void *p); 635 636 #ifdef CONFIG_DEBUG_TCG 637 const void *tcg_splitwx_to_rx(void *rw); 638 void *tcg_splitwx_to_rw(const void *rx); 639 #else 640 static inline const void *tcg_splitwx_to_rx(void *rw) 641 { 642 return rw ? rw + tcg_splitwx_diff : NULL; 643 } 644 645 static inline void *tcg_splitwx_to_rw(const void *rx) 646 { 647 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 648 } 649 #endif 650 651 static inline size_t temp_idx(TCGTemp *ts) 652 { 653 ptrdiff_t n = ts - tcg_ctx->temps; 654 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 655 return n; 656 } 657 658 static inline TCGArg temp_arg(TCGTemp *ts) 659 { 660 return (uintptr_t)ts; 661 } 662 663 static inline TCGTemp *arg_temp(TCGArg a) 664 { 665 return (TCGTemp *)(uintptr_t)a; 666 } 667 668 /* Using the offset of a temporary, relative to TCGContext, rather than 669 its index means that we don't use 0. That leaves offset 0 free for 670 a NULL representation without having to leave index 0 unused. */ 671 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 672 { 673 uintptr_t o = (uintptr_t)v; 674 TCGTemp *t = (void *)tcg_ctx + o; 675 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 676 return t; 677 } 678 679 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 680 { 681 return tcgv_i32_temp((TCGv_i32)v); 682 } 683 684 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 685 { 686 return tcgv_i32_temp((TCGv_i32)v); 687 } 688 689 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 690 { 691 return tcgv_i32_temp((TCGv_i32)v); 692 } 693 694 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 695 { 696 return temp_arg(tcgv_i32_temp(v)); 697 } 698 699 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 700 { 701 return temp_arg(tcgv_i64_temp(v)); 702 } 703 704 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 705 { 706 return temp_arg(tcgv_ptr_temp(v)); 707 } 708 709 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 710 { 711 return temp_arg(tcgv_vec_temp(v)); 712 } 713 714 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 715 { 716 (void)temp_idx(t); /* trigger embedded assert */ 717 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 718 } 719 720 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 721 { 722 return (TCGv_i64)temp_tcgv_i32(t); 723 } 724 725 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 726 { 727 return (TCGv_ptr)temp_tcgv_i32(t); 728 } 729 730 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 731 { 732 return (TCGv_vec)temp_tcgv_i32(t); 733 } 734 735 #if TCG_TARGET_REG_BITS == 32 736 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) 737 { 738 return temp_tcgv_i32(tcgv_i64_temp(t)); 739 } 740 741 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) 742 { 743 return temp_tcgv_i32(tcgv_i64_temp(t) + 1); 744 } 745 #endif 746 747 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 748 { 749 return op->args[arg]; 750 } 751 752 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 753 { 754 op->args[arg] = v; 755 } 756 757 static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) 758 { 759 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 760 return tcg_get_insn_param(op, arg); 761 #else 762 return tcg_get_insn_param(op, arg * 2) | 763 ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); 764 #endif 765 } 766 767 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) 768 { 769 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 770 tcg_set_insn_param(op, arg, v); 771 #else 772 tcg_set_insn_param(op, arg * 2, v); 773 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 774 #endif 775 } 776 777 /* The last op that was emitted. */ 778 static inline TCGOp *tcg_last_op(void) 779 { 780 return QTAILQ_LAST(&tcg_ctx->ops); 781 } 782 783 /* Test for whether to terminate the TB for using too many opcodes. */ 784 static inline bool tcg_op_buf_full(void) 785 { 786 /* This is not a hard limit, it merely stops translation when 787 * we have produced "enough" opcodes. We want to limit TB size 788 * such that a RISC host can reasonably use a 16-bit signed 789 * branch within the TB. We also need to be mindful of the 790 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 791 * and TCGContext.gen_insn_end_off[]. 792 */ 793 return tcg_ctx->nb_ops >= 4000; 794 } 795 796 /* pool based memory allocation */ 797 798 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 799 void *tcg_malloc_internal(TCGContext *s, int size); 800 void tcg_pool_reset(TCGContext *s); 801 TranslationBlock *tcg_tb_alloc(TCGContext *s); 802 803 void tcg_region_reset_all(void); 804 805 size_t tcg_code_size(void); 806 size_t tcg_code_capacity(void); 807 808 void tcg_tb_insert(TranslationBlock *tb); 809 void tcg_tb_remove(TranslationBlock *tb); 810 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 811 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 812 size_t tcg_nb_tbs(void); 813 814 /* user-mode: Called with mmap_lock held. */ 815 static inline void *tcg_malloc(int size) 816 { 817 TCGContext *s = tcg_ctx; 818 uint8_t *ptr, *ptr_end; 819 820 /* ??? This is a weak placeholder for minimum malloc alignment. */ 821 size = QEMU_ALIGN_UP(size, 8); 822 823 ptr = s->pool_cur; 824 ptr_end = ptr + size; 825 if (unlikely(ptr_end > s->pool_end)) { 826 return tcg_malloc_internal(tcg_ctx, size); 827 } else { 828 s->pool_cur = ptr_end; 829 return ptr; 830 } 831 } 832 833 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 834 void tcg_register_thread(void); 835 void tcg_prologue_init(TCGContext *s); 836 void tcg_func_start(TCGContext *s); 837 838 int tcg_gen_code(TCGContext *s, TranslationBlock *tb); 839 840 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 841 842 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 843 intptr_t, const char *); 844 TCGTemp *tcg_temp_new_internal(TCGType, bool); 845 void tcg_temp_free_internal(TCGTemp *); 846 TCGv_vec tcg_temp_new_vec(TCGType type); 847 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 848 849 static inline void tcg_temp_free_i32(TCGv_i32 arg) 850 { 851 tcg_temp_free_internal(tcgv_i32_temp(arg)); 852 } 853 854 static inline void tcg_temp_free_i64(TCGv_i64 arg) 855 { 856 tcg_temp_free_internal(tcgv_i64_temp(arg)); 857 } 858 859 static inline void tcg_temp_free_ptr(TCGv_ptr arg) 860 { 861 tcg_temp_free_internal(tcgv_ptr_temp(arg)); 862 } 863 864 static inline void tcg_temp_free_vec(TCGv_vec arg) 865 { 866 tcg_temp_free_internal(tcgv_vec_temp(arg)); 867 } 868 869 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 870 const char *name) 871 { 872 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 873 return temp_tcgv_i32(t); 874 } 875 876 static inline TCGv_i32 tcg_temp_new_i32(void) 877 { 878 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); 879 return temp_tcgv_i32(t); 880 } 881 882 static inline TCGv_i32 tcg_temp_local_new_i32(void) 883 { 884 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); 885 return temp_tcgv_i32(t); 886 } 887 888 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 889 const char *name) 890 { 891 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 892 return temp_tcgv_i64(t); 893 } 894 895 static inline TCGv_i64 tcg_temp_new_i64(void) 896 { 897 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); 898 return temp_tcgv_i64(t); 899 } 900 901 static inline TCGv_i64 tcg_temp_local_new_i64(void) 902 { 903 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); 904 return temp_tcgv_i64(t); 905 } 906 907 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 908 const char *name) 909 { 910 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 911 return temp_tcgv_ptr(t); 912 } 913 914 static inline TCGv_ptr tcg_temp_new_ptr(void) 915 { 916 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); 917 return temp_tcgv_ptr(t); 918 } 919 920 static inline TCGv_ptr tcg_temp_local_new_ptr(void) 921 { 922 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); 923 return temp_tcgv_ptr(t); 924 } 925 926 #if defined(CONFIG_DEBUG_TCG) 927 /* If you call tcg_clear_temp_count() at the start of a section of 928 * code which is not supposed to leak any TCG temporaries, then 929 * calling tcg_check_temp_count() at the end of the section will 930 * return 1 if the section did in fact leak a temporary. 931 */ 932 void tcg_clear_temp_count(void); 933 int tcg_check_temp_count(void); 934 #else 935 #define tcg_clear_temp_count() do { } while (0) 936 #define tcg_check_temp_count() 0 937 #endif 938 939 int64_t tcg_cpu_exec_time(void); 940 void tcg_dump_info(GString *buf); 941 void tcg_dump_op_count(GString *buf); 942 943 #define TCG_CT_CONST 1 /* any constant of register size */ 944 945 typedef struct TCGArgConstraint { 946 unsigned ct : 16; 947 unsigned alias_index : 4; 948 unsigned sort_index : 4; 949 bool oalias : 1; 950 bool ialias : 1; 951 bool newreg : 1; 952 TCGRegSet regs; 953 } TCGArgConstraint; 954 955 #define TCG_MAX_OP_ARGS 16 956 957 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 958 enum { 959 /* Instruction exits the translation block. */ 960 TCG_OPF_BB_EXIT = 0x01, 961 /* Instruction defines the end of a basic block. */ 962 TCG_OPF_BB_END = 0x02, 963 /* Instruction clobbers call registers and potentially update globals. */ 964 TCG_OPF_CALL_CLOBBER = 0x04, 965 /* Instruction has side effects: it cannot be removed if its outputs 966 are not used, and might trigger exceptions. */ 967 TCG_OPF_SIDE_EFFECTS = 0x08, 968 /* Instruction operands are 64-bits (otherwise 32-bits). */ 969 TCG_OPF_64BIT = 0x10, 970 /* Instruction is optional and not implemented by the host, or insn 971 is generic and should not be implemened by the host. */ 972 TCG_OPF_NOT_PRESENT = 0x20, 973 /* Instruction operands are vectors. */ 974 TCG_OPF_VECTOR = 0x40, 975 /* Instruction is a conditional branch. */ 976 TCG_OPF_COND_BRANCH = 0x80 977 }; 978 979 typedef struct TCGOpDef { 980 const char *name; 981 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 982 uint8_t flags; 983 TCGArgConstraint *args_ct; 984 } TCGOpDef; 985 986 extern TCGOpDef tcg_op_defs[]; 987 extern const size_t tcg_op_defs_max; 988 989 typedef struct TCGTargetOpDef { 990 TCGOpcode op; 991 const char *args_ct_str[TCG_MAX_OP_ARGS]; 992 } TCGTargetOpDef; 993 994 #define tcg_abort() \ 995 do {\ 996 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ 997 abort();\ 998 } while (0) 999 1000 bool tcg_op_supported(TCGOpcode op); 1001 1002 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 1003 1004 TCGOp *tcg_emit_op(TCGOpcode opc); 1005 void tcg_op_remove(TCGContext *s, TCGOp *op); 1006 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc); 1007 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); 1008 1009 /** 1010 * tcg_remove_ops_after: 1011 * @op: target operation 1012 * 1013 * Discard any opcodes emitted since @op. Expected usage is to save 1014 * a starting point with tcg_last_op(), speculatively emit opcodes, 1015 * then decide whether or not to keep those opcodes after the fact. 1016 */ 1017 void tcg_remove_ops_after(TCGOp *op); 1018 1019 void tcg_optimize(TCGContext *s); 1020 1021 /* Allocate a new temporary and initialize it with a constant. */ 1022 TCGv_i32 tcg_const_i32(int32_t val); 1023 TCGv_i64 tcg_const_i64(int64_t val); 1024 TCGv_i32 tcg_const_local_i32(int32_t val); 1025 TCGv_i64 tcg_const_local_i64(int64_t val); 1026 TCGv_vec tcg_const_zeros_vec(TCGType); 1027 TCGv_vec tcg_const_ones_vec(TCGType); 1028 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); 1029 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); 1030 1031 /* 1032 * Locate or create a read-only temporary that is a constant. 1033 * This kind of temporary need not be freed, but for convenience 1034 * will be silently ignored by tcg_temp_free_*. 1035 */ 1036 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 1037 1038 static inline TCGv_i32 tcg_constant_i32(int32_t val) 1039 { 1040 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 1041 } 1042 1043 static inline TCGv_i64 tcg_constant_i64(int64_t val) 1044 { 1045 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1046 } 1047 1048 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1049 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1050 1051 #if UINTPTR_MAX == UINT32_MAX 1052 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) 1053 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) 1054 #else 1055 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) 1056 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) 1057 #endif 1058 1059 TCGLabel *gen_new_label(void); 1060 1061 /** 1062 * label_arg 1063 * @l: label 1064 * 1065 * Encode a label for storage in the TCG opcode stream. 1066 */ 1067 1068 static inline TCGArg label_arg(TCGLabel *l) 1069 { 1070 return (uintptr_t)l; 1071 } 1072 1073 /** 1074 * arg_label 1075 * @i: value 1076 * 1077 * The opposite of label_arg. Retrieve a label from the 1078 * encoding of the TCG opcode stream. 1079 */ 1080 1081 static inline TCGLabel *arg_label(TCGArg i) 1082 { 1083 return (TCGLabel *)(uintptr_t)i; 1084 } 1085 1086 /** 1087 * tcg_ptr_byte_diff 1088 * @a, @b: addresses to be differenced 1089 * 1090 * There are many places within the TCG backends where we need a byte 1091 * difference between two pointers. While this can be accomplished 1092 * with local casting, it's easy to get wrong -- especially if one is 1093 * concerned with the signedness of the result. 1094 * 1095 * This version relies on GCC's void pointer arithmetic to get the 1096 * correct result. 1097 */ 1098 1099 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1100 { 1101 return a - b; 1102 } 1103 1104 /** 1105 * tcg_pcrel_diff 1106 * @s: the tcg context 1107 * @target: address of the target 1108 * 1109 * Produce a pc-relative difference, from the current code_ptr 1110 * to the destination address. 1111 */ 1112 1113 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1114 { 1115 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1116 } 1117 1118 /** 1119 * tcg_tbrel_diff 1120 * @s: the tcg context 1121 * @target: address of the target 1122 * 1123 * Produce a difference, from the beginning of the current TB code 1124 * to the destination address. 1125 */ 1126 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1127 { 1128 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1129 } 1130 1131 /** 1132 * tcg_current_code_size 1133 * @s: the tcg context 1134 * 1135 * Compute the current code size within the translation block. 1136 * This is used to fill in qemu's data structures for goto_tb. 1137 */ 1138 1139 static inline size_t tcg_current_code_size(TCGContext *s) 1140 { 1141 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1142 } 1143 1144 /** 1145 * tcg_qemu_tb_exec: 1146 * @env: pointer to CPUArchState for the CPU 1147 * @tb_ptr: address of generated code for the TB to execute 1148 * 1149 * Start executing code from a given translation block. 1150 * Where translation blocks have been linked, execution 1151 * may proceed from the given TB into successive ones. 1152 * Control eventually returns only when some action is needed 1153 * from the top-level loop: either control must pass to a TB 1154 * which has not yet been directly linked, or an asynchronous 1155 * event such as an interrupt needs handling. 1156 * 1157 * Return: The return value is the value passed to the corresponding 1158 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1159 * The value is either zero or a 4-byte aligned pointer to that TB combined 1160 * with additional information in its two least significant bits. The 1161 * additional information is encoded as follows: 1162 * 0, 1: the link between this TB and the next is via the specified 1163 * TB index (0 or 1). That is, we left the TB via (the equivalent 1164 * of) "goto_tb <index>". The main loop uses this to determine 1165 * how to link the TB just executed to the next. 1166 * 2: we are using instruction counting code generation, and we 1167 * did not start executing this TB because the instruction counter 1168 * would hit zero midway through it. In this case the pointer 1169 * returned is the TB we were about to execute, and the caller must 1170 * arrange to execute the remaining count of instructions. 1171 * 3: we stopped because the CPU's exit_request flag was set 1172 * (usually meaning that there is an interrupt that needs to be 1173 * handled). The pointer returned is the TB we were about to execute 1174 * when we noticed the pending exit request. 1175 * 1176 * If the bottom two bits indicate an exit-via-index then the CPU 1177 * state is correctly synchronised and ready for execution of the next 1178 * TB (and in particular the guest PC is the address to execute next). 1179 * Otherwise, we gave up on execution of this TB before it started, and 1180 * the caller must fix up the CPU state by calling the CPU's 1181 * synchronize_from_tb() method with the TB pointer we return (falling 1182 * back to calling the CPU's set_pc method with tb->pb if no 1183 * synchronize_from_tb() method exists). 1184 * 1185 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1186 * to this default (which just calls the prologue.code emitted by 1187 * tcg_target_qemu_prologue()). 1188 */ 1189 #define TB_EXIT_MASK 3 1190 #define TB_EXIT_IDX0 0 1191 #define TB_EXIT_IDX1 1 1192 #define TB_EXIT_IDXMAX 1 1193 #define TB_EXIT_REQUESTED 3 1194 1195 #ifdef CONFIG_TCG_INTERPRETER 1196 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1197 #else 1198 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1199 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1200 #endif 1201 1202 void tcg_register_jit(const void *buf, size_t buf_size); 1203 1204 #if TCG_TARGET_MAYBE_vec 1205 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1206 return > 0 if it is directly supportable; 1207 return < 0 if we must call tcg_expand_vec_op. */ 1208 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1209 #else 1210 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1211 { 1212 return 0; 1213 } 1214 #endif 1215 1216 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1217 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1218 1219 /* Replicate a constant C accoring to the log2 of the element size. */ 1220 uint64_t dup_const(unsigned vece, uint64_t c); 1221 1222 #define dup_const(VECE, C) \ 1223 (__builtin_constant_p(VECE) \ 1224 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1225 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1226 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1227 : (VECE) == MO_64 ? (uint64_t)(C) \ 1228 : (qemu_build_not_reached_always(), 0)) \ 1229 : dup_const(VECE, C)) 1230 1231 #if TARGET_LONG_BITS == 64 1232 # define dup_const_tl dup_const 1233 #else 1234 # define dup_const_tl(VECE, C) \ 1235 (__builtin_constant_p(VECE) \ 1236 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1237 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1238 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1239 : (qemu_build_not_reached_always(), 0)) \ 1240 : (target_long)dup_const(VECE, C)) 1241 #endif 1242 1243 #ifdef CONFIG_DEBUG_TCG 1244 void tcg_assert_listed_vecop(TCGOpcode); 1245 #else 1246 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1247 #endif 1248 1249 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1250 { 1251 #ifdef CONFIG_DEBUG_TCG 1252 const TCGOpcode *o = tcg_ctx->vecop_list; 1253 tcg_ctx->vecop_list = n; 1254 return o; 1255 #else 1256 return NULL; 1257 #endif 1258 } 1259 1260 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1261 1262 #endif /* TCG_H */ 1263