1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 38 /* XXX: make safe guess about sizes */ 39 #define MAX_OP_PER_INSTR 266 40 41 #define MAX_CALL_IARGS 7 42 43 #define CPU_TEMP_BUF_NLONGS 128 44 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 45 46 /* Default target word size to pointer size. */ 47 #ifndef TCG_TARGET_REG_BITS 48 # if UINTPTR_MAX == UINT32_MAX 49 # define TCG_TARGET_REG_BITS 32 50 # elif UINTPTR_MAX == UINT64_MAX 51 # define TCG_TARGET_REG_BITS 64 52 # else 53 # error Unknown pointer size for tcg target 54 # endif 55 #endif 56 57 #if TCG_TARGET_REG_BITS == 32 58 typedef int32_t tcg_target_long; 59 typedef uint32_t tcg_target_ulong; 60 #define TCG_PRIlx PRIx32 61 #define TCG_PRIld PRId32 62 #elif TCG_TARGET_REG_BITS == 64 63 typedef int64_t tcg_target_long; 64 typedef uint64_t tcg_target_ulong; 65 #define TCG_PRIlx PRIx64 66 #define TCG_PRIld PRId64 67 #else 68 #error unsupported 69 #endif 70 71 /* Oversized TCG guests make things like MTTCG hard 72 * as we can't use atomics for cputlb updates. 73 */ 74 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 75 #define TCG_OVERSIZED_GUEST 1 76 #else 77 #define TCG_OVERSIZED_GUEST 0 78 #endif 79 80 #if TCG_TARGET_NB_REGS <= 32 81 typedef uint32_t TCGRegSet; 82 #elif TCG_TARGET_NB_REGS <= 64 83 typedef uint64_t TCGRegSet; 84 #else 85 #error unsupported 86 #endif 87 88 #if TCG_TARGET_REG_BITS == 32 89 /* Turn some undef macros into false macros. */ 90 #define TCG_TARGET_HAS_extrl_i64_i32 0 91 #define TCG_TARGET_HAS_extrh_i64_i32 0 92 #define TCG_TARGET_HAS_div_i64 0 93 #define TCG_TARGET_HAS_rem_i64 0 94 #define TCG_TARGET_HAS_div2_i64 0 95 #define TCG_TARGET_HAS_rot_i64 0 96 #define TCG_TARGET_HAS_ext8s_i64 0 97 #define TCG_TARGET_HAS_ext16s_i64 0 98 #define TCG_TARGET_HAS_ext32s_i64 0 99 #define TCG_TARGET_HAS_ext8u_i64 0 100 #define TCG_TARGET_HAS_ext16u_i64 0 101 #define TCG_TARGET_HAS_ext32u_i64 0 102 #define TCG_TARGET_HAS_bswap16_i64 0 103 #define TCG_TARGET_HAS_bswap32_i64 0 104 #define TCG_TARGET_HAS_bswap64_i64 0 105 #define TCG_TARGET_HAS_neg_i64 0 106 #define TCG_TARGET_HAS_not_i64 0 107 #define TCG_TARGET_HAS_andc_i64 0 108 #define TCG_TARGET_HAS_orc_i64 0 109 #define TCG_TARGET_HAS_eqv_i64 0 110 #define TCG_TARGET_HAS_nand_i64 0 111 #define TCG_TARGET_HAS_nor_i64 0 112 #define TCG_TARGET_HAS_clz_i64 0 113 #define TCG_TARGET_HAS_ctz_i64 0 114 #define TCG_TARGET_HAS_ctpop_i64 0 115 #define TCG_TARGET_HAS_deposit_i64 0 116 #define TCG_TARGET_HAS_extract_i64 0 117 #define TCG_TARGET_HAS_sextract_i64 0 118 #define TCG_TARGET_HAS_extract2_i64 0 119 #define TCG_TARGET_HAS_movcond_i64 0 120 #define TCG_TARGET_HAS_add2_i64 0 121 #define TCG_TARGET_HAS_sub2_i64 0 122 #define TCG_TARGET_HAS_mulu2_i64 0 123 #define TCG_TARGET_HAS_muls2_i64 0 124 #define TCG_TARGET_HAS_muluh_i64 0 125 #define TCG_TARGET_HAS_mulsh_i64 0 126 /* Turn some undef macros into true macros. */ 127 #define TCG_TARGET_HAS_add2_i32 1 128 #define TCG_TARGET_HAS_sub2_i32 1 129 #endif 130 131 #ifndef TCG_TARGET_deposit_i32_valid 132 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 133 #endif 134 #ifndef TCG_TARGET_deposit_i64_valid 135 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 136 #endif 137 #ifndef TCG_TARGET_extract_i32_valid 138 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 139 #endif 140 #ifndef TCG_TARGET_extract_i64_valid 141 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 142 #endif 143 144 /* Only one of DIV or DIV2 should be defined. */ 145 #if defined(TCG_TARGET_HAS_div_i32) 146 #define TCG_TARGET_HAS_div2_i32 0 147 #elif defined(TCG_TARGET_HAS_div2_i32) 148 #define TCG_TARGET_HAS_div_i32 0 149 #define TCG_TARGET_HAS_rem_i32 0 150 #endif 151 #if defined(TCG_TARGET_HAS_div_i64) 152 #define TCG_TARGET_HAS_div2_i64 0 153 #elif defined(TCG_TARGET_HAS_div2_i64) 154 #define TCG_TARGET_HAS_div_i64 0 155 #define TCG_TARGET_HAS_rem_i64 0 156 #endif 157 158 #if !defined(TCG_TARGET_HAS_v64) \ 159 && !defined(TCG_TARGET_HAS_v128) \ 160 && !defined(TCG_TARGET_HAS_v256) 161 #define TCG_TARGET_MAYBE_vec 0 162 #define TCG_TARGET_HAS_abs_vec 0 163 #define TCG_TARGET_HAS_neg_vec 0 164 #define TCG_TARGET_HAS_not_vec 0 165 #define TCG_TARGET_HAS_andc_vec 0 166 #define TCG_TARGET_HAS_orc_vec 0 167 #define TCG_TARGET_HAS_nand_vec 0 168 #define TCG_TARGET_HAS_nor_vec 0 169 #define TCG_TARGET_HAS_eqv_vec 0 170 #define TCG_TARGET_HAS_roti_vec 0 171 #define TCG_TARGET_HAS_rots_vec 0 172 #define TCG_TARGET_HAS_rotv_vec 0 173 #define TCG_TARGET_HAS_shi_vec 0 174 #define TCG_TARGET_HAS_shs_vec 0 175 #define TCG_TARGET_HAS_shv_vec 0 176 #define TCG_TARGET_HAS_mul_vec 0 177 #define TCG_TARGET_HAS_sat_vec 0 178 #define TCG_TARGET_HAS_minmax_vec 0 179 #define TCG_TARGET_HAS_bitsel_vec 0 180 #define TCG_TARGET_HAS_cmpsel_vec 0 181 #else 182 #define TCG_TARGET_MAYBE_vec 1 183 #endif 184 #ifndef TCG_TARGET_HAS_v64 185 #define TCG_TARGET_HAS_v64 0 186 #endif 187 #ifndef TCG_TARGET_HAS_v128 188 #define TCG_TARGET_HAS_v128 0 189 #endif 190 #ifndef TCG_TARGET_HAS_v256 191 #define TCG_TARGET_HAS_v256 0 192 #endif 193 194 #ifndef TARGET_INSN_START_EXTRA_WORDS 195 # define TARGET_INSN_START_WORDS 1 196 #else 197 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 198 #endif 199 200 typedef enum TCGOpcode { 201 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 202 #include "tcg/tcg-opc.h" 203 #undef DEF 204 NB_OPS, 205 } TCGOpcode; 206 207 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 208 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 209 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 210 211 #ifndef TCG_TARGET_INSN_UNIT_SIZE 212 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 213 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 214 typedef uint8_t tcg_insn_unit; 215 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 216 typedef uint16_t tcg_insn_unit; 217 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 218 typedef uint32_t tcg_insn_unit; 219 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 220 typedef uint64_t tcg_insn_unit; 221 #else 222 /* The port better have done this. */ 223 #endif 224 225 226 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS 227 # define tcg_debug_assert(X) do { assert(X); } while (0) 228 #else 229 # define tcg_debug_assert(X) \ 230 do { if (!(X)) { __builtin_unreachable(); } } while (0) 231 #endif 232 233 typedef struct TCGRelocation TCGRelocation; 234 struct TCGRelocation { 235 QSIMPLEQ_ENTRY(TCGRelocation) next; 236 tcg_insn_unit *ptr; 237 intptr_t addend; 238 int type; 239 }; 240 241 typedef struct TCGOp TCGOp; 242 typedef struct TCGLabelUse TCGLabelUse; 243 struct TCGLabelUse { 244 QSIMPLEQ_ENTRY(TCGLabelUse) next; 245 TCGOp *op; 246 }; 247 248 typedef struct TCGLabel TCGLabel; 249 struct TCGLabel { 250 bool present; 251 bool has_value; 252 uint16_t id; 253 union { 254 uintptr_t value; 255 const tcg_insn_unit *value_ptr; 256 } u; 257 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 258 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 259 QSIMPLEQ_ENTRY(TCGLabel) next; 260 }; 261 262 typedef struct TCGPool { 263 struct TCGPool *next; 264 int size; 265 uint8_t data[] __attribute__ ((aligned)); 266 } TCGPool; 267 268 #define TCG_POOL_CHUNK_SIZE 32768 269 270 #define TCG_MAX_TEMPS 512 271 #define TCG_MAX_INSNS 512 272 273 /* when the size of the arguments of a called function is smaller than 274 this value, they are statically allocated in the TB stack frame */ 275 #define TCG_STATIC_CALL_ARGS_SIZE 128 276 277 typedef enum TCGType { 278 TCG_TYPE_I32, 279 TCG_TYPE_I64, 280 TCG_TYPE_I128, 281 282 TCG_TYPE_V64, 283 TCG_TYPE_V128, 284 TCG_TYPE_V256, 285 286 /* Number of different types (integer not enum) */ 287 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 288 289 /* An alias for the size of the host register. */ 290 #if TCG_TARGET_REG_BITS == 32 291 TCG_TYPE_REG = TCG_TYPE_I32, 292 #else 293 TCG_TYPE_REG = TCG_TYPE_I64, 294 #endif 295 296 /* An alias for the size of the native pointer. */ 297 #if UINTPTR_MAX == UINT32_MAX 298 TCG_TYPE_PTR = TCG_TYPE_I32, 299 #else 300 TCG_TYPE_PTR = TCG_TYPE_I64, 301 #endif 302 303 /* An alias for the size of the target "long", aka register. */ 304 #if TARGET_LONG_BITS == 64 305 TCG_TYPE_TL = TCG_TYPE_I64, 306 #else 307 TCG_TYPE_TL = TCG_TYPE_I32, 308 #endif 309 } TCGType; 310 311 /** 312 * tcg_type_size 313 * @t: type 314 * 315 * Return the size of the type in bytes. 316 */ 317 static inline int tcg_type_size(TCGType t) 318 { 319 unsigned i = t; 320 if (i >= TCG_TYPE_V64) { 321 tcg_debug_assert(i < TCG_TYPE_COUNT); 322 i -= TCG_TYPE_V64 - 1; 323 } 324 return 4 << i; 325 } 326 327 /** 328 * get_alignment_bits 329 * @memop: MemOp value 330 * 331 * Extract the alignment size from the memop. 332 */ 333 static inline unsigned get_alignment_bits(MemOp memop) 334 { 335 unsigned a = memop & MO_AMASK; 336 337 if (a == MO_UNALN) { 338 /* No alignment required. */ 339 a = 0; 340 } else if (a == MO_ALIGN) { 341 /* A natural alignment requirement. */ 342 a = memop & MO_SIZE; 343 } else { 344 /* A specific alignment requirement. */ 345 a = a >> MO_ASHIFT; 346 } 347 #if defined(CONFIG_SOFTMMU) 348 /* The requested alignment cannot overlap the TLB flags. */ 349 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 350 #endif 351 return a; 352 } 353 354 typedef tcg_target_ulong TCGArg; 355 356 /* Define type and accessor macros for TCG variables. 357 358 TCG variables are the inputs and outputs of TCG ops, as described 359 in tcg/README. Target CPU front-end code uses these types to deal 360 with TCG variables as it emits TCG code via the tcg_gen_* functions. 361 They come in several flavours: 362 * TCGv_i32 : 32 bit integer type 363 * TCGv_i64 : 64 bit integer type 364 * TCGv_i128 : 128 bit integer type 365 * TCGv_ptr : a host pointer type 366 * TCGv_vec : a host vector type; the exact size is not exposed 367 to the CPU front-end code. 368 * TCGv : an integer type the same size as target_ulong 369 (an alias for either TCGv_i32 or TCGv_i64) 370 The compiler's type checking will complain if you mix them 371 up and pass the wrong sized TCGv to a function. 372 373 Users of tcg_gen_* don't need to know about any of the internal 374 details of these, and should treat them as opaque types. 375 You won't be able to look inside them in a debugger either. 376 377 Internal implementation details follow: 378 379 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 380 This is deliberate, because the values we store in variables of type 381 TCGv_i32 are not really pointers-to-structures. They're just small 382 integers, but keeping them in pointer types like this means that the 383 compiler will complain if you accidentally pass a TCGv_i32 to a 384 function which takes a TCGv_i64, and so on. Only the internals of 385 TCG need to care about the actual contents of the types. */ 386 387 typedef struct TCGv_i32_d *TCGv_i32; 388 typedef struct TCGv_i64_d *TCGv_i64; 389 typedef struct TCGv_i128_d *TCGv_i128; 390 typedef struct TCGv_ptr_d *TCGv_ptr; 391 typedef struct TCGv_vec_d *TCGv_vec; 392 typedef TCGv_ptr TCGv_env; 393 #if TARGET_LONG_BITS == 32 394 #define TCGv TCGv_i32 395 #elif TARGET_LONG_BITS == 64 396 #define TCGv TCGv_i64 397 #else 398 #error Unhandled TARGET_LONG_BITS value 399 #endif 400 401 /* call flags */ 402 /* Helper does not read globals (either directly or through an exception). It 403 implies TCG_CALL_NO_WRITE_GLOBALS. */ 404 #define TCG_CALL_NO_READ_GLOBALS 0x0001 405 /* Helper does not write globals */ 406 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 407 /* Helper can be safely suppressed if the return value is not used. */ 408 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 409 /* Helper is G_NORETURN. */ 410 #define TCG_CALL_NO_RETURN 0x0008 411 /* Helper is part of Plugins. */ 412 #define TCG_CALL_PLUGIN 0x0010 413 414 /* convenience version of most used call flags */ 415 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 416 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 417 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 418 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 419 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 420 421 /* 422 * Flags for the bswap opcodes. 423 * If IZ, the input is zero-extended, otherwise unknown. 424 * If OZ or OS, the output is zero- or sign-extended respectively, 425 * otherwise the high bits are undefined. 426 */ 427 enum { 428 TCG_BSWAP_IZ = 1, 429 TCG_BSWAP_OZ = 2, 430 TCG_BSWAP_OS = 4, 431 }; 432 433 typedef enum TCGTempVal { 434 TEMP_VAL_DEAD, 435 TEMP_VAL_REG, 436 TEMP_VAL_MEM, 437 TEMP_VAL_CONST, 438 } TCGTempVal; 439 440 typedef enum TCGTempKind { 441 /* 442 * Temp is dead at the end of the extended basic block (EBB), 443 * the single-entry multiple-exit region that falls through 444 * conditional branches. 445 */ 446 TEMP_EBB, 447 /* Temp is live across the entire translation block, but dead at end. */ 448 TEMP_TB, 449 /* Temp is live across the entire translation block, and between them. */ 450 TEMP_GLOBAL, 451 /* Temp is in a fixed register. */ 452 TEMP_FIXED, 453 /* Temp is a fixed constant. */ 454 TEMP_CONST, 455 } TCGTempKind; 456 457 typedef struct TCGTemp { 458 TCGReg reg:8; 459 TCGTempVal val_type:8; 460 TCGType base_type:8; 461 TCGType type:8; 462 TCGTempKind kind:3; 463 unsigned int indirect_reg:1; 464 unsigned int indirect_base:1; 465 unsigned int mem_coherent:1; 466 unsigned int mem_allocated:1; 467 unsigned int temp_allocated:1; 468 unsigned int temp_subindex:1; 469 470 int64_t val; 471 struct TCGTemp *mem_base; 472 intptr_t mem_offset; 473 const char *name; 474 475 /* Pass-specific information that can be stored for a temporary. 476 One word worth of integer data, and one pointer to data 477 allocated separately. */ 478 uintptr_t state; 479 void *state_ptr; 480 } TCGTemp; 481 482 typedef struct TCGContext TCGContext; 483 484 typedef struct TCGTempSet { 485 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 486 } TCGTempSet; 487 488 /* 489 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 490 * which leaves a maximum of 28 other slots. Which is enough for 7 491 * 128-bit operands. 492 */ 493 #define DEAD_ARG (1 << 4) 494 #define SYNC_ARG (1 << 0) 495 typedef uint32_t TCGLifeData; 496 497 struct TCGOp { 498 TCGOpcode opc : 8; 499 unsigned nargs : 8; 500 501 /* Parameters for this opcode. See below. */ 502 unsigned param1 : 8; 503 unsigned param2 : 8; 504 505 /* Lifetime data of the operands. */ 506 TCGLifeData life; 507 508 /* Next and previous opcodes. */ 509 QTAILQ_ENTRY(TCGOp) link; 510 511 /* Register preferences for the output(s). */ 512 TCGRegSet output_pref[2]; 513 514 /* Arguments for the opcode. */ 515 TCGArg args[]; 516 }; 517 518 #define TCGOP_CALLI(X) (X)->param1 519 #define TCGOP_CALLO(X) (X)->param2 520 521 #define TCGOP_VECL(X) (X)->param1 522 #define TCGOP_VECE(X) (X)->param2 523 524 /* Make sure operands fit in the bitfields above. */ 525 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 526 527 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 528 { 529 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 530 } 531 532 typedef struct TCGProfile { 533 int64_t cpu_exec_time; 534 int64_t tb_count1; 535 int64_t tb_count; 536 int64_t op_count; /* total insn count */ 537 int op_count_max; /* max insn per TB */ 538 int temp_count_max; 539 int64_t temp_count; 540 int64_t del_op_count; 541 int64_t code_in_len; 542 int64_t code_out_len; 543 int64_t search_out_len; 544 int64_t interm_time; 545 int64_t code_time; 546 int64_t la_time; 547 int64_t opt_time; 548 int64_t restore_count; 549 int64_t restore_time; 550 int64_t table_op_count[NB_OPS]; 551 } TCGProfile; 552 553 struct TCGContext { 554 uint8_t *pool_cur, *pool_end; 555 TCGPool *pool_first, *pool_current, *pool_first_large; 556 int nb_labels; 557 int nb_globals; 558 int nb_temps; 559 int nb_indirects; 560 int nb_ops; 561 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 562 563 #ifdef CONFIG_SOFTMMU 564 int page_mask; 565 uint8_t page_bits; 566 uint8_t tlb_dyn_max_bits; 567 #endif 568 569 TCGRegSet reserved_regs; 570 intptr_t current_frame_offset; 571 intptr_t frame_start; 572 intptr_t frame_end; 573 TCGTemp *frame_temp; 574 575 TranslationBlock *gen_tb; /* tb for which code is being generated */ 576 tcg_insn_unit *code_buf; /* pointer for start of tb */ 577 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 578 579 #ifdef CONFIG_PROFILER 580 TCGProfile prof; 581 #endif 582 583 #ifdef CONFIG_DEBUG_TCG 584 int goto_tb_issue_mask; 585 const TCGOpcode *vecop_list; 586 #endif 587 588 /* Code generation. Note that we specifically do not use tcg_insn_unit 589 here, because there's too much arithmetic throughout that relies 590 on addition and subtraction working on bytes. Rely on the GCC 591 extension that allows arithmetic on void*. */ 592 void *code_gen_buffer; 593 size_t code_gen_buffer_size; 594 void *code_gen_ptr; 595 void *data_gen_ptr; 596 597 /* Threshold to flush the translated code buffer. */ 598 void *code_gen_highwater; 599 600 /* Track which vCPU triggers events */ 601 CPUState *cpu; /* *_trans */ 602 603 /* These structures are private to tcg-target.c.inc. */ 604 #ifdef TCG_TARGET_NEED_LDST_LABELS 605 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 606 #endif 607 #ifdef TCG_TARGET_NEED_POOL_LABELS 608 struct TCGLabelPoolData *pool_labels; 609 #endif 610 611 TCGLabel *exitreq_label; 612 613 #ifdef CONFIG_PLUGIN 614 /* 615 * We keep one plugin_tb struct per TCGContext. Note that on every TB 616 * translation we clear but do not free its contents; this way we 617 * avoid a lot of malloc/free churn, since after a few TB's it's 618 * unlikely that we'll need to allocate either more instructions or more 619 * space for instructions (for variable-instruction-length ISAs). 620 */ 621 struct qemu_plugin_tb *plugin_tb; 622 623 /* descriptor of the instruction being translated */ 624 struct qemu_plugin_insn *plugin_insn; 625 #endif 626 627 GHashTable *const_table[TCG_TYPE_COUNT]; 628 TCGTempSet free_temps[TCG_TYPE_COUNT]; 629 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 630 631 QTAILQ_HEAD(, TCGOp) ops, free_ops; 632 QSIMPLEQ_HEAD(, TCGLabel) labels; 633 634 /* Tells which temporary holds a given register. 635 It does not take into account fixed registers */ 636 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 637 638 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 639 uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 640 641 /* Exit to translator on overflow. */ 642 sigjmp_buf jmp_trans; 643 }; 644 645 static inline bool temp_readonly(TCGTemp *ts) 646 { 647 return ts->kind >= TEMP_FIXED; 648 } 649 650 extern __thread TCGContext *tcg_ctx; 651 extern const void *tcg_code_gen_epilogue; 652 extern uintptr_t tcg_splitwx_diff; 653 extern TCGv_env cpu_env; 654 655 bool in_code_gen_buffer(const void *p); 656 657 #ifdef CONFIG_DEBUG_TCG 658 const void *tcg_splitwx_to_rx(void *rw); 659 void *tcg_splitwx_to_rw(const void *rx); 660 #else 661 static inline const void *tcg_splitwx_to_rx(void *rw) 662 { 663 return rw ? rw + tcg_splitwx_diff : NULL; 664 } 665 666 static inline void *tcg_splitwx_to_rw(const void *rx) 667 { 668 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 669 } 670 #endif 671 672 static inline size_t temp_idx(TCGTemp *ts) 673 { 674 ptrdiff_t n = ts - tcg_ctx->temps; 675 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 676 return n; 677 } 678 679 static inline TCGArg temp_arg(TCGTemp *ts) 680 { 681 return (uintptr_t)ts; 682 } 683 684 static inline TCGTemp *arg_temp(TCGArg a) 685 { 686 return (TCGTemp *)(uintptr_t)a; 687 } 688 689 /* Using the offset of a temporary, relative to TCGContext, rather than 690 its index means that we don't use 0. That leaves offset 0 free for 691 a NULL representation without having to leave index 0 unused. */ 692 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 693 { 694 uintptr_t o = (uintptr_t)v; 695 TCGTemp *t = (void *)tcg_ctx + o; 696 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 697 return t; 698 } 699 700 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 701 { 702 return tcgv_i32_temp((TCGv_i32)v); 703 } 704 705 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 706 { 707 return tcgv_i32_temp((TCGv_i32)v); 708 } 709 710 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 711 { 712 return tcgv_i32_temp((TCGv_i32)v); 713 } 714 715 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 716 { 717 return tcgv_i32_temp((TCGv_i32)v); 718 } 719 720 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 721 { 722 return temp_arg(tcgv_i32_temp(v)); 723 } 724 725 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 726 { 727 return temp_arg(tcgv_i64_temp(v)); 728 } 729 730 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 731 { 732 return temp_arg(tcgv_i128_temp(v)); 733 } 734 735 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 736 { 737 return temp_arg(tcgv_ptr_temp(v)); 738 } 739 740 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 741 { 742 return temp_arg(tcgv_vec_temp(v)); 743 } 744 745 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 746 { 747 (void)temp_idx(t); /* trigger embedded assert */ 748 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 749 } 750 751 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 752 { 753 return (TCGv_i64)temp_tcgv_i32(t); 754 } 755 756 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 757 { 758 return (TCGv_i128)temp_tcgv_i32(t); 759 } 760 761 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 762 { 763 return (TCGv_ptr)temp_tcgv_i32(t); 764 } 765 766 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 767 { 768 return (TCGv_vec)temp_tcgv_i32(t); 769 } 770 771 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 772 { 773 return op->args[arg]; 774 } 775 776 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 777 { 778 op->args[arg] = v; 779 } 780 781 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 782 { 783 if (TCG_TARGET_REG_BITS == 64) { 784 return tcg_get_insn_param(op, arg); 785 } else { 786 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 787 tcg_get_insn_param(op, arg * 2 + 1)); 788 } 789 } 790 791 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 792 { 793 if (TCG_TARGET_REG_BITS == 64) { 794 tcg_set_insn_param(op, arg, v); 795 } else { 796 tcg_set_insn_param(op, arg * 2, v); 797 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 798 } 799 } 800 801 /* The last op that was emitted. */ 802 static inline TCGOp *tcg_last_op(void) 803 { 804 return QTAILQ_LAST(&tcg_ctx->ops); 805 } 806 807 /* Test for whether to terminate the TB for using too many opcodes. */ 808 static inline bool tcg_op_buf_full(void) 809 { 810 /* This is not a hard limit, it merely stops translation when 811 * we have produced "enough" opcodes. We want to limit TB size 812 * such that a RISC host can reasonably use a 16-bit signed 813 * branch within the TB. We also need to be mindful of the 814 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 815 * and TCGContext.gen_insn_end_off[]. 816 */ 817 return tcg_ctx->nb_ops >= 4000; 818 } 819 820 /* pool based memory allocation */ 821 822 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 823 void *tcg_malloc_internal(TCGContext *s, int size); 824 void tcg_pool_reset(TCGContext *s); 825 TranslationBlock *tcg_tb_alloc(TCGContext *s); 826 827 void tcg_region_reset_all(void); 828 829 size_t tcg_code_size(void); 830 size_t tcg_code_capacity(void); 831 832 void tcg_tb_insert(TranslationBlock *tb); 833 void tcg_tb_remove(TranslationBlock *tb); 834 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 835 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 836 size_t tcg_nb_tbs(void); 837 838 /* user-mode: Called with mmap_lock held. */ 839 static inline void *tcg_malloc(int size) 840 { 841 TCGContext *s = tcg_ctx; 842 uint8_t *ptr, *ptr_end; 843 844 /* ??? This is a weak placeholder for minimum malloc alignment. */ 845 size = QEMU_ALIGN_UP(size, 8); 846 847 ptr = s->pool_cur; 848 ptr_end = ptr + size; 849 if (unlikely(ptr_end > s->pool_end)) { 850 return tcg_malloc_internal(tcg_ctx, size); 851 } else { 852 s->pool_cur = ptr_end; 853 return ptr; 854 } 855 } 856 857 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 858 void tcg_register_thread(void); 859 void tcg_prologue_init(TCGContext *s); 860 void tcg_func_start(TCGContext *s); 861 862 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 863 864 void tb_target_set_jmp_target(const TranslationBlock *, int, 865 uintptr_t, uintptr_t); 866 867 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 868 869 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 870 intptr_t, const char *); 871 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 872 TCGv_vec tcg_temp_new_vec(TCGType type); 873 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 874 875 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 876 const char *name) 877 { 878 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 879 return temp_tcgv_i32(t); 880 } 881 882 static inline TCGv_i32 tcg_temp_new_i32(void) 883 { 884 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 885 return temp_tcgv_i32(t); 886 } 887 888 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 889 const char *name) 890 { 891 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 892 return temp_tcgv_i64(t); 893 } 894 895 static inline TCGv_i64 tcg_temp_new_i64(void) 896 { 897 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 898 return temp_tcgv_i64(t); 899 } 900 901 static inline TCGv_i128 tcg_temp_new_i128(void) 902 { 903 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 904 return temp_tcgv_i128(t); 905 } 906 907 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 908 const char *name) 909 { 910 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 911 return temp_tcgv_ptr(t); 912 } 913 914 static inline TCGv_ptr tcg_temp_new_ptr(void) 915 { 916 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 917 return temp_tcgv_ptr(t); 918 } 919 920 int64_t tcg_cpu_exec_time(void); 921 void tcg_dump_info(GString *buf); 922 void tcg_dump_op_count(GString *buf); 923 924 #define TCG_CT_CONST 1 /* any constant of register size */ 925 926 typedef struct TCGArgConstraint { 927 unsigned ct : 16; 928 unsigned alias_index : 4; 929 unsigned sort_index : 4; 930 unsigned pair_index : 4; 931 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 932 bool oalias : 1; 933 bool ialias : 1; 934 bool newreg : 1; 935 TCGRegSet regs; 936 } TCGArgConstraint; 937 938 #define TCG_MAX_OP_ARGS 16 939 940 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 941 enum { 942 /* Instruction exits the translation block. */ 943 TCG_OPF_BB_EXIT = 0x01, 944 /* Instruction defines the end of a basic block. */ 945 TCG_OPF_BB_END = 0x02, 946 /* Instruction clobbers call registers and potentially update globals. */ 947 TCG_OPF_CALL_CLOBBER = 0x04, 948 /* Instruction has side effects: it cannot be removed if its outputs 949 are not used, and might trigger exceptions. */ 950 TCG_OPF_SIDE_EFFECTS = 0x08, 951 /* Instruction operands are 64-bits (otherwise 32-bits). */ 952 TCG_OPF_64BIT = 0x10, 953 /* Instruction is optional and not implemented by the host, or insn 954 is generic and should not be implemened by the host. */ 955 TCG_OPF_NOT_PRESENT = 0x20, 956 /* Instruction operands are vectors. */ 957 TCG_OPF_VECTOR = 0x40, 958 /* Instruction is a conditional branch. */ 959 TCG_OPF_COND_BRANCH = 0x80 960 }; 961 962 typedef struct TCGOpDef { 963 const char *name; 964 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 965 uint8_t flags; 966 TCGArgConstraint *args_ct; 967 } TCGOpDef; 968 969 extern TCGOpDef tcg_op_defs[]; 970 extern const size_t tcg_op_defs_max; 971 972 typedef struct TCGTargetOpDef { 973 TCGOpcode op; 974 const char *args_ct_str[TCG_MAX_OP_ARGS]; 975 } TCGTargetOpDef; 976 977 bool tcg_op_supported(TCGOpcode op); 978 979 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 980 981 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 982 void tcg_op_remove(TCGContext *s, TCGOp *op); 983 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 984 TCGOpcode opc, unsigned nargs); 985 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 986 TCGOpcode opc, unsigned nargs); 987 988 /** 989 * tcg_remove_ops_after: 990 * @op: target operation 991 * 992 * Discard any opcodes emitted since @op. Expected usage is to save 993 * a starting point with tcg_last_op(), speculatively emit opcodes, 994 * then decide whether or not to keep those opcodes after the fact. 995 */ 996 void tcg_remove_ops_after(TCGOp *op); 997 998 void tcg_optimize(TCGContext *s); 999 1000 /* 1001 * Locate or create a read-only temporary that is a constant. 1002 * This kind of temporary need not be freed, but for convenience 1003 * will be silently ignored by tcg_temp_free_*. 1004 */ 1005 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 1006 1007 static inline TCGv_i32 tcg_constant_i32(int32_t val) 1008 { 1009 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 1010 } 1011 1012 static inline TCGv_i64 tcg_constant_i64(int64_t val) 1013 { 1014 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1015 } 1016 1017 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1018 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1019 1020 #if UINTPTR_MAX == UINT32_MAX 1021 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 1022 #else 1023 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1024 #endif 1025 1026 TCGLabel *gen_new_label(void); 1027 1028 /** 1029 * label_arg 1030 * @l: label 1031 * 1032 * Encode a label for storage in the TCG opcode stream. 1033 */ 1034 1035 static inline TCGArg label_arg(TCGLabel *l) 1036 { 1037 return (uintptr_t)l; 1038 } 1039 1040 /** 1041 * arg_label 1042 * @i: value 1043 * 1044 * The opposite of label_arg. Retrieve a label from the 1045 * encoding of the TCG opcode stream. 1046 */ 1047 1048 static inline TCGLabel *arg_label(TCGArg i) 1049 { 1050 return (TCGLabel *)(uintptr_t)i; 1051 } 1052 1053 /** 1054 * tcg_ptr_byte_diff 1055 * @a, @b: addresses to be differenced 1056 * 1057 * There are many places within the TCG backends where we need a byte 1058 * difference between two pointers. While this can be accomplished 1059 * with local casting, it's easy to get wrong -- especially if one is 1060 * concerned with the signedness of the result. 1061 * 1062 * This version relies on GCC's void pointer arithmetic to get the 1063 * correct result. 1064 */ 1065 1066 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1067 { 1068 return a - b; 1069 } 1070 1071 /** 1072 * tcg_pcrel_diff 1073 * @s: the tcg context 1074 * @target: address of the target 1075 * 1076 * Produce a pc-relative difference, from the current code_ptr 1077 * to the destination address. 1078 */ 1079 1080 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1081 { 1082 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1083 } 1084 1085 /** 1086 * tcg_tbrel_diff 1087 * @s: the tcg context 1088 * @target: address of the target 1089 * 1090 * Produce a difference, from the beginning of the current TB code 1091 * to the destination address. 1092 */ 1093 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1094 { 1095 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1096 } 1097 1098 /** 1099 * tcg_current_code_size 1100 * @s: the tcg context 1101 * 1102 * Compute the current code size within the translation block. 1103 * This is used to fill in qemu's data structures for goto_tb. 1104 */ 1105 1106 static inline size_t tcg_current_code_size(TCGContext *s) 1107 { 1108 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1109 } 1110 1111 /** 1112 * tcg_qemu_tb_exec: 1113 * @env: pointer to CPUArchState for the CPU 1114 * @tb_ptr: address of generated code for the TB to execute 1115 * 1116 * Start executing code from a given translation block. 1117 * Where translation blocks have been linked, execution 1118 * may proceed from the given TB into successive ones. 1119 * Control eventually returns only when some action is needed 1120 * from the top-level loop: either control must pass to a TB 1121 * which has not yet been directly linked, or an asynchronous 1122 * event such as an interrupt needs handling. 1123 * 1124 * Return: The return value is the value passed to the corresponding 1125 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1126 * The value is either zero or a 4-byte aligned pointer to that TB combined 1127 * with additional information in its two least significant bits. The 1128 * additional information is encoded as follows: 1129 * 0, 1: the link between this TB and the next is via the specified 1130 * TB index (0 or 1). That is, we left the TB via (the equivalent 1131 * of) "goto_tb <index>". The main loop uses this to determine 1132 * how to link the TB just executed to the next. 1133 * 2: we are using instruction counting code generation, and we 1134 * did not start executing this TB because the instruction counter 1135 * would hit zero midway through it. In this case the pointer 1136 * returned is the TB we were about to execute, and the caller must 1137 * arrange to execute the remaining count of instructions. 1138 * 3: we stopped because the CPU's exit_request flag was set 1139 * (usually meaning that there is an interrupt that needs to be 1140 * handled). The pointer returned is the TB we were about to execute 1141 * when we noticed the pending exit request. 1142 * 1143 * If the bottom two bits indicate an exit-via-index then the CPU 1144 * state is correctly synchronised and ready for execution of the next 1145 * TB (and in particular the guest PC is the address to execute next). 1146 * Otherwise, we gave up on execution of this TB before it started, and 1147 * the caller must fix up the CPU state by calling the CPU's 1148 * synchronize_from_tb() method with the TB pointer we return (falling 1149 * back to calling the CPU's set_pc method with tb->pb if no 1150 * synchronize_from_tb() method exists). 1151 * 1152 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1153 * to this default (which just calls the prologue.code emitted by 1154 * tcg_target_qemu_prologue()). 1155 */ 1156 #define TB_EXIT_MASK 3 1157 #define TB_EXIT_IDX0 0 1158 #define TB_EXIT_IDX1 1 1159 #define TB_EXIT_IDXMAX 1 1160 #define TB_EXIT_REQUESTED 3 1161 1162 #ifdef CONFIG_TCG_INTERPRETER 1163 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1164 #else 1165 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1166 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1167 #endif 1168 1169 void tcg_register_jit(const void *buf, size_t buf_size); 1170 1171 #if TCG_TARGET_MAYBE_vec 1172 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1173 return > 0 if it is directly supportable; 1174 return < 0 if we must call tcg_expand_vec_op. */ 1175 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1176 #else 1177 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1178 { 1179 return 0; 1180 } 1181 #endif 1182 1183 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1184 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1185 1186 /* Replicate a constant C accoring to the log2 of the element size. */ 1187 uint64_t dup_const(unsigned vece, uint64_t c); 1188 1189 #define dup_const(VECE, C) \ 1190 (__builtin_constant_p(VECE) \ 1191 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1192 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1193 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1194 : (VECE) == MO_64 ? (uint64_t)(C) \ 1195 : (qemu_build_not_reached_always(), 0)) \ 1196 : dup_const(VECE, C)) 1197 1198 #if TARGET_LONG_BITS == 64 1199 # define dup_const_tl dup_const 1200 #else 1201 # define dup_const_tl(VECE, C) \ 1202 (__builtin_constant_p(VECE) \ 1203 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1204 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1205 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1206 : (qemu_build_not_reached_always(), 0)) \ 1207 : (target_long)dup_const(VECE, C)) 1208 #endif 1209 1210 #ifdef CONFIG_DEBUG_TCG 1211 void tcg_assert_listed_vecop(TCGOpcode); 1212 #else 1213 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1214 #endif 1215 1216 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1217 { 1218 #ifdef CONFIG_DEBUG_TCG 1219 const TCGOpcode *o = tcg_ctx->vecop_list; 1220 tcg_ctx->vecop_list = n; 1221 return o; 1222 #else 1223 return NULL; 1224 #endif 1225 } 1226 1227 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1228 1229 #endif /* TCG_H */ 1230