1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "exec/memop.h" 29 #include "exec/memopidx.h" 30 #include "qemu/bitops.h" 31 #include "qemu/plugin.h" 32 #include "qemu/queue.h" 33 #include "tcg/tcg-mo.h" 34 #include "tcg-target-reg-bits.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 #include "tcg/debug-assert.h" 38 39 /* XXX: make safe guess about sizes */ 40 #define MAX_OP_PER_INSTR 266 41 42 #define MAX_CALL_IARGS 7 43 44 #define CPU_TEMP_BUF_NLONGS 128 45 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 46 47 #if TCG_TARGET_REG_BITS == 32 48 typedef int32_t tcg_target_long; 49 typedef uint32_t tcg_target_ulong; 50 #define TCG_PRIlx PRIx32 51 #define TCG_PRIld PRId32 52 #elif TCG_TARGET_REG_BITS == 64 53 typedef int64_t tcg_target_long; 54 typedef uint64_t tcg_target_ulong; 55 #define TCG_PRIlx PRIx64 56 #define TCG_PRIld PRId64 57 #else 58 #error unsupported 59 #endif 60 61 #if TCG_TARGET_NB_REGS <= 32 62 typedef uint32_t TCGRegSet; 63 #elif TCG_TARGET_NB_REGS <= 64 64 typedef uint64_t TCGRegSet; 65 #else 66 #error unsupported 67 #endif 68 69 #if TCG_TARGET_REG_BITS == 32 70 /* Turn some undef macros into false macros. */ 71 #define TCG_TARGET_HAS_extr_i64_i32 0 72 #define TCG_TARGET_HAS_div_i64 0 73 #define TCG_TARGET_HAS_rem_i64 0 74 #define TCG_TARGET_HAS_div2_i64 0 75 #define TCG_TARGET_HAS_rot_i64 0 76 #define TCG_TARGET_HAS_ext8s_i64 0 77 #define TCG_TARGET_HAS_ext16s_i64 0 78 #define TCG_TARGET_HAS_ext32s_i64 0 79 #define TCG_TARGET_HAS_ext8u_i64 0 80 #define TCG_TARGET_HAS_ext16u_i64 0 81 #define TCG_TARGET_HAS_ext32u_i64 0 82 #define TCG_TARGET_HAS_bswap16_i64 0 83 #define TCG_TARGET_HAS_bswap32_i64 0 84 #define TCG_TARGET_HAS_bswap64_i64 0 85 #define TCG_TARGET_HAS_neg_i64 0 86 #define TCG_TARGET_HAS_not_i64 0 87 #define TCG_TARGET_HAS_andc_i64 0 88 #define TCG_TARGET_HAS_orc_i64 0 89 #define TCG_TARGET_HAS_eqv_i64 0 90 #define TCG_TARGET_HAS_nand_i64 0 91 #define TCG_TARGET_HAS_nor_i64 0 92 #define TCG_TARGET_HAS_clz_i64 0 93 #define TCG_TARGET_HAS_ctz_i64 0 94 #define TCG_TARGET_HAS_ctpop_i64 0 95 #define TCG_TARGET_HAS_deposit_i64 0 96 #define TCG_TARGET_HAS_extract_i64 0 97 #define TCG_TARGET_HAS_sextract_i64 0 98 #define TCG_TARGET_HAS_extract2_i64 0 99 #define TCG_TARGET_HAS_movcond_i64 0 100 #define TCG_TARGET_HAS_negsetcond_i64 0 101 #define TCG_TARGET_HAS_add2_i64 0 102 #define TCG_TARGET_HAS_sub2_i64 0 103 #define TCG_TARGET_HAS_mulu2_i64 0 104 #define TCG_TARGET_HAS_muls2_i64 0 105 #define TCG_TARGET_HAS_muluh_i64 0 106 #define TCG_TARGET_HAS_mulsh_i64 0 107 /* Turn some undef macros into true macros. */ 108 #define TCG_TARGET_HAS_add2_i32 1 109 #define TCG_TARGET_HAS_sub2_i32 1 110 #endif 111 112 #ifndef TCG_TARGET_deposit_i32_valid 113 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 114 #endif 115 #ifndef TCG_TARGET_deposit_i64_valid 116 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 117 #endif 118 #ifndef TCG_TARGET_extract_i32_valid 119 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 120 #endif 121 #ifndef TCG_TARGET_extract_i64_valid 122 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 123 #endif 124 125 /* Only one of DIV or DIV2 should be defined. */ 126 #if defined(TCG_TARGET_HAS_div_i32) 127 #define TCG_TARGET_HAS_div2_i32 0 128 #elif defined(TCG_TARGET_HAS_div2_i32) 129 #define TCG_TARGET_HAS_div_i32 0 130 #define TCG_TARGET_HAS_rem_i32 0 131 #endif 132 #if defined(TCG_TARGET_HAS_div_i64) 133 #define TCG_TARGET_HAS_div2_i64 0 134 #elif defined(TCG_TARGET_HAS_div2_i64) 135 #define TCG_TARGET_HAS_div_i64 0 136 #define TCG_TARGET_HAS_rem_i64 0 137 #endif 138 139 #if !defined(TCG_TARGET_HAS_v64) \ 140 && !defined(TCG_TARGET_HAS_v128) \ 141 && !defined(TCG_TARGET_HAS_v256) 142 #define TCG_TARGET_MAYBE_vec 0 143 #define TCG_TARGET_HAS_abs_vec 0 144 #define TCG_TARGET_HAS_neg_vec 0 145 #define TCG_TARGET_HAS_not_vec 0 146 #define TCG_TARGET_HAS_andc_vec 0 147 #define TCG_TARGET_HAS_orc_vec 0 148 #define TCG_TARGET_HAS_nand_vec 0 149 #define TCG_TARGET_HAS_nor_vec 0 150 #define TCG_TARGET_HAS_eqv_vec 0 151 #define TCG_TARGET_HAS_roti_vec 0 152 #define TCG_TARGET_HAS_rots_vec 0 153 #define TCG_TARGET_HAS_rotv_vec 0 154 #define TCG_TARGET_HAS_shi_vec 0 155 #define TCG_TARGET_HAS_shs_vec 0 156 #define TCG_TARGET_HAS_shv_vec 0 157 #define TCG_TARGET_HAS_mul_vec 0 158 #define TCG_TARGET_HAS_sat_vec 0 159 #define TCG_TARGET_HAS_minmax_vec 0 160 #define TCG_TARGET_HAS_bitsel_vec 0 161 #define TCG_TARGET_HAS_cmpsel_vec 0 162 #else 163 #define TCG_TARGET_MAYBE_vec 1 164 #endif 165 #ifndef TCG_TARGET_HAS_v64 166 #define TCG_TARGET_HAS_v64 0 167 #endif 168 #ifndef TCG_TARGET_HAS_v128 169 #define TCG_TARGET_HAS_v128 0 170 #endif 171 #ifndef TCG_TARGET_HAS_v256 172 #define TCG_TARGET_HAS_v256 0 173 #endif 174 175 typedef enum TCGOpcode { 176 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 177 #include "tcg/tcg-opc.h" 178 #undef DEF 179 NB_OPS, 180 } TCGOpcode; 181 182 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 183 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 184 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 185 186 #ifndef TCG_TARGET_INSN_UNIT_SIZE 187 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 188 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 189 typedef uint8_t tcg_insn_unit; 190 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 191 typedef uint16_t tcg_insn_unit; 192 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 193 typedef uint32_t tcg_insn_unit; 194 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 195 typedef uint64_t tcg_insn_unit; 196 #else 197 /* The port better have done this. */ 198 #endif 199 200 typedef struct TCGRelocation TCGRelocation; 201 struct TCGRelocation { 202 QSIMPLEQ_ENTRY(TCGRelocation) next; 203 tcg_insn_unit *ptr; 204 intptr_t addend; 205 int type; 206 }; 207 208 typedef struct TCGOp TCGOp; 209 typedef struct TCGLabelUse TCGLabelUse; 210 struct TCGLabelUse { 211 QSIMPLEQ_ENTRY(TCGLabelUse) next; 212 TCGOp *op; 213 }; 214 215 typedef struct TCGLabel TCGLabel; 216 struct TCGLabel { 217 bool present; 218 bool has_value; 219 uint16_t id; 220 union { 221 uintptr_t value; 222 const tcg_insn_unit *value_ptr; 223 } u; 224 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 225 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 226 QSIMPLEQ_ENTRY(TCGLabel) next; 227 }; 228 229 typedef struct TCGPool { 230 struct TCGPool *next; 231 int size; 232 uint8_t data[] __attribute__ ((aligned)); 233 } TCGPool; 234 235 #define TCG_POOL_CHUNK_SIZE 32768 236 237 #define TCG_MAX_TEMPS 512 238 #define TCG_MAX_INSNS 512 239 240 /* when the size of the arguments of a called function is smaller than 241 this value, they are statically allocated in the TB stack frame */ 242 #define TCG_STATIC_CALL_ARGS_SIZE 128 243 244 typedef enum TCGType { 245 TCG_TYPE_I32, 246 TCG_TYPE_I64, 247 TCG_TYPE_I128, 248 249 TCG_TYPE_V64, 250 TCG_TYPE_V128, 251 TCG_TYPE_V256, 252 253 /* Number of different types (integer not enum) */ 254 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 255 256 /* An alias for the size of the host register. */ 257 #if TCG_TARGET_REG_BITS == 32 258 TCG_TYPE_REG = TCG_TYPE_I32, 259 #else 260 TCG_TYPE_REG = TCG_TYPE_I64, 261 #endif 262 263 /* An alias for the size of the native pointer. */ 264 #if UINTPTR_MAX == UINT32_MAX 265 TCG_TYPE_PTR = TCG_TYPE_I32, 266 #else 267 TCG_TYPE_PTR = TCG_TYPE_I64, 268 #endif 269 } TCGType; 270 271 /** 272 * tcg_type_size 273 * @t: type 274 * 275 * Return the size of the type in bytes. 276 */ 277 static inline int tcg_type_size(TCGType t) 278 { 279 unsigned i = t; 280 if (i >= TCG_TYPE_V64) { 281 tcg_debug_assert(i < TCG_TYPE_COUNT); 282 i -= TCG_TYPE_V64 - 1; 283 } 284 return 4 << i; 285 } 286 287 /** 288 * get_alignment_bits 289 * @memop: MemOp value 290 * 291 * Extract the alignment size from the memop. 292 */ 293 static inline unsigned get_alignment_bits(MemOp memop) 294 { 295 unsigned a = memop & MO_AMASK; 296 297 if (a == MO_UNALN) { 298 /* No alignment required. */ 299 a = 0; 300 } else if (a == MO_ALIGN) { 301 /* A natural alignment requirement. */ 302 a = memop & MO_SIZE; 303 } else { 304 /* A specific alignment requirement. */ 305 a = a >> MO_ASHIFT; 306 } 307 return a; 308 } 309 310 typedef tcg_target_ulong TCGArg; 311 312 /* Define type and accessor macros for TCG variables. 313 314 TCG variables are the inputs and outputs of TCG ops, as described 315 in tcg/README. Target CPU front-end code uses these types to deal 316 with TCG variables as it emits TCG code via the tcg_gen_* functions. 317 They come in several flavours: 318 * TCGv_i32 : 32 bit integer type 319 * TCGv_i64 : 64 bit integer type 320 * TCGv_i128 : 128 bit integer type 321 * TCGv_ptr : a host pointer type 322 * TCGv_vec : a host vector type; the exact size is not exposed 323 to the CPU front-end code. 324 * TCGv : an integer type the same size as target_ulong 325 (an alias for either TCGv_i32 or TCGv_i64) 326 The compiler's type checking will complain if you mix them 327 up and pass the wrong sized TCGv to a function. 328 329 Users of tcg_gen_* don't need to know about any of the internal 330 details of these, and should treat them as opaque types. 331 You won't be able to look inside them in a debugger either. 332 333 Internal implementation details follow: 334 335 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 336 This is deliberate, because the values we store in variables of type 337 TCGv_i32 are not really pointers-to-structures. They're just small 338 integers, but keeping them in pointer types like this means that the 339 compiler will complain if you accidentally pass a TCGv_i32 to a 340 function which takes a TCGv_i64, and so on. Only the internals of 341 TCG need to care about the actual contents of the types. */ 342 343 typedef struct TCGv_i32_d *TCGv_i32; 344 typedef struct TCGv_i64_d *TCGv_i64; 345 typedef struct TCGv_i128_d *TCGv_i128; 346 typedef struct TCGv_ptr_d *TCGv_ptr; 347 typedef struct TCGv_vec_d *TCGv_vec; 348 typedef TCGv_ptr TCGv_env; 349 350 /* call flags */ 351 /* Helper does not read globals (either directly or through an exception). It 352 implies TCG_CALL_NO_WRITE_GLOBALS. */ 353 #define TCG_CALL_NO_READ_GLOBALS 0x0001 354 /* Helper does not write globals */ 355 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 356 /* Helper can be safely suppressed if the return value is not used. */ 357 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 358 /* Helper is G_NORETURN. */ 359 #define TCG_CALL_NO_RETURN 0x0008 360 /* Helper is part of Plugins. */ 361 #define TCG_CALL_PLUGIN 0x0010 362 363 /* convenience version of most used call flags */ 364 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 365 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 366 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 367 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 368 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 369 370 /* 371 * Flags for the bswap opcodes. 372 * If IZ, the input is zero-extended, otherwise unknown. 373 * If OZ or OS, the output is zero- or sign-extended respectively, 374 * otherwise the high bits are undefined. 375 */ 376 enum { 377 TCG_BSWAP_IZ = 1, 378 TCG_BSWAP_OZ = 2, 379 TCG_BSWAP_OS = 4, 380 }; 381 382 typedef enum TCGTempVal { 383 TEMP_VAL_DEAD, 384 TEMP_VAL_REG, 385 TEMP_VAL_MEM, 386 TEMP_VAL_CONST, 387 } TCGTempVal; 388 389 typedef enum TCGTempKind { 390 /* 391 * Temp is dead at the end of the extended basic block (EBB), 392 * the single-entry multiple-exit region that falls through 393 * conditional branches. 394 */ 395 TEMP_EBB, 396 /* Temp is live across the entire translation block, but dead at end. */ 397 TEMP_TB, 398 /* Temp is live across the entire translation block, and between them. */ 399 TEMP_GLOBAL, 400 /* Temp is in a fixed register. */ 401 TEMP_FIXED, 402 /* Temp is a fixed constant. */ 403 TEMP_CONST, 404 } TCGTempKind; 405 406 typedef struct TCGTemp { 407 TCGReg reg:8; 408 TCGTempVal val_type:8; 409 TCGType base_type:8; 410 TCGType type:8; 411 TCGTempKind kind:3; 412 unsigned int indirect_reg:1; 413 unsigned int indirect_base:1; 414 unsigned int mem_coherent:1; 415 unsigned int mem_allocated:1; 416 unsigned int temp_allocated:1; 417 unsigned int temp_subindex:1; 418 419 int64_t val; 420 struct TCGTemp *mem_base; 421 intptr_t mem_offset; 422 const char *name; 423 424 /* Pass-specific information that can be stored for a temporary. 425 One word worth of integer data, and one pointer to data 426 allocated separately. */ 427 uintptr_t state; 428 void *state_ptr; 429 } TCGTemp; 430 431 typedef struct TCGContext TCGContext; 432 433 typedef struct TCGTempSet { 434 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 435 } TCGTempSet; 436 437 /* 438 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 439 * which leaves a maximum of 28 other slots. Which is enough for 7 440 * 128-bit operands. 441 */ 442 #define DEAD_ARG (1 << 4) 443 #define SYNC_ARG (1 << 0) 444 typedef uint32_t TCGLifeData; 445 446 struct TCGOp { 447 TCGOpcode opc : 8; 448 unsigned nargs : 8; 449 450 /* Parameters for this opcode. See below. */ 451 unsigned param1 : 8; 452 unsigned param2 : 8; 453 454 /* Lifetime data of the operands. */ 455 TCGLifeData life; 456 457 /* Next and previous opcodes. */ 458 QTAILQ_ENTRY(TCGOp) link; 459 460 /* Register preferences for the output(s). */ 461 TCGRegSet output_pref[2]; 462 463 /* Arguments for the opcode. */ 464 TCGArg args[]; 465 }; 466 467 #define TCGOP_CALLI(X) (X)->param1 468 #define TCGOP_CALLO(X) (X)->param2 469 470 #define TCGOP_VECL(X) (X)->param1 471 #define TCGOP_VECE(X) (X)->param2 472 473 /* Make sure operands fit in the bitfields above. */ 474 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 475 476 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 477 { 478 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 479 } 480 481 struct TCGContext { 482 uint8_t *pool_cur, *pool_end; 483 TCGPool *pool_first, *pool_current, *pool_first_large; 484 int nb_labels; 485 int nb_globals; 486 int nb_temps; 487 int nb_indirects; 488 int nb_ops; 489 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 490 491 #ifdef CONFIG_SOFTMMU 492 int tlb_fast_offset; 493 int page_mask; 494 uint8_t page_bits; 495 uint8_t tlb_dyn_max_bits; 496 #endif 497 uint8_t insn_start_words; 498 TCGBar guest_mo; 499 500 TCGRegSet reserved_regs; 501 intptr_t current_frame_offset; 502 intptr_t frame_start; 503 intptr_t frame_end; 504 TCGTemp *frame_temp; 505 506 TranslationBlock *gen_tb; /* tb for which code is being generated */ 507 tcg_insn_unit *code_buf; /* pointer for start of tb */ 508 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 509 510 #ifdef CONFIG_DEBUG_TCG 511 int goto_tb_issue_mask; 512 const TCGOpcode *vecop_list; 513 #endif 514 515 /* Code generation. Note that we specifically do not use tcg_insn_unit 516 here, because there's too much arithmetic throughout that relies 517 on addition and subtraction working on bytes. Rely on the GCC 518 extension that allows arithmetic on void*. */ 519 void *code_gen_buffer; 520 size_t code_gen_buffer_size; 521 void *code_gen_ptr; 522 void *data_gen_ptr; 523 524 /* Threshold to flush the translated code buffer. */ 525 void *code_gen_highwater; 526 527 /* Track which vCPU triggers events */ 528 CPUState *cpu; /* *_trans */ 529 530 /* These structures are private to tcg-target.c.inc. */ 531 #ifdef TCG_TARGET_NEED_LDST_LABELS 532 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 533 #endif 534 #ifdef TCG_TARGET_NEED_POOL_LABELS 535 struct TCGLabelPoolData *pool_labels; 536 #endif 537 538 TCGLabel *exitreq_label; 539 540 #ifdef CONFIG_PLUGIN 541 /* 542 * We keep one plugin_tb struct per TCGContext. Note that on every TB 543 * translation we clear but do not free its contents; this way we 544 * avoid a lot of malloc/free churn, since after a few TB's it's 545 * unlikely that we'll need to allocate either more instructions or more 546 * space for instructions (for variable-instruction-length ISAs). 547 */ 548 struct qemu_plugin_tb *plugin_tb; 549 550 /* descriptor of the instruction being translated */ 551 struct qemu_plugin_insn *plugin_insn; 552 #endif 553 554 GHashTable *const_table[TCG_TYPE_COUNT]; 555 TCGTempSet free_temps[TCG_TYPE_COUNT]; 556 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 557 558 QTAILQ_HEAD(, TCGOp) ops, free_ops; 559 QSIMPLEQ_HEAD(, TCGLabel) labels; 560 561 /* Tells which temporary holds a given register. 562 It does not take into account fixed registers */ 563 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 564 565 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 566 uint64_t *gen_insn_data; 567 568 /* Exit to translator on overflow. */ 569 sigjmp_buf jmp_trans; 570 }; 571 572 static inline bool temp_readonly(TCGTemp *ts) 573 { 574 return ts->kind >= TEMP_FIXED; 575 } 576 577 extern __thread TCGContext *tcg_ctx; 578 extern const void *tcg_code_gen_epilogue; 579 extern uintptr_t tcg_splitwx_diff; 580 extern TCGv_env cpu_env; 581 582 bool in_code_gen_buffer(const void *p); 583 584 #ifdef CONFIG_DEBUG_TCG 585 const void *tcg_splitwx_to_rx(void *rw); 586 void *tcg_splitwx_to_rw(const void *rx); 587 #else 588 static inline const void *tcg_splitwx_to_rx(void *rw) 589 { 590 return rw ? rw + tcg_splitwx_diff : NULL; 591 } 592 593 static inline void *tcg_splitwx_to_rw(const void *rx) 594 { 595 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 596 } 597 #endif 598 599 static inline TCGArg temp_arg(TCGTemp *ts) 600 { 601 return (uintptr_t)ts; 602 } 603 604 static inline TCGTemp *arg_temp(TCGArg a) 605 { 606 return (TCGTemp *)(uintptr_t)a; 607 } 608 609 #ifdef CONFIG_DEBUG_TCG 610 size_t temp_idx(TCGTemp *ts); 611 TCGTemp *tcgv_i32_temp(TCGv_i32 v); 612 #else 613 static inline size_t temp_idx(TCGTemp *ts) 614 { 615 return ts - tcg_ctx->temps; 616 } 617 618 /* 619 * Using the offset of a temporary, relative to TCGContext, rather than 620 * its index means that we don't use 0. That leaves offset 0 free for 621 * a NULL representation without having to leave index 0 unused. 622 */ 623 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 624 { 625 return (void *)tcg_ctx + (uintptr_t)v; 626 } 627 #endif 628 629 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 630 { 631 return tcgv_i32_temp((TCGv_i32)v); 632 } 633 634 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 635 { 636 return tcgv_i32_temp((TCGv_i32)v); 637 } 638 639 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 640 { 641 return tcgv_i32_temp((TCGv_i32)v); 642 } 643 644 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 645 { 646 return tcgv_i32_temp((TCGv_i32)v); 647 } 648 649 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 650 { 651 return temp_arg(tcgv_i32_temp(v)); 652 } 653 654 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 655 { 656 return temp_arg(tcgv_i64_temp(v)); 657 } 658 659 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 660 { 661 return temp_arg(tcgv_i128_temp(v)); 662 } 663 664 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 665 { 666 return temp_arg(tcgv_ptr_temp(v)); 667 } 668 669 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 670 { 671 return temp_arg(tcgv_vec_temp(v)); 672 } 673 674 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 675 { 676 (void)temp_idx(t); /* trigger embedded assert */ 677 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 678 } 679 680 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 681 { 682 return (TCGv_i64)temp_tcgv_i32(t); 683 } 684 685 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 686 { 687 return (TCGv_i128)temp_tcgv_i32(t); 688 } 689 690 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 691 { 692 return (TCGv_ptr)temp_tcgv_i32(t); 693 } 694 695 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 696 { 697 return (TCGv_vec)temp_tcgv_i32(t); 698 } 699 700 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 701 { 702 return op->args[arg]; 703 } 704 705 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 706 { 707 op->args[arg] = v; 708 } 709 710 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 711 { 712 if (TCG_TARGET_REG_BITS == 64) { 713 return tcg_get_insn_param(op, arg); 714 } else { 715 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 716 tcg_get_insn_param(op, arg * 2 + 1)); 717 } 718 } 719 720 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 721 { 722 if (TCG_TARGET_REG_BITS == 64) { 723 tcg_set_insn_param(op, arg, v); 724 } else { 725 tcg_set_insn_param(op, arg * 2, v); 726 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 727 } 728 } 729 730 /* The last op that was emitted. */ 731 static inline TCGOp *tcg_last_op(void) 732 { 733 return QTAILQ_LAST(&tcg_ctx->ops); 734 } 735 736 /* Test for whether to terminate the TB for using too many opcodes. */ 737 static inline bool tcg_op_buf_full(void) 738 { 739 /* This is not a hard limit, it merely stops translation when 740 * we have produced "enough" opcodes. We want to limit TB size 741 * such that a RISC host can reasonably use a 16-bit signed 742 * branch within the TB. We also need to be mindful of the 743 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 744 * and TCGContext.gen_insn_end_off[]. 745 */ 746 return tcg_ctx->nb_ops >= 4000; 747 } 748 749 /* pool based memory allocation */ 750 751 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 752 void *tcg_malloc_internal(TCGContext *s, int size); 753 void tcg_pool_reset(TCGContext *s); 754 TranslationBlock *tcg_tb_alloc(TCGContext *s); 755 756 void tcg_region_reset_all(void); 757 758 size_t tcg_code_size(void); 759 size_t tcg_code_capacity(void); 760 761 void tcg_tb_insert(TranslationBlock *tb); 762 void tcg_tb_remove(TranslationBlock *tb); 763 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 764 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 765 size_t tcg_nb_tbs(void); 766 767 /* user-mode: Called with mmap_lock held. */ 768 static inline void *tcg_malloc(int size) 769 { 770 TCGContext *s = tcg_ctx; 771 uint8_t *ptr, *ptr_end; 772 773 /* ??? This is a weak placeholder for minimum malloc alignment. */ 774 size = QEMU_ALIGN_UP(size, 8); 775 776 ptr = s->pool_cur; 777 ptr_end = ptr + size; 778 if (unlikely(ptr_end > s->pool_end)) { 779 return tcg_malloc_internal(tcg_ctx, size); 780 } else { 781 s->pool_cur = ptr_end; 782 return ptr; 783 } 784 } 785 786 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 787 void tcg_register_thread(void); 788 void tcg_prologue_init(TCGContext *s); 789 void tcg_func_start(TCGContext *s); 790 791 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 792 793 void tb_target_set_jmp_target(const TranslationBlock *, int, 794 uintptr_t, uintptr_t); 795 796 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 797 798 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 799 intptr_t, const char *); 800 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 801 TCGv_vec tcg_temp_new_vec(TCGType type); 802 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 803 804 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 805 const char *name) 806 { 807 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 808 return temp_tcgv_i32(t); 809 } 810 811 static inline TCGv_i32 tcg_temp_new_i32(void) 812 { 813 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 814 return temp_tcgv_i32(t); 815 } 816 817 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 818 const char *name) 819 { 820 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 821 return temp_tcgv_i64(t); 822 } 823 824 static inline TCGv_i64 tcg_temp_new_i64(void) 825 { 826 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 827 return temp_tcgv_i64(t); 828 } 829 830 static inline TCGv_i128 tcg_temp_new_i128(void) 831 { 832 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 833 return temp_tcgv_i128(t); 834 } 835 836 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 837 const char *name) 838 { 839 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 840 return temp_tcgv_ptr(t); 841 } 842 843 static inline TCGv_ptr tcg_temp_new_ptr(void) 844 { 845 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 846 return temp_tcgv_ptr(t); 847 } 848 849 void tcg_dump_info(GString *buf); 850 void tcg_dump_op_count(GString *buf); 851 852 #define TCG_CT_CONST 1 /* any constant of register size */ 853 854 typedef struct TCGArgConstraint { 855 unsigned ct : 16; 856 unsigned alias_index : 4; 857 unsigned sort_index : 4; 858 unsigned pair_index : 4; 859 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 860 bool oalias : 1; 861 bool ialias : 1; 862 bool newreg : 1; 863 TCGRegSet regs; 864 } TCGArgConstraint; 865 866 #define TCG_MAX_OP_ARGS 16 867 868 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 869 enum { 870 /* Instruction exits the translation block. */ 871 TCG_OPF_BB_EXIT = 0x01, 872 /* Instruction defines the end of a basic block. */ 873 TCG_OPF_BB_END = 0x02, 874 /* Instruction clobbers call registers and potentially update globals. */ 875 TCG_OPF_CALL_CLOBBER = 0x04, 876 /* Instruction has side effects: it cannot be removed if its outputs 877 are not used, and might trigger exceptions. */ 878 TCG_OPF_SIDE_EFFECTS = 0x08, 879 /* Instruction operands are 64-bits (otherwise 32-bits). */ 880 TCG_OPF_64BIT = 0x10, 881 /* Instruction is optional and not implemented by the host, or insn 882 is generic and should not be implemened by the host. */ 883 TCG_OPF_NOT_PRESENT = 0x20, 884 /* Instruction operands are vectors. */ 885 TCG_OPF_VECTOR = 0x40, 886 /* Instruction is a conditional branch. */ 887 TCG_OPF_COND_BRANCH = 0x80 888 }; 889 890 typedef struct TCGOpDef { 891 const char *name; 892 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 893 uint8_t flags; 894 TCGArgConstraint *args_ct; 895 } TCGOpDef; 896 897 extern TCGOpDef tcg_op_defs[]; 898 extern const size_t tcg_op_defs_max; 899 900 typedef struct TCGTargetOpDef { 901 TCGOpcode op; 902 const char *args_ct_str[TCG_MAX_OP_ARGS]; 903 } TCGTargetOpDef; 904 905 bool tcg_op_supported(TCGOpcode op); 906 907 void tcg_gen_call0(TCGHelperInfo *, TCGTemp *ret); 908 void tcg_gen_call1(TCGHelperInfo *, TCGTemp *ret, TCGTemp *); 909 void tcg_gen_call2(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *); 910 void tcg_gen_call3(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, 911 TCGTemp *, TCGTemp *); 912 void tcg_gen_call4(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 913 TCGTemp *, TCGTemp *); 914 void tcg_gen_call5(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 915 TCGTemp *, TCGTemp *, TCGTemp *); 916 void tcg_gen_call6(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 917 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); 918 void tcg_gen_call7(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, 919 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); 920 921 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 922 void tcg_op_remove(TCGContext *s, TCGOp *op); 923 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 924 TCGOpcode opc, unsigned nargs); 925 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 926 TCGOpcode opc, unsigned nargs); 927 928 /** 929 * tcg_remove_ops_after: 930 * @op: target operation 931 * 932 * Discard any opcodes emitted since @op. Expected usage is to save 933 * a starting point with tcg_last_op(), speculatively emit opcodes, 934 * then decide whether or not to keep those opcodes after the fact. 935 */ 936 void tcg_remove_ops_after(TCGOp *op); 937 938 void tcg_optimize(TCGContext *s); 939 940 /* 941 * Locate or create a read-only temporary that is a constant. 942 * This kind of temporary need not be freed, but for convenience 943 * will be silently ignored by tcg_temp_free_*. 944 */ 945 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 946 947 static inline TCGv_i32 tcg_constant_i32(int32_t val) 948 { 949 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 950 } 951 952 static inline TCGv_i64 tcg_constant_i64(int64_t val) 953 { 954 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 955 } 956 957 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 958 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 959 960 #if UINTPTR_MAX == UINT32_MAX 961 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 962 #else 963 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 964 #endif 965 966 TCGLabel *gen_new_label(void); 967 968 /** 969 * label_arg 970 * @l: label 971 * 972 * Encode a label for storage in the TCG opcode stream. 973 */ 974 975 static inline TCGArg label_arg(TCGLabel *l) 976 { 977 return (uintptr_t)l; 978 } 979 980 /** 981 * arg_label 982 * @i: value 983 * 984 * The opposite of label_arg. Retrieve a label from the 985 * encoding of the TCG opcode stream. 986 */ 987 988 static inline TCGLabel *arg_label(TCGArg i) 989 { 990 return (TCGLabel *)(uintptr_t)i; 991 } 992 993 /** 994 * tcg_ptr_byte_diff 995 * @a, @b: addresses to be differenced 996 * 997 * There are many places within the TCG backends where we need a byte 998 * difference between two pointers. While this can be accomplished 999 * with local casting, it's easy to get wrong -- especially if one is 1000 * concerned with the signedness of the result. 1001 * 1002 * This version relies on GCC's void pointer arithmetic to get the 1003 * correct result. 1004 */ 1005 1006 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1007 { 1008 return a - b; 1009 } 1010 1011 /** 1012 * tcg_pcrel_diff 1013 * @s: the tcg context 1014 * @target: address of the target 1015 * 1016 * Produce a pc-relative difference, from the current code_ptr 1017 * to the destination address. 1018 */ 1019 1020 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1021 { 1022 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1023 } 1024 1025 /** 1026 * tcg_tbrel_diff 1027 * @s: the tcg context 1028 * @target: address of the target 1029 * 1030 * Produce a difference, from the beginning of the current TB code 1031 * to the destination address. 1032 */ 1033 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1034 { 1035 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1036 } 1037 1038 /** 1039 * tcg_current_code_size 1040 * @s: the tcg context 1041 * 1042 * Compute the current code size within the translation block. 1043 * This is used to fill in qemu's data structures for goto_tb. 1044 */ 1045 1046 static inline size_t tcg_current_code_size(TCGContext *s) 1047 { 1048 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1049 } 1050 1051 /** 1052 * tcg_qemu_tb_exec: 1053 * @env: pointer to CPUArchState for the CPU 1054 * @tb_ptr: address of generated code for the TB to execute 1055 * 1056 * Start executing code from a given translation block. 1057 * Where translation blocks have been linked, execution 1058 * may proceed from the given TB into successive ones. 1059 * Control eventually returns only when some action is needed 1060 * from the top-level loop: either control must pass to a TB 1061 * which has not yet been directly linked, or an asynchronous 1062 * event such as an interrupt needs handling. 1063 * 1064 * Return: The return value is the value passed to the corresponding 1065 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1066 * The value is either zero or a 4-byte aligned pointer to that TB combined 1067 * with additional information in its two least significant bits. The 1068 * additional information is encoded as follows: 1069 * 0, 1: the link between this TB and the next is via the specified 1070 * TB index (0 or 1). That is, we left the TB via (the equivalent 1071 * of) "goto_tb <index>". The main loop uses this to determine 1072 * how to link the TB just executed to the next. 1073 * 2: we are using instruction counting code generation, and we 1074 * did not start executing this TB because the instruction counter 1075 * would hit zero midway through it. In this case the pointer 1076 * returned is the TB we were about to execute, and the caller must 1077 * arrange to execute the remaining count of instructions. 1078 * 3: we stopped because the CPU's exit_request flag was set 1079 * (usually meaning that there is an interrupt that needs to be 1080 * handled). The pointer returned is the TB we were about to execute 1081 * when we noticed the pending exit request. 1082 * 1083 * If the bottom two bits indicate an exit-via-index then the CPU 1084 * state is correctly synchronised and ready for execution of the next 1085 * TB (and in particular the guest PC is the address to execute next). 1086 * Otherwise, we gave up on execution of this TB before it started, and 1087 * the caller must fix up the CPU state by calling the CPU's 1088 * synchronize_from_tb() method with the TB pointer we return (falling 1089 * back to calling the CPU's set_pc method with tb->pb if no 1090 * synchronize_from_tb() method exists). 1091 * 1092 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1093 * to this default (which just calls the prologue.code emitted by 1094 * tcg_target_qemu_prologue()). 1095 */ 1096 #define TB_EXIT_MASK 3 1097 #define TB_EXIT_IDX0 0 1098 #define TB_EXIT_IDX1 1 1099 #define TB_EXIT_IDXMAX 1 1100 #define TB_EXIT_REQUESTED 3 1101 1102 #ifdef CONFIG_TCG_INTERPRETER 1103 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1104 #else 1105 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1106 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1107 #endif 1108 1109 void tcg_register_jit(const void *buf, size_t buf_size); 1110 1111 #if TCG_TARGET_MAYBE_vec 1112 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1113 return > 0 if it is directly supportable; 1114 return < 0 if we must call tcg_expand_vec_op. */ 1115 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1116 #else 1117 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1118 { 1119 return 0; 1120 } 1121 #endif 1122 1123 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1124 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1125 1126 /* Replicate a constant C accoring to the log2 of the element size. */ 1127 uint64_t dup_const(unsigned vece, uint64_t c); 1128 1129 #define dup_const(VECE, C) \ 1130 (__builtin_constant_p(VECE) \ 1131 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1132 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1133 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1134 : (VECE) == MO_64 ? (uint64_t)(C) \ 1135 : (qemu_build_not_reached_always(), 0)) \ 1136 : dup_const(VECE, C)) 1137 1138 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1139 { 1140 #ifdef CONFIG_DEBUG_TCG 1141 const TCGOpcode *o = tcg_ctx->vecop_list; 1142 tcg_ctx->vecop_list = n; 1143 return o; 1144 #else 1145 return NULL; 1146 #endif 1147 } 1148 1149 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1150 1151 #endif /* TCG_H */ 1152