1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 38 /* XXX: make safe guess about sizes */ 39 #define MAX_OP_PER_INSTR 266 40 41 #define MAX_CALL_IARGS 7 42 43 #define CPU_TEMP_BUF_NLONGS 128 44 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 45 46 /* Default target word size to pointer size. */ 47 #ifndef TCG_TARGET_REG_BITS 48 # if UINTPTR_MAX == UINT32_MAX 49 # define TCG_TARGET_REG_BITS 32 50 # elif UINTPTR_MAX == UINT64_MAX 51 # define TCG_TARGET_REG_BITS 64 52 # else 53 # error Unknown pointer size for tcg target 54 # endif 55 #endif 56 57 #if TCG_TARGET_REG_BITS == 32 58 typedef int32_t tcg_target_long; 59 typedef uint32_t tcg_target_ulong; 60 #define TCG_PRIlx PRIx32 61 #define TCG_PRIld PRId32 62 #elif TCG_TARGET_REG_BITS == 64 63 typedef int64_t tcg_target_long; 64 typedef uint64_t tcg_target_ulong; 65 #define TCG_PRIlx PRIx64 66 #define TCG_PRIld PRId64 67 #else 68 #error unsupported 69 #endif 70 71 /* Oversized TCG guests make things like MTTCG hard 72 * as we can't use atomics for cputlb updates. 73 */ 74 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 75 #define TCG_OVERSIZED_GUEST 1 76 #else 77 #define TCG_OVERSIZED_GUEST 0 78 #endif 79 80 #if TCG_TARGET_NB_REGS <= 32 81 typedef uint32_t TCGRegSet; 82 #elif TCG_TARGET_NB_REGS <= 64 83 typedef uint64_t TCGRegSet; 84 #else 85 #error unsupported 86 #endif 87 88 #if TCG_TARGET_REG_BITS == 32 89 /* Turn some undef macros into false macros. */ 90 #define TCG_TARGET_HAS_extrl_i64_i32 0 91 #define TCG_TARGET_HAS_extrh_i64_i32 0 92 #define TCG_TARGET_HAS_div_i64 0 93 #define TCG_TARGET_HAS_rem_i64 0 94 #define TCG_TARGET_HAS_div2_i64 0 95 #define TCG_TARGET_HAS_rot_i64 0 96 #define TCG_TARGET_HAS_ext8s_i64 0 97 #define TCG_TARGET_HAS_ext16s_i64 0 98 #define TCG_TARGET_HAS_ext32s_i64 0 99 #define TCG_TARGET_HAS_ext8u_i64 0 100 #define TCG_TARGET_HAS_ext16u_i64 0 101 #define TCG_TARGET_HAS_ext32u_i64 0 102 #define TCG_TARGET_HAS_bswap16_i64 0 103 #define TCG_TARGET_HAS_bswap32_i64 0 104 #define TCG_TARGET_HAS_bswap64_i64 0 105 #define TCG_TARGET_HAS_neg_i64 0 106 #define TCG_TARGET_HAS_not_i64 0 107 #define TCG_TARGET_HAS_andc_i64 0 108 #define TCG_TARGET_HAS_orc_i64 0 109 #define TCG_TARGET_HAS_eqv_i64 0 110 #define TCG_TARGET_HAS_nand_i64 0 111 #define TCG_TARGET_HAS_nor_i64 0 112 #define TCG_TARGET_HAS_clz_i64 0 113 #define TCG_TARGET_HAS_ctz_i64 0 114 #define TCG_TARGET_HAS_ctpop_i64 0 115 #define TCG_TARGET_HAS_deposit_i64 0 116 #define TCG_TARGET_HAS_extract_i64 0 117 #define TCG_TARGET_HAS_sextract_i64 0 118 #define TCG_TARGET_HAS_extract2_i64 0 119 #define TCG_TARGET_HAS_movcond_i64 0 120 #define TCG_TARGET_HAS_add2_i64 0 121 #define TCG_TARGET_HAS_sub2_i64 0 122 #define TCG_TARGET_HAS_mulu2_i64 0 123 #define TCG_TARGET_HAS_muls2_i64 0 124 #define TCG_TARGET_HAS_muluh_i64 0 125 #define TCG_TARGET_HAS_mulsh_i64 0 126 /* Turn some undef macros into true macros. */ 127 #define TCG_TARGET_HAS_add2_i32 1 128 #define TCG_TARGET_HAS_sub2_i32 1 129 #endif 130 131 #ifndef TCG_TARGET_deposit_i32_valid 132 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 133 #endif 134 #ifndef TCG_TARGET_deposit_i64_valid 135 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 136 #endif 137 #ifndef TCG_TARGET_extract_i32_valid 138 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 139 #endif 140 #ifndef TCG_TARGET_extract_i64_valid 141 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 142 #endif 143 144 /* Only one of DIV or DIV2 should be defined. */ 145 #if defined(TCG_TARGET_HAS_div_i32) 146 #define TCG_TARGET_HAS_div2_i32 0 147 #elif defined(TCG_TARGET_HAS_div2_i32) 148 #define TCG_TARGET_HAS_div_i32 0 149 #define TCG_TARGET_HAS_rem_i32 0 150 #endif 151 #if defined(TCG_TARGET_HAS_div_i64) 152 #define TCG_TARGET_HAS_div2_i64 0 153 #elif defined(TCG_TARGET_HAS_div2_i64) 154 #define TCG_TARGET_HAS_div_i64 0 155 #define TCG_TARGET_HAS_rem_i64 0 156 #endif 157 158 #if !defined(TCG_TARGET_HAS_v64) \ 159 && !defined(TCG_TARGET_HAS_v128) \ 160 && !defined(TCG_TARGET_HAS_v256) 161 #define TCG_TARGET_MAYBE_vec 0 162 #define TCG_TARGET_HAS_abs_vec 0 163 #define TCG_TARGET_HAS_neg_vec 0 164 #define TCG_TARGET_HAS_not_vec 0 165 #define TCG_TARGET_HAS_andc_vec 0 166 #define TCG_TARGET_HAS_orc_vec 0 167 #define TCG_TARGET_HAS_nand_vec 0 168 #define TCG_TARGET_HAS_nor_vec 0 169 #define TCG_TARGET_HAS_eqv_vec 0 170 #define TCG_TARGET_HAS_roti_vec 0 171 #define TCG_TARGET_HAS_rots_vec 0 172 #define TCG_TARGET_HAS_rotv_vec 0 173 #define TCG_TARGET_HAS_shi_vec 0 174 #define TCG_TARGET_HAS_shs_vec 0 175 #define TCG_TARGET_HAS_shv_vec 0 176 #define TCG_TARGET_HAS_mul_vec 0 177 #define TCG_TARGET_HAS_sat_vec 0 178 #define TCG_TARGET_HAS_minmax_vec 0 179 #define TCG_TARGET_HAS_bitsel_vec 0 180 #define TCG_TARGET_HAS_cmpsel_vec 0 181 #else 182 #define TCG_TARGET_MAYBE_vec 1 183 #endif 184 #ifndef TCG_TARGET_HAS_v64 185 #define TCG_TARGET_HAS_v64 0 186 #endif 187 #ifndef TCG_TARGET_HAS_v128 188 #define TCG_TARGET_HAS_v128 0 189 #endif 190 #ifndef TCG_TARGET_HAS_v256 191 #define TCG_TARGET_HAS_v256 0 192 #endif 193 194 #ifndef TARGET_INSN_START_EXTRA_WORDS 195 # define TARGET_INSN_START_WORDS 1 196 #else 197 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 198 #endif 199 200 typedef enum TCGOpcode { 201 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 202 #include "tcg/tcg-opc.h" 203 #undef DEF 204 NB_OPS, 205 } TCGOpcode; 206 207 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 208 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 209 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 210 211 #ifndef TCG_TARGET_INSN_UNIT_SIZE 212 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 213 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 214 typedef uint8_t tcg_insn_unit; 215 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 216 typedef uint16_t tcg_insn_unit; 217 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 218 typedef uint32_t tcg_insn_unit; 219 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 220 typedef uint64_t tcg_insn_unit; 221 #else 222 /* The port better have done this. */ 223 #endif 224 225 226 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS 227 # define tcg_debug_assert(X) do { assert(X); } while (0) 228 #else 229 # define tcg_debug_assert(X) \ 230 do { if (!(X)) { __builtin_unreachable(); } } while (0) 231 #endif 232 233 typedef struct TCGRelocation TCGRelocation; 234 struct TCGRelocation { 235 QSIMPLEQ_ENTRY(TCGRelocation) next; 236 tcg_insn_unit *ptr; 237 intptr_t addend; 238 int type; 239 }; 240 241 typedef struct TCGLabel TCGLabel; 242 struct TCGLabel { 243 unsigned present : 1; 244 unsigned has_value : 1; 245 unsigned id : 14; 246 unsigned refs : 16; 247 union { 248 uintptr_t value; 249 const tcg_insn_unit *value_ptr; 250 } u; 251 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 252 QSIMPLEQ_ENTRY(TCGLabel) next; 253 }; 254 255 typedef struct TCGPool { 256 struct TCGPool *next; 257 int size; 258 uint8_t data[] __attribute__ ((aligned)); 259 } TCGPool; 260 261 #define TCG_POOL_CHUNK_SIZE 32768 262 263 #define TCG_MAX_TEMPS 512 264 #define TCG_MAX_INSNS 512 265 266 /* when the size of the arguments of a called function is smaller than 267 this value, they are statically allocated in the TB stack frame */ 268 #define TCG_STATIC_CALL_ARGS_SIZE 128 269 270 typedef enum TCGType { 271 TCG_TYPE_I32, 272 TCG_TYPE_I64, 273 TCG_TYPE_I128, 274 275 TCG_TYPE_V64, 276 TCG_TYPE_V128, 277 TCG_TYPE_V256, 278 279 /* Number of different types (integer not enum) */ 280 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 281 282 /* An alias for the size of the host register. */ 283 #if TCG_TARGET_REG_BITS == 32 284 TCG_TYPE_REG = TCG_TYPE_I32, 285 #else 286 TCG_TYPE_REG = TCG_TYPE_I64, 287 #endif 288 289 /* An alias for the size of the native pointer. */ 290 #if UINTPTR_MAX == UINT32_MAX 291 TCG_TYPE_PTR = TCG_TYPE_I32, 292 #else 293 TCG_TYPE_PTR = TCG_TYPE_I64, 294 #endif 295 296 /* An alias for the size of the target "long", aka register. */ 297 #if TARGET_LONG_BITS == 64 298 TCG_TYPE_TL = TCG_TYPE_I64, 299 #else 300 TCG_TYPE_TL = TCG_TYPE_I32, 301 #endif 302 } TCGType; 303 304 /** 305 * tcg_type_size 306 * @t: type 307 * 308 * Return the size of the type in bytes. 309 */ 310 static inline int tcg_type_size(TCGType t) 311 { 312 unsigned i = t; 313 if (i >= TCG_TYPE_V64) { 314 tcg_debug_assert(i < TCG_TYPE_COUNT); 315 i -= TCG_TYPE_V64 - 1; 316 } 317 return 4 << i; 318 } 319 320 /** 321 * get_alignment_bits 322 * @memop: MemOp value 323 * 324 * Extract the alignment size from the memop. 325 */ 326 static inline unsigned get_alignment_bits(MemOp memop) 327 { 328 unsigned a = memop & MO_AMASK; 329 330 if (a == MO_UNALN) { 331 /* No alignment required. */ 332 a = 0; 333 } else if (a == MO_ALIGN) { 334 /* A natural alignment requirement. */ 335 a = memop & MO_SIZE; 336 } else { 337 /* A specific alignment requirement. */ 338 a = a >> MO_ASHIFT; 339 } 340 #if defined(CONFIG_SOFTMMU) 341 /* The requested alignment cannot overlap the TLB flags. */ 342 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 343 #endif 344 return a; 345 } 346 347 typedef tcg_target_ulong TCGArg; 348 349 /* Define type and accessor macros for TCG variables. 350 351 TCG variables are the inputs and outputs of TCG ops, as described 352 in tcg/README. Target CPU front-end code uses these types to deal 353 with TCG variables as it emits TCG code via the tcg_gen_* functions. 354 They come in several flavours: 355 * TCGv_i32 : 32 bit integer type 356 * TCGv_i64 : 64 bit integer type 357 * TCGv_i128 : 128 bit integer type 358 * TCGv_ptr : a host pointer type 359 * TCGv_vec : a host vector type; the exact size is not exposed 360 to the CPU front-end code. 361 * TCGv : an integer type the same size as target_ulong 362 (an alias for either TCGv_i32 or TCGv_i64) 363 The compiler's type checking will complain if you mix them 364 up and pass the wrong sized TCGv to a function. 365 366 Users of tcg_gen_* don't need to know about any of the internal 367 details of these, and should treat them as opaque types. 368 You won't be able to look inside them in a debugger either. 369 370 Internal implementation details follow: 371 372 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 373 This is deliberate, because the values we store in variables of type 374 TCGv_i32 are not really pointers-to-structures. They're just small 375 integers, but keeping them in pointer types like this means that the 376 compiler will complain if you accidentally pass a TCGv_i32 to a 377 function which takes a TCGv_i64, and so on. Only the internals of 378 TCG need to care about the actual contents of the types. */ 379 380 typedef struct TCGv_i32_d *TCGv_i32; 381 typedef struct TCGv_i64_d *TCGv_i64; 382 typedef struct TCGv_i128_d *TCGv_i128; 383 typedef struct TCGv_ptr_d *TCGv_ptr; 384 typedef struct TCGv_vec_d *TCGv_vec; 385 typedef TCGv_ptr TCGv_env; 386 #if TARGET_LONG_BITS == 32 387 #define TCGv TCGv_i32 388 #elif TARGET_LONG_BITS == 64 389 #define TCGv TCGv_i64 390 #else 391 #error Unhandled TARGET_LONG_BITS value 392 #endif 393 394 /* call flags */ 395 /* Helper does not read globals (either directly or through an exception). It 396 implies TCG_CALL_NO_WRITE_GLOBALS. */ 397 #define TCG_CALL_NO_READ_GLOBALS 0x0001 398 /* Helper does not write globals */ 399 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 400 /* Helper can be safely suppressed if the return value is not used. */ 401 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 402 /* Helper is G_NORETURN. */ 403 #define TCG_CALL_NO_RETURN 0x0008 404 /* Helper is part of Plugins. */ 405 #define TCG_CALL_PLUGIN 0x0010 406 407 /* convenience version of most used call flags */ 408 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 409 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 410 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 411 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 412 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 413 414 /* 415 * Flags for the bswap opcodes. 416 * If IZ, the input is zero-extended, otherwise unknown. 417 * If OZ or OS, the output is zero- or sign-extended respectively, 418 * otherwise the high bits are undefined. 419 */ 420 enum { 421 TCG_BSWAP_IZ = 1, 422 TCG_BSWAP_OZ = 2, 423 TCG_BSWAP_OS = 4, 424 }; 425 426 typedef enum TCGTempVal { 427 TEMP_VAL_DEAD, 428 TEMP_VAL_REG, 429 TEMP_VAL_MEM, 430 TEMP_VAL_CONST, 431 } TCGTempVal; 432 433 typedef enum TCGTempKind { 434 /* Temp is dead at the end of all basic blocks. */ 435 TEMP_NORMAL, 436 /* Temp is live across conditional branch, but dead otherwise. */ 437 TEMP_EBB, 438 /* Temp is saved across basic blocks but dead at the end of TBs. */ 439 TEMP_LOCAL, 440 /* Temp is saved across both basic blocks and translation blocks. */ 441 TEMP_GLOBAL, 442 /* Temp is in a fixed register. */ 443 TEMP_FIXED, 444 /* Temp is a fixed constant. */ 445 TEMP_CONST, 446 } TCGTempKind; 447 448 typedef struct TCGTemp { 449 TCGReg reg:8; 450 TCGTempVal val_type:8; 451 TCGType base_type:8; 452 TCGType type:8; 453 TCGTempKind kind:3; 454 unsigned int indirect_reg:1; 455 unsigned int indirect_base:1; 456 unsigned int mem_coherent:1; 457 unsigned int mem_allocated:1; 458 unsigned int temp_allocated:1; 459 unsigned int temp_subindex:1; 460 461 int64_t val; 462 struct TCGTemp *mem_base; 463 intptr_t mem_offset; 464 const char *name; 465 466 /* Pass-specific information that can be stored for a temporary. 467 One word worth of integer data, and one pointer to data 468 allocated separately. */ 469 uintptr_t state; 470 void *state_ptr; 471 } TCGTemp; 472 473 typedef struct TCGContext TCGContext; 474 475 typedef struct TCGTempSet { 476 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 477 } TCGTempSet; 478 479 /* 480 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 481 * which leaves a maximum of 28 other slots. Which is enough for 7 482 * 128-bit operands. 483 */ 484 #define DEAD_ARG (1 << 4) 485 #define SYNC_ARG (1 << 0) 486 typedef uint32_t TCGLifeData; 487 488 typedef struct TCGOp { 489 TCGOpcode opc : 8; 490 unsigned nargs : 8; 491 492 /* Parameters for this opcode. See below. */ 493 unsigned param1 : 8; 494 unsigned param2 : 8; 495 496 /* Lifetime data of the operands. */ 497 TCGLifeData life; 498 499 /* Next and previous opcodes. */ 500 QTAILQ_ENTRY(TCGOp) link; 501 502 /* Register preferences for the output(s). */ 503 TCGRegSet output_pref[2]; 504 505 /* Arguments for the opcode. */ 506 TCGArg args[]; 507 } TCGOp; 508 509 #define TCGOP_CALLI(X) (X)->param1 510 #define TCGOP_CALLO(X) (X)->param2 511 512 #define TCGOP_VECL(X) (X)->param1 513 #define TCGOP_VECE(X) (X)->param2 514 515 /* Make sure operands fit in the bitfields above. */ 516 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 517 518 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 519 { 520 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 521 } 522 523 typedef struct TCGProfile { 524 int64_t cpu_exec_time; 525 int64_t tb_count1; 526 int64_t tb_count; 527 int64_t op_count; /* total insn count */ 528 int op_count_max; /* max insn per TB */ 529 int temp_count_max; 530 int64_t temp_count; 531 int64_t del_op_count; 532 int64_t code_in_len; 533 int64_t code_out_len; 534 int64_t search_out_len; 535 int64_t interm_time; 536 int64_t code_time; 537 int64_t la_time; 538 int64_t opt_time; 539 int64_t restore_count; 540 int64_t restore_time; 541 int64_t table_op_count[NB_OPS]; 542 } TCGProfile; 543 544 struct TCGContext { 545 uint8_t *pool_cur, *pool_end; 546 TCGPool *pool_first, *pool_current, *pool_first_large; 547 int nb_labels; 548 int nb_globals; 549 int nb_temps; 550 int nb_indirects; 551 int nb_ops; 552 553 TCGRegSet reserved_regs; 554 intptr_t current_frame_offset; 555 intptr_t frame_start; 556 intptr_t frame_end; 557 TCGTemp *frame_temp; 558 559 TranslationBlock *gen_tb; /* tb for which code is being generated */ 560 tcg_insn_unit *code_buf; /* pointer for start of tb */ 561 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 562 563 #ifdef CONFIG_PROFILER 564 TCGProfile prof; 565 #endif 566 567 #ifdef CONFIG_DEBUG_TCG 568 int temps_in_use; 569 int goto_tb_issue_mask; 570 const TCGOpcode *vecop_list; 571 #endif 572 573 /* Code generation. Note that we specifically do not use tcg_insn_unit 574 here, because there's too much arithmetic throughout that relies 575 on addition and subtraction working on bytes. Rely on the GCC 576 extension that allows arithmetic on void*. */ 577 void *code_gen_buffer; 578 size_t code_gen_buffer_size; 579 void *code_gen_ptr; 580 void *data_gen_ptr; 581 582 /* Threshold to flush the translated code buffer. */ 583 void *code_gen_highwater; 584 585 /* Track which vCPU triggers events */ 586 CPUState *cpu; /* *_trans */ 587 588 /* These structures are private to tcg-target.c.inc. */ 589 #ifdef TCG_TARGET_NEED_LDST_LABELS 590 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 591 #endif 592 #ifdef TCG_TARGET_NEED_POOL_LABELS 593 struct TCGLabelPoolData *pool_labels; 594 #endif 595 596 TCGLabel *exitreq_label; 597 598 #ifdef CONFIG_PLUGIN 599 /* 600 * We keep one plugin_tb struct per TCGContext. Note that on every TB 601 * translation we clear but do not free its contents; this way we 602 * avoid a lot of malloc/free churn, since after a few TB's it's 603 * unlikely that we'll need to allocate either more instructions or more 604 * space for instructions (for variable-instruction-length ISAs). 605 */ 606 struct qemu_plugin_tb *plugin_tb; 607 608 /* descriptor of the instruction being translated */ 609 struct qemu_plugin_insn *plugin_insn; 610 #endif 611 612 GHashTable *const_table[TCG_TYPE_COUNT]; 613 TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; 614 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 615 616 QTAILQ_HEAD(, TCGOp) ops, free_ops; 617 QSIMPLEQ_HEAD(, TCGLabel) labels; 618 619 /* Tells which temporary holds a given register. 620 It does not take into account fixed registers */ 621 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 622 623 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 624 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 625 626 /* Exit to translator on overflow. */ 627 sigjmp_buf jmp_trans; 628 }; 629 630 static inline bool temp_readonly(TCGTemp *ts) 631 { 632 return ts->kind >= TEMP_FIXED; 633 } 634 635 extern __thread TCGContext *tcg_ctx; 636 extern const void *tcg_code_gen_epilogue; 637 extern uintptr_t tcg_splitwx_diff; 638 extern TCGv_env cpu_env; 639 640 bool in_code_gen_buffer(const void *p); 641 642 #ifdef CONFIG_DEBUG_TCG 643 const void *tcg_splitwx_to_rx(void *rw); 644 void *tcg_splitwx_to_rw(const void *rx); 645 #else 646 static inline const void *tcg_splitwx_to_rx(void *rw) 647 { 648 return rw ? rw + tcg_splitwx_diff : NULL; 649 } 650 651 static inline void *tcg_splitwx_to_rw(const void *rx) 652 { 653 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 654 } 655 #endif 656 657 static inline size_t temp_idx(TCGTemp *ts) 658 { 659 ptrdiff_t n = ts - tcg_ctx->temps; 660 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 661 return n; 662 } 663 664 static inline TCGArg temp_arg(TCGTemp *ts) 665 { 666 return (uintptr_t)ts; 667 } 668 669 static inline TCGTemp *arg_temp(TCGArg a) 670 { 671 return (TCGTemp *)(uintptr_t)a; 672 } 673 674 /* Using the offset of a temporary, relative to TCGContext, rather than 675 its index means that we don't use 0. That leaves offset 0 free for 676 a NULL representation without having to leave index 0 unused. */ 677 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 678 { 679 uintptr_t o = (uintptr_t)v; 680 TCGTemp *t = (void *)tcg_ctx + o; 681 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 682 return t; 683 } 684 685 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 686 { 687 return tcgv_i32_temp((TCGv_i32)v); 688 } 689 690 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 691 { 692 return tcgv_i32_temp((TCGv_i32)v); 693 } 694 695 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 696 { 697 return tcgv_i32_temp((TCGv_i32)v); 698 } 699 700 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 701 { 702 return tcgv_i32_temp((TCGv_i32)v); 703 } 704 705 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 706 { 707 return temp_arg(tcgv_i32_temp(v)); 708 } 709 710 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 711 { 712 return temp_arg(tcgv_i64_temp(v)); 713 } 714 715 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 716 { 717 return temp_arg(tcgv_i128_temp(v)); 718 } 719 720 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 721 { 722 return temp_arg(tcgv_ptr_temp(v)); 723 } 724 725 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 726 { 727 return temp_arg(tcgv_vec_temp(v)); 728 } 729 730 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 731 { 732 (void)temp_idx(t); /* trigger embedded assert */ 733 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 734 } 735 736 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 737 { 738 return (TCGv_i64)temp_tcgv_i32(t); 739 } 740 741 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 742 { 743 return (TCGv_i128)temp_tcgv_i32(t); 744 } 745 746 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 747 { 748 return (TCGv_ptr)temp_tcgv_i32(t); 749 } 750 751 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 752 { 753 return (TCGv_vec)temp_tcgv_i32(t); 754 } 755 756 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 757 { 758 return op->args[arg]; 759 } 760 761 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 762 { 763 op->args[arg] = v; 764 } 765 766 static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) 767 { 768 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 769 return tcg_get_insn_param(op, arg); 770 #else 771 return tcg_get_insn_param(op, arg * 2) | 772 ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); 773 #endif 774 } 775 776 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) 777 { 778 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 779 tcg_set_insn_param(op, arg, v); 780 #else 781 tcg_set_insn_param(op, arg * 2, v); 782 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 783 #endif 784 } 785 786 /* The last op that was emitted. */ 787 static inline TCGOp *tcg_last_op(void) 788 { 789 return QTAILQ_LAST(&tcg_ctx->ops); 790 } 791 792 /* Test for whether to terminate the TB for using too many opcodes. */ 793 static inline bool tcg_op_buf_full(void) 794 { 795 /* This is not a hard limit, it merely stops translation when 796 * we have produced "enough" opcodes. We want to limit TB size 797 * such that a RISC host can reasonably use a 16-bit signed 798 * branch within the TB. We also need to be mindful of the 799 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 800 * and TCGContext.gen_insn_end_off[]. 801 */ 802 return tcg_ctx->nb_ops >= 4000; 803 } 804 805 /* pool based memory allocation */ 806 807 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 808 void *tcg_malloc_internal(TCGContext *s, int size); 809 void tcg_pool_reset(TCGContext *s); 810 TranslationBlock *tcg_tb_alloc(TCGContext *s); 811 812 void tcg_region_reset_all(void); 813 814 size_t tcg_code_size(void); 815 size_t tcg_code_capacity(void); 816 817 void tcg_tb_insert(TranslationBlock *tb); 818 void tcg_tb_remove(TranslationBlock *tb); 819 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 820 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 821 size_t tcg_nb_tbs(void); 822 823 /* user-mode: Called with mmap_lock held. */ 824 static inline void *tcg_malloc(int size) 825 { 826 TCGContext *s = tcg_ctx; 827 uint8_t *ptr, *ptr_end; 828 829 /* ??? This is a weak placeholder for minimum malloc alignment. */ 830 size = QEMU_ALIGN_UP(size, 8); 831 832 ptr = s->pool_cur; 833 ptr_end = ptr + size; 834 if (unlikely(ptr_end > s->pool_end)) { 835 return tcg_malloc_internal(tcg_ctx, size); 836 } else { 837 s->pool_cur = ptr_end; 838 return ptr; 839 } 840 } 841 842 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 843 void tcg_register_thread(void); 844 void tcg_prologue_init(TCGContext *s); 845 void tcg_func_start(TCGContext *s); 846 847 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start); 848 849 void tb_target_set_jmp_target(const TranslationBlock *, int, 850 uintptr_t, uintptr_t); 851 852 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 853 854 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 855 intptr_t, const char *); 856 TCGTemp *tcg_temp_new_internal(TCGType, bool); 857 void tcg_temp_free_internal(TCGTemp *); 858 TCGv_vec tcg_temp_new_vec(TCGType type); 859 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 860 861 static inline void tcg_temp_free_i32(TCGv_i32 arg) 862 { 863 tcg_temp_free_internal(tcgv_i32_temp(arg)); 864 } 865 866 static inline void tcg_temp_free_i64(TCGv_i64 arg) 867 { 868 tcg_temp_free_internal(tcgv_i64_temp(arg)); 869 } 870 871 static inline void tcg_temp_free_i128(TCGv_i128 arg) 872 { 873 tcg_temp_free_internal(tcgv_i128_temp(arg)); 874 } 875 876 static inline void tcg_temp_free_ptr(TCGv_ptr arg) 877 { 878 tcg_temp_free_internal(tcgv_ptr_temp(arg)); 879 } 880 881 static inline void tcg_temp_free_vec(TCGv_vec arg) 882 { 883 tcg_temp_free_internal(tcgv_vec_temp(arg)); 884 } 885 886 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 887 const char *name) 888 { 889 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 890 return temp_tcgv_i32(t); 891 } 892 893 static inline TCGv_i32 tcg_temp_new_i32(void) 894 { 895 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); 896 return temp_tcgv_i32(t); 897 } 898 899 static inline TCGv_i32 tcg_temp_local_new_i32(void) 900 { 901 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); 902 return temp_tcgv_i32(t); 903 } 904 905 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 906 const char *name) 907 { 908 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 909 return temp_tcgv_i64(t); 910 } 911 912 static inline TCGv_i64 tcg_temp_new_i64(void) 913 { 914 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); 915 return temp_tcgv_i64(t); 916 } 917 918 static inline TCGv_i64 tcg_temp_local_new_i64(void) 919 { 920 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); 921 return temp_tcgv_i64(t); 922 } 923 924 static inline TCGv_i128 tcg_temp_new_i128(void) 925 { 926 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, false); 927 return temp_tcgv_i128(t); 928 } 929 930 static inline TCGv_i128 tcg_temp_local_new_i128(void) 931 { 932 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, true); 933 return temp_tcgv_i128(t); 934 } 935 936 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 937 const char *name) 938 { 939 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 940 return temp_tcgv_ptr(t); 941 } 942 943 static inline TCGv_ptr tcg_temp_new_ptr(void) 944 { 945 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); 946 return temp_tcgv_ptr(t); 947 } 948 949 static inline TCGv_ptr tcg_temp_local_new_ptr(void) 950 { 951 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); 952 return temp_tcgv_ptr(t); 953 } 954 955 #if defined(CONFIG_DEBUG_TCG) 956 /* If you call tcg_clear_temp_count() at the start of a section of 957 * code which is not supposed to leak any TCG temporaries, then 958 * calling tcg_check_temp_count() at the end of the section will 959 * return 1 if the section did in fact leak a temporary. 960 */ 961 void tcg_clear_temp_count(void); 962 int tcg_check_temp_count(void); 963 #else 964 #define tcg_clear_temp_count() do { } while (0) 965 #define tcg_check_temp_count() 0 966 #endif 967 968 int64_t tcg_cpu_exec_time(void); 969 void tcg_dump_info(GString *buf); 970 void tcg_dump_op_count(GString *buf); 971 972 #define TCG_CT_CONST 1 /* any constant of register size */ 973 974 typedef struct TCGArgConstraint { 975 unsigned ct : 16; 976 unsigned alias_index : 4; 977 unsigned sort_index : 4; 978 unsigned pair_index : 4; 979 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 980 bool oalias : 1; 981 bool ialias : 1; 982 bool newreg : 1; 983 TCGRegSet regs; 984 } TCGArgConstraint; 985 986 #define TCG_MAX_OP_ARGS 16 987 988 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 989 enum { 990 /* Instruction exits the translation block. */ 991 TCG_OPF_BB_EXIT = 0x01, 992 /* Instruction defines the end of a basic block. */ 993 TCG_OPF_BB_END = 0x02, 994 /* Instruction clobbers call registers and potentially update globals. */ 995 TCG_OPF_CALL_CLOBBER = 0x04, 996 /* Instruction has side effects: it cannot be removed if its outputs 997 are not used, and might trigger exceptions. */ 998 TCG_OPF_SIDE_EFFECTS = 0x08, 999 /* Instruction operands are 64-bits (otherwise 32-bits). */ 1000 TCG_OPF_64BIT = 0x10, 1001 /* Instruction is optional and not implemented by the host, or insn 1002 is generic and should not be implemened by the host. */ 1003 TCG_OPF_NOT_PRESENT = 0x20, 1004 /* Instruction operands are vectors. */ 1005 TCG_OPF_VECTOR = 0x40, 1006 /* Instruction is a conditional branch. */ 1007 TCG_OPF_COND_BRANCH = 0x80 1008 }; 1009 1010 typedef struct TCGOpDef { 1011 const char *name; 1012 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 1013 uint8_t flags; 1014 TCGArgConstraint *args_ct; 1015 } TCGOpDef; 1016 1017 extern TCGOpDef tcg_op_defs[]; 1018 extern const size_t tcg_op_defs_max; 1019 1020 typedef struct TCGTargetOpDef { 1021 TCGOpcode op; 1022 const char *args_ct_str[TCG_MAX_OP_ARGS]; 1023 } TCGTargetOpDef; 1024 1025 #define tcg_abort() \ 1026 do {\ 1027 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ 1028 abort();\ 1029 } while (0) 1030 1031 bool tcg_op_supported(TCGOpcode op); 1032 1033 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 1034 1035 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 1036 void tcg_op_remove(TCGContext *s, TCGOp *op); 1037 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 1038 TCGOpcode opc, unsigned nargs); 1039 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 1040 TCGOpcode opc, unsigned nargs); 1041 1042 /** 1043 * tcg_remove_ops_after: 1044 * @op: target operation 1045 * 1046 * Discard any opcodes emitted since @op. Expected usage is to save 1047 * a starting point with tcg_last_op(), speculatively emit opcodes, 1048 * then decide whether or not to keep those opcodes after the fact. 1049 */ 1050 void tcg_remove_ops_after(TCGOp *op); 1051 1052 void tcg_optimize(TCGContext *s); 1053 1054 /* Allocate a new temporary and initialize it with a constant. */ 1055 TCGv_i32 tcg_const_i32(int32_t val); 1056 TCGv_i64 tcg_const_i64(int64_t val); 1057 TCGv_i32 tcg_const_local_i32(int32_t val); 1058 TCGv_i64 tcg_const_local_i64(int64_t val); 1059 TCGv_vec tcg_const_zeros_vec(TCGType); 1060 TCGv_vec tcg_const_ones_vec(TCGType); 1061 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); 1062 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); 1063 1064 /* 1065 * Locate or create a read-only temporary that is a constant. 1066 * This kind of temporary need not be freed, but for convenience 1067 * will be silently ignored by tcg_temp_free_*. 1068 */ 1069 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 1070 1071 static inline TCGv_i32 tcg_constant_i32(int32_t val) 1072 { 1073 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 1074 } 1075 1076 static inline TCGv_i64 tcg_constant_i64(int64_t val) 1077 { 1078 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 1079 } 1080 1081 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 1082 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 1083 1084 #if UINTPTR_MAX == UINT32_MAX 1085 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) 1086 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) 1087 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 1088 #else 1089 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) 1090 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) 1091 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 1092 #endif 1093 1094 TCGLabel *gen_new_label(void); 1095 1096 /** 1097 * label_arg 1098 * @l: label 1099 * 1100 * Encode a label for storage in the TCG opcode stream. 1101 */ 1102 1103 static inline TCGArg label_arg(TCGLabel *l) 1104 { 1105 return (uintptr_t)l; 1106 } 1107 1108 /** 1109 * arg_label 1110 * @i: value 1111 * 1112 * The opposite of label_arg. Retrieve a label from the 1113 * encoding of the TCG opcode stream. 1114 */ 1115 1116 static inline TCGLabel *arg_label(TCGArg i) 1117 { 1118 return (TCGLabel *)(uintptr_t)i; 1119 } 1120 1121 /** 1122 * tcg_ptr_byte_diff 1123 * @a, @b: addresses to be differenced 1124 * 1125 * There are many places within the TCG backends where we need a byte 1126 * difference between two pointers. While this can be accomplished 1127 * with local casting, it's easy to get wrong -- especially if one is 1128 * concerned with the signedness of the result. 1129 * 1130 * This version relies on GCC's void pointer arithmetic to get the 1131 * correct result. 1132 */ 1133 1134 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1135 { 1136 return a - b; 1137 } 1138 1139 /** 1140 * tcg_pcrel_diff 1141 * @s: the tcg context 1142 * @target: address of the target 1143 * 1144 * Produce a pc-relative difference, from the current code_ptr 1145 * to the destination address. 1146 */ 1147 1148 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1149 { 1150 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1151 } 1152 1153 /** 1154 * tcg_tbrel_diff 1155 * @s: the tcg context 1156 * @target: address of the target 1157 * 1158 * Produce a difference, from the beginning of the current TB code 1159 * to the destination address. 1160 */ 1161 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1162 { 1163 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1164 } 1165 1166 /** 1167 * tcg_current_code_size 1168 * @s: the tcg context 1169 * 1170 * Compute the current code size within the translation block. 1171 * This is used to fill in qemu's data structures for goto_tb. 1172 */ 1173 1174 static inline size_t tcg_current_code_size(TCGContext *s) 1175 { 1176 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1177 } 1178 1179 /** 1180 * tcg_qemu_tb_exec: 1181 * @env: pointer to CPUArchState for the CPU 1182 * @tb_ptr: address of generated code for the TB to execute 1183 * 1184 * Start executing code from a given translation block. 1185 * Where translation blocks have been linked, execution 1186 * may proceed from the given TB into successive ones. 1187 * Control eventually returns only when some action is needed 1188 * from the top-level loop: either control must pass to a TB 1189 * which has not yet been directly linked, or an asynchronous 1190 * event such as an interrupt needs handling. 1191 * 1192 * Return: The return value is the value passed to the corresponding 1193 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1194 * The value is either zero or a 4-byte aligned pointer to that TB combined 1195 * with additional information in its two least significant bits. The 1196 * additional information is encoded as follows: 1197 * 0, 1: the link between this TB and the next is via the specified 1198 * TB index (0 or 1). That is, we left the TB via (the equivalent 1199 * of) "goto_tb <index>". The main loop uses this to determine 1200 * how to link the TB just executed to the next. 1201 * 2: we are using instruction counting code generation, and we 1202 * did not start executing this TB because the instruction counter 1203 * would hit zero midway through it. In this case the pointer 1204 * returned is the TB we were about to execute, and the caller must 1205 * arrange to execute the remaining count of instructions. 1206 * 3: we stopped because the CPU's exit_request flag was set 1207 * (usually meaning that there is an interrupt that needs to be 1208 * handled). The pointer returned is the TB we were about to execute 1209 * when we noticed the pending exit request. 1210 * 1211 * If the bottom two bits indicate an exit-via-index then the CPU 1212 * state is correctly synchronised and ready for execution of the next 1213 * TB (and in particular the guest PC is the address to execute next). 1214 * Otherwise, we gave up on execution of this TB before it started, and 1215 * the caller must fix up the CPU state by calling the CPU's 1216 * synchronize_from_tb() method with the TB pointer we return (falling 1217 * back to calling the CPU's set_pc method with tb->pb if no 1218 * synchronize_from_tb() method exists). 1219 * 1220 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1221 * to this default (which just calls the prologue.code emitted by 1222 * tcg_target_qemu_prologue()). 1223 */ 1224 #define TB_EXIT_MASK 3 1225 #define TB_EXIT_IDX0 0 1226 #define TB_EXIT_IDX1 1 1227 #define TB_EXIT_IDXMAX 1 1228 #define TB_EXIT_REQUESTED 3 1229 1230 #ifdef CONFIG_TCG_INTERPRETER 1231 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1232 #else 1233 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1234 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1235 #endif 1236 1237 void tcg_register_jit(const void *buf, size_t buf_size); 1238 1239 #if TCG_TARGET_MAYBE_vec 1240 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1241 return > 0 if it is directly supportable; 1242 return < 0 if we must call tcg_expand_vec_op. */ 1243 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1244 #else 1245 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1246 { 1247 return 0; 1248 } 1249 #endif 1250 1251 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1252 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1253 1254 /* Replicate a constant C accoring to the log2 of the element size. */ 1255 uint64_t dup_const(unsigned vece, uint64_t c); 1256 1257 #define dup_const(VECE, C) \ 1258 (__builtin_constant_p(VECE) \ 1259 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1260 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1261 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1262 : (VECE) == MO_64 ? (uint64_t)(C) \ 1263 : (qemu_build_not_reached_always(), 0)) \ 1264 : dup_const(VECE, C)) 1265 1266 #if TARGET_LONG_BITS == 64 1267 # define dup_const_tl dup_const 1268 #else 1269 # define dup_const_tl(VECE, C) \ 1270 (__builtin_constant_p(VECE) \ 1271 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1272 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1273 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1274 : (qemu_build_not_reached_always(), 0)) \ 1275 : (target_long)dup_const(VECE, C)) 1276 #endif 1277 1278 #ifdef CONFIG_DEBUG_TCG 1279 void tcg_assert_listed_vecop(TCGOpcode); 1280 #else 1281 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1282 #endif 1283 1284 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1285 { 1286 #ifdef CONFIG_DEBUG_TCG 1287 const TCGOpcode *o = tcg_ctx->vecop_list; 1288 tcg_ctx->vecop_list = n; 1289 return o; 1290 #else 1291 return NULL; 1292 #endif 1293 } 1294 1295 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1296 1297 #endif /* TCG_H */ 1298