1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "exec/memop.h" 29 #include "exec/memopidx.h" 30 #include "qemu/bitops.h" 31 #include "qemu/plugin.h" 32 #include "qemu/queue.h" 33 #include "tcg/tcg-mo.h" 34 #include "tcg-target-reg-bits.h" 35 #include "tcg-target.h" 36 #include "tcg/tcg-cond.h" 37 #include "tcg/debug-assert.h" 38 39 /* XXX: make safe guess about sizes */ 40 #define MAX_OP_PER_INSTR 266 41 42 #define CPU_TEMP_BUF_NLONGS 128 43 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 44 45 #if TCG_TARGET_REG_BITS == 32 46 typedef int32_t tcg_target_long; 47 typedef uint32_t tcg_target_ulong; 48 #define TCG_PRIlx PRIx32 49 #define TCG_PRIld PRId32 50 #elif TCG_TARGET_REG_BITS == 64 51 typedef int64_t tcg_target_long; 52 typedef uint64_t tcg_target_ulong; 53 #define TCG_PRIlx PRIx64 54 #define TCG_PRIld PRId64 55 #else 56 #error unsupported 57 #endif 58 59 #if TCG_TARGET_NB_REGS <= 32 60 typedef uint32_t TCGRegSet; 61 #elif TCG_TARGET_NB_REGS <= 64 62 typedef uint64_t TCGRegSet; 63 #else 64 #error unsupported 65 #endif 66 67 #if TCG_TARGET_REG_BITS == 32 68 /* Turn some undef macros into false macros. */ 69 #define TCG_TARGET_HAS_extr_i64_i32 0 70 #define TCG_TARGET_HAS_div_i64 0 71 #define TCG_TARGET_HAS_rem_i64 0 72 #define TCG_TARGET_HAS_div2_i64 0 73 #define TCG_TARGET_HAS_rot_i64 0 74 #define TCG_TARGET_HAS_ext8s_i64 0 75 #define TCG_TARGET_HAS_ext16s_i64 0 76 #define TCG_TARGET_HAS_ext32s_i64 0 77 #define TCG_TARGET_HAS_ext8u_i64 0 78 #define TCG_TARGET_HAS_ext16u_i64 0 79 #define TCG_TARGET_HAS_ext32u_i64 0 80 #define TCG_TARGET_HAS_bswap16_i64 0 81 #define TCG_TARGET_HAS_bswap32_i64 0 82 #define TCG_TARGET_HAS_bswap64_i64 0 83 #define TCG_TARGET_HAS_not_i64 0 84 #define TCG_TARGET_HAS_andc_i64 0 85 #define TCG_TARGET_HAS_orc_i64 0 86 #define TCG_TARGET_HAS_eqv_i64 0 87 #define TCG_TARGET_HAS_nand_i64 0 88 #define TCG_TARGET_HAS_nor_i64 0 89 #define TCG_TARGET_HAS_clz_i64 0 90 #define TCG_TARGET_HAS_ctz_i64 0 91 #define TCG_TARGET_HAS_ctpop_i64 0 92 #define TCG_TARGET_HAS_deposit_i64 0 93 #define TCG_TARGET_HAS_extract_i64 0 94 #define TCG_TARGET_HAS_sextract_i64 0 95 #define TCG_TARGET_HAS_extract2_i64 0 96 #define TCG_TARGET_HAS_negsetcond_i64 0 97 #define TCG_TARGET_HAS_add2_i64 0 98 #define TCG_TARGET_HAS_sub2_i64 0 99 #define TCG_TARGET_HAS_mulu2_i64 0 100 #define TCG_TARGET_HAS_muls2_i64 0 101 #define TCG_TARGET_HAS_muluh_i64 0 102 #define TCG_TARGET_HAS_mulsh_i64 0 103 /* Turn some undef macros into true macros. */ 104 #define TCG_TARGET_HAS_add2_i32 1 105 #define TCG_TARGET_HAS_sub2_i32 1 106 #endif 107 108 #ifndef TCG_TARGET_deposit_i32_valid 109 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 110 #endif 111 #ifndef TCG_TARGET_deposit_i64_valid 112 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 113 #endif 114 #ifndef TCG_TARGET_extract_i32_valid 115 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 116 #endif 117 #ifndef TCG_TARGET_extract_i64_valid 118 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 119 #endif 120 121 /* Only one of DIV or DIV2 should be defined. */ 122 #if defined(TCG_TARGET_HAS_div_i32) 123 #define TCG_TARGET_HAS_div2_i32 0 124 #elif defined(TCG_TARGET_HAS_div2_i32) 125 #define TCG_TARGET_HAS_div_i32 0 126 #define TCG_TARGET_HAS_rem_i32 0 127 #endif 128 #if defined(TCG_TARGET_HAS_div_i64) 129 #define TCG_TARGET_HAS_div2_i64 0 130 #elif defined(TCG_TARGET_HAS_div2_i64) 131 #define TCG_TARGET_HAS_div_i64 0 132 #define TCG_TARGET_HAS_rem_i64 0 133 #endif 134 135 #if !defined(TCG_TARGET_HAS_v64) \ 136 && !defined(TCG_TARGET_HAS_v128) \ 137 && !defined(TCG_TARGET_HAS_v256) 138 #define TCG_TARGET_MAYBE_vec 0 139 #define TCG_TARGET_HAS_abs_vec 0 140 #define TCG_TARGET_HAS_neg_vec 0 141 #define TCG_TARGET_HAS_not_vec 0 142 #define TCG_TARGET_HAS_andc_vec 0 143 #define TCG_TARGET_HAS_orc_vec 0 144 #define TCG_TARGET_HAS_nand_vec 0 145 #define TCG_TARGET_HAS_nor_vec 0 146 #define TCG_TARGET_HAS_eqv_vec 0 147 #define TCG_TARGET_HAS_roti_vec 0 148 #define TCG_TARGET_HAS_rots_vec 0 149 #define TCG_TARGET_HAS_rotv_vec 0 150 #define TCG_TARGET_HAS_shi_vec 0 151 #define TCG_TARGET_HAS_shs_vec 0 152 #define TCG_TARGET_HAS_shv_vec 0 153 #define TCG_TARGET_HAS_mul_vec 0 154 #define TCG_TARGET_HAS_sat_vec 0 155 #define TCG_TARGET_HAS_minmax_vec 0 156 #define TCG_TARGET_HAS_bitsel_vec 0 157 #define TCG_TARGET_HAS_cmpsel_vec 0 158 #else 159 #define TCG_TARGET_MAYBE_vec 1 160 #endif 161 #ifndef TCG_TARGET_HAS_v64 162 #define TCG_TARGET_HAS_v64 0 163 #endif 164 #ifndef TCG_TARGET_HAS_v128 165 #define TCG_TARGET_HAS_v128 0 166 #endif 167 #ifndef TCG_TARGET_HAS_v256 168 #define TCG_TARGET_HAS_v256 0 169 #endif 170 171 typedef enum TCGOpcode { 172 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 173 #include "tcg/tcg-opc.h" 174 #undef DEF 175 NB_OPS, 176 } TCGOpcode; 177 178 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 179 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 180 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 181 182 #ifndef TCG_TARGET_INSN_UNIT_SIZE 183 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 184 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 185 typedef uint8_t tcg_insn_unit; 186 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 187 typedef uint16_t tcg_insn_unit; 188 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 189 typedef uint32_t tcg_insn_unit; 190 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 191 typedef uint64_t tcg_insn_unit; 192 #else 193 /* The port better have done this. */ 194 #endif 195 196 typedef struct TCGRelocation TCGRelocation; 197 struct TCGRelocation { 198 QSIMPLEQ_ENTRY(TCGRelocation) next; 199 tcg_insn_unit *ptr; 200 intptr_t addend; 201 int type; 202 }; 203 204 typedef struct TCGOp TCGOp; 205 typedef struct TCGLabelUse TCGLabelUse; 206 struct TCGLabelUse { 207 QSIMPLEQ_ENTRY(TCGLabelUse) next; 208 TCGOp *op; 209 }; 210 211 typedef struct TCGLabel TCGLabel; 212 struct TCGLabel { 213 bool present; 214 bool has_value; 215 uint16_t id; 216 union { 217 uintptr_t value; 218 const tcg_insn_unit *value_ptr; 219 } u; 220 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 221 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 222 QSIMPLEQ_ENTRY(TCGLabel) next; 223 }; 224 225 typedef struct TCGPool { 226 struct TCGPool *next; 227 int size; 228 uint8_t data[] __attribute__ ((aligned)); 229 } TCGPool; 230 231 #define TCG_POOL_CHUNK_SIZE 32768 232 233 #define TCG_MAX_TEMPS 512 234 #define TCG_MAX_INSNS 512 235 236 /* when the size of the arguments of a called function is smaller than 237 this value, they are statically allocated in the TB stack frame */ 238 #define TCG_STATIC_CALL_ARGS_SIZE 128 239 240 typedef enum TCGType { 241 TCG_TYPE_I32, 242 TCG_TYPE_I64, 243 TCG_TYPE_I128, 244 245 TCG_TYPE_V64, 246 TCG_TYPE_V128, 247 TCG_TYPE_V256, 248 249 /* Number of different types (integer not enum) */ 250 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 251 252 /* An alias for the size of the host register. */ 253 #if TCG_TARGET_REG_BITS == 32 254 TCG_TYPE_REG = TCG_TYPE_I32, 255 #else 256 TCG_TYPE_REG = TCG_TYPE_I64, 257 #endif 258 259 /* An alias for the size of the native pointer. */ 260 #if UINTPTR_MAX == UINT32_MAX 261 TCG_TYPE_PTR = TCG_TYPE_I32, 262 #else 263 TCG_TYPE_PTR = TCG_TYPE_I64, 264 #endif 265 } TCGType; 266 267 /** 268 * tcg_type_size 269 * @t: type 270 * 271 * Return the size of the type in bytes. 272 */ 273 static inline int tcg_type_size(TCGType t) 274 { 275 unsigned i = t; 276 if (i >= TCG_TYPE_V64) { 277 tcg_debug_assert(i < TCG_TYPE_COUNT); 278 i -= TCG_TYPE_V64 - 1; 279 } 280 return 4 << i; 281 } 282 283 /** 284 * get_alignment_bits 285 * @memop: MemOp value 286 * 287 * Extract the alignment size from the memop. 288 */ 289 static inline unsigned get_alignment_bits(MemOp memop) 290 { 291 unsigned a = memop & MO_AMASK; 292 293 if (a == MO_UNALN) { 294 /* No alignment required. */ 295 a = 0; 296 } else if (a == MO_ALIGN) { 297 /* A natural alignment requirement. */ 298 a = memop & MO_SIZE; 299 } else { 300 /* A specific alignment requirement. */ 301 a = a >> MO_ASHIFT; 302 } 303 return a; 304 } 305 306 typedef tcg_target_ulong TCGArg; 307 308 /* Define type and accessor macros for TCG variables. 309 310 TCG variables are the inputs and outputs of TCG ops, as described 311 in tcg/README. Target CPU front-end code uses these types to deal 312 with TCG variables as it emits TCG code via the tcg_gen_* functions. 313 They come in several flavours: 314 * TCGv_i32 : 32 bit integer type 315 * TCGv_i64 : 64 bit integer type 316 * TCGv_i128 : 128 bit integer type 317 * TCGv_ptr : a host pointer type 318 * TCGv_vec : a host vector type; the exact size is not exposed 319 to the CPU front-end code. 320 * TCGv : an integer type the same size as target_ulong 321 (an alias for either TCGv_i32 or TCGv_i64) 322 The compiler's type checking will complain if you mix them 323 up and pass the wrong sized TCGv to a function. 324 325 Users of tcg_gen_* don't need to know about any of the internal 326 details of these, and should treat them as opaque types. 327 You won't be able to look inside them in a debugger either. 328 329 Internal implementation details follow: 330 331 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 332 This is deliberate, because the values we store in variables of type 333 TCGv_i32 are not really pointers-to-structures. They're just small 334 integers, but keeping them in pointer types like this means that the 335 compiler will complain if you accidentally pass a TCGv_i32 to a 336 function which takes a TCGv_i64, and so on. Only the internals of 337 TCG need to care about the actual contents of the types. */ 338 339 typedef struct TCGv_i32_d *TCGv_i32; 340 typedef struct TCGv_i64_d *TCGv_i64; 341 typedef struct TCGv_i128_d *TCGv_i128; 342 typedef struct TCGv_ptr_d *TCGv_ptr; 343 typedef struct TCGv_vec_d *TCGv_vec; 344 typedef TCGv_ptr TCGv_env; 345 346 /* call flags */ 347 /* Helper does not read globals (either directly or through an exception). It 348 implies TCG_CALL_NO_WRITE_GLOBALS. */ 349 #define TCG_CALL_NO_READ_GLOBALS 0x0001 350 /* Helper does not write globals */ 351 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 352 /* Helper can be safely suppressed if the return value is not used. */ 353 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 354 /* Helper is G_NORETURN. */ 355 #define TCG_CALL_NO_RETURN 0x0008 356 357 /* convenience version of most used call flags */ 358 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 359 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 360 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 361 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 362 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 363 364 /* 365 * Flags for the bswap opcodes. 366 * If IZ, the input is zero-extended, otherwise unknown. 367 * If OZ or OS, the output is zero- or sign-extended respectively, 368 * otherwise the high bits are undefined. 369 */ 370 enum { 371 TCG_BSWAP_IZ = 1, 372 TCG_BSWAP_OZ = 2, 373 TCG_BSWAP_OS = 4, 374 }; 375 376 typedef enum TCGTempVal { 377 TEMP_VAL_DEAD, 378 TEMP_VAL_REG, 379 TEMP_VAL_MEM, 380 TEMP_VAL_CONST, 381 } TCGTempVal; 382 383 typedef enum TCGTempKind { 384 /* 385 * Temp is dead at the end of the extended basic block (EBB), 386 * the single-entry multiple-exit region that falls through 387 * conditional branches. 388 */ 389 TEMP_EBB, 390 /* Temp is live across the entire translation block, but dead at end. */ 391 TEMP_TB, 392 /* Temp is live across the entire translation block, and between them. */ 393 TEMP_GLOBAL, 394 /* Temp is in a fixed register. */ 395 TEMP_FIXED, 396 /* Temp is a fixed constant. */ 397 TEMP_CONST, 398 } TCGTempKind; 399 400 typedef struct TCGTemp { 401 TCGReg reg:8; 402 TCGTempVal val_type:8; 403 TCGType base_type:8; 404 TCGType type:8; 405 TCGTempKind kind:3; 406 unsigned int indirect_reg:1; 407 unsigned int indirect_base:1; 408 unsigned int mem_coherent:1; 409 unsigned int mem_allocated:1; 410 unsigned int temp_allocated:1; 411 unsigned int temp_subindex:2; 412 413 int64_t val; 414 struct TCGTemp *mem_base; 415 intptr_t mem_offset; 416 const char *name; 417 418 /* Pass-specific information that can be stored for a temporary. 419 One word worth of integer data, and one pointer to data 420 allocated separately. */ 421 uintptr_t state; 422 void *state_ptr; 423 } TCGTemp; 424 425 typedef struct TCGContext TCGContext; 426 427 typedef struct TCGTempSet { 428 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 429 } TCGTempSet; 430 431 /* 432 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 433 * which leaves a maximum of 28 other slots. Which is enough for 7 434 * 128-bit operands. 435 */ 436 #define DEAD_ARG (1 << 4) 437 #define SYNC_ARG (1 << 0) 438 typedef uint32_t TCGLifeData; 439 440 struct TCGOp { 441 TCGOpcode opc : 8; 442 unsigned nargs : 8; 443 444 /* Parameters for this opcode. See below. */ 445 unsigned param1 : 8; 446 unsigned param2 : 8; 447 448 /* Lifetime data of the operands. */ 449 TCGLifeData life; 450 451 /* Next and previous opcodes. */ 452 QTAILQ_ENTRY(TCGOp) link; 453 454 /* Register preferences for the output(s). */ 455 TCGRegSet output_pref[2]; 456 457 /* Arguments for the opcode. */ 458 TCGArg args[]; 459 }; 460 461 #define TCGOP_CALLI(X) (X)->param1 462 #define TCGOP_CALLO(X) (X)->param2 463 464 #define TCGOP_VECL(X) (X)->param1 465 #define TCGOP_VECE(X) (X)->param2 466 467 /* Make sure operands fit in the bitfields above. */ 468 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 469 470 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 471 { 472 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 473 } 474 475 struct TCGContext { 476 uint8_t *pool_cur, *pool_end; 477 TCGPool *pool_first, *pool_current, *pool_first_large; 478 int nb_labels; 479 int nb_globals; 480 int nb_temps; 481 int nb_indirects; 482 int nb_ops; 483 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 484 485 int page_mask; 486 uint8_t page_bits; 487 uint8_t tlb_dyn_max_bits; 488 uint8_t insn_start_words; 489 TCGBar guest_mo; 490 491 TCGRegSet reserved_regs; 492 intptr_t current_frame_offset; 493 intptr_t frame_start; 494 intptr_t frame_end; 495 TCGTemp *frame_temp; 496 497 TranslationBlock *gen_tb; /* tb for which code is being generated */ 498 tcg_insn_unit *code_buf; /* pointer for start of tb */ 499 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 500 501 #ifdef CONFIG_DEBUG_TCG 502 int goto_tb_issue_mask; 503 const TCGOpcode *vecop_list; 504 #endif 505 506 /* Code generation. Note that we specifically do not use tcg_insn_unit 507 here, because there's too much arithmetic throughout that relies 508 on addition and subtraction working on bytes. Rely on the GCC 509 extension that allows arithmetic on void*. */ 510 void *code_gen_buffer; 511 size_t code_gen_buffer_size; 512 void *code_gen_ptr; 513 void *data_gen_ptr; 514 515 /* Threshold to flush the translated code buffer. */ 516 void *code_gen_highwater; 517 518 /* Track which vCPU triggers events */ 519 CPUState *cpu; /* *_trans */ 520 521 /* These structures are private to tcg-target.c.inc. */ 522 #ifdef TCG_TARGET_NEED_LDST_LABELS 523 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 524 #endif 525 #ifdef TCG_TARGET_NEED_POOL_LABELS 526 struct TCGLabelPoolData *pool_labels; 527 #endif 528 529 TCGLabel *exitreq_label; 530 531 #ifdef CONFIG_PLUGIN 532 /* 533 * We keep one plugin_tb struct per TCGContext. Note that on every TB 534 * translation we clear but do not free its contents; this way we 535 * avoid a lot of malloc/free churn, since after a few TB's it's 536 * unlikely that we'll need to allocate either more instructions or more 537 * space for instructions (for variable-instruction-length ISAs). 538 */ 539 struct qemu_plugin_tb *plugin_tb; 540 541 /* descriptor of the instruction being translated */ 542 struct qemu_plugin_insn *plugin_insn; 543 #endif 544 545 GHashTable *const_table[TCG_TYPE_COUNT]; 546 TCGTempSet free_temps[TCG_TYPE_COUNT]; 547 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 548 549 QTAILQ_HEAD(, TCGOp) ops, free_ops; 550 QSIMPLEQ_HEAD(, TCGLabel) labels; 551 552 /* 553 * When clear, new ops are added to the tail of @ops. 554 * When set, new ops are added in front of @emit_before_op. 555 */ 556 TCGOp *emit_before_op; 557 558 /* Tells which temporary holds a given register. 559 It does not take into account fixed registers */ 560 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 561 562 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 563 uint64_t *gen_insn_data; 564 565 /* Exit to translator on overflow. */ 566 sigjmp_buf jmp_trans; 567 }; 568 569 static inline bool temp_readonly(TCGTemp *ts) 570 { 571 return ts->kind >= TEMP_FIXED; 572 } 573 574 #ifdef CONFIG_USER_ONLY 575 extern bool tcg_use_softmmu; 576 #else 577 #define tcg_use_softmmu true 578 #endif 579 580 extern __thread TCGContext *tcg_ctx; 581 extern const void *tcg_code_gen_epilogue; 582 extern uintptr_t tcg_splitwx_diff; 583 extern TCGv_env tcg_env; 584 585 bool in_code_gen_buffer(const void *p); 586 587 #ifdef CONFIG_DEBUG_TCG 588 const void *tcg_splitwx_to_rx(void *rw); 589 void *tcg_splitwx_to_rw(const void *rx); 590 #else 591 static inline const void *tcg_splitwx_to_rx(void *rw) 592 { 593 return rw ? rw + tcg_splitwx_diff : NULL; 594 } 595 596 static inline void *tcg_splitwx_to_rw(const void *rx) 597 { 598 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 599 } 600 #endif 601 602 static inline TCGArg temp_arg(TCGTemp *ts) 603 { 604 return (uintptr_t)ts; 605 } 606 607 static inline TCGTemp *arg_temp(TCGArg a) 608 { 609 return (TCGTemp *)(uintptr_t)a; 610 } 611 612 #ifdef CONFIG_DEBUG_TCG 613 size_t temp_idx(TCGTemp *ts); 614 TCGTemp *tcgv_i32_temp(TCGv_i32 v); 615 #else 616 static inline size_t temp_idx(TCGTemp *ts) 617 { 618 return ts - tcg_ctx->temps; 619 } 620 621 /* 622 * Using the offset of a temporary, relative to TCGContext, rather than 623 * its index means that we don't use 0. That leaves offset 0 free for 624 * a NULL representation without having to leave index 0 unused. 625 */ 626 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 627 { 628 return (void *)tcg_ctx + (uintptr_t)v; 629 } 630 #endif 631 632 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 633 { 634 return tcgv_i32_temp((TCGv_i32)v); 635 } 636 637 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 638 { 639 return tcgv_i32_temp((TCGv_i32)v); 640 } 641 642 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 643 { 644 return tcgv_i32_temp((TCGv_i32)v); 645 } 646 647 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 648 { 649 return tcgv_i32_temp((TCGv_i32)v); 650 } 651 652 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 653 { 654 return temp_arg(tcgv_i32_temp(v)); 655 } 656 657 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 658 { 659 return temp_arg(tcgv_i64_temp(v)); 660 } 661 662 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 663 { 664 return temp_arg(tcgv_i128_temp(v)); 665 } 666 667 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 668 { 669 return temp_arg(tcgv_ptr_temp(v)); 670 } 671 672 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 673 { 674 return temp_arg(tcgv_vec_temp(v)); 675 } 676 677 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 678 { 679 (void)temp_idx(t); /* trigger embedded assert */ 680 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 681 } 682 683 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 684 { 685 return (TCGv_i64)temp_tcgv_i32(t); 686 } 687 688 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 689 { 690 return (TCGv_i128)temp_tcgv_i32(t); 691 } 692 693 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 694 { 695 return (TCGv_ptr)temp_tcgv_i32(t); 696 } 697 698 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 699 { 700 return (TCGv_vec)temp_tcgv_i32(t); 701 } 702 703 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 704 { 705 return op->args[arg]; 706 } 707 708 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 709 { 710 op->args[arg] = v; 711 } 712 713 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 714 { 715 if (TCG_TARGET_REG_BITS == 64) { 716 return tcg_get_insn_param(op, arg); 717 } else { 718 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 719 tcg_get_insn_param(op, arg * 2 + 1)); 720 } 721 } 722 723 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 724 { 725 if (TCG_TARGET_REG_BITS == 64) { 726 tcg_set_insn_param(op, arg, v); 727 } else { 728 tcg_set_insn_param(op, arg * 2, v); 729 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 730 } 731 } 732 733 /* The last op that was emitted. */ 734 static inline TCGOp *tcg_last_op(void) 735 { 736 return QTAILQ_LAST(&tcg_ctx->ops); 737 } 738 739 /* Test for whether to terminate the TB for using too many opcodes. */ 740 static inline bool tcg_op_buf_full(void) 741 { 742 /* This is not a hard limit, it merely stops translation when 743 * we have produced "enough" opcodes. We want to limit TB size 744 * such that a RISC host can reasonably use a 16-bit signed 745 * branch within the TB. We also need to be mindful of the 746 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 747 * and TCGContext.gen_insn_end_off[]. 748 */ 749 return tcg_ctx->nb_ops >= 4000; 750 } 751 752 /* pool based memory allocation */ 753 754 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 755 void *tcg_malloc_internal(TCGContext *s, int size); 756 void tcg_pool_reset(TCGContext *s); 757 TranslationBlock *tcg_tb_alloc(TCGContext *s); 758 759 void tcg_region_reset_all(void); 760 761 size_t tcg_code_size(void); 762 size_t tcg_code_capacity(void); 763 764 void tcg_tb_insert(TranslationBlock *tb); 765 void tcg_tb_remove(TranslationBlock *tb); 766 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 767 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 768 size_t tcg_nb_tbs(void); 769 770 /* user-mode: Called with mmap_lock held. */ 771 static inline void *tcg_malloc(int size) 772 { 773 TCGContext *s = tcg_ctx; 774 uint8_t *ptr, *ptr_end; 775 776 /* ??? This is a weak placeholder for minimum malloc alignment. */ 777 size = QEMU_ALIGN_UP(size, 8); 778 779 ptr = s->pool_cur; 780 ptr_end = ptr + size; 781 if (unlikely(ptr_end > s->pool_end)) { 782 return tcg_malloc_internal(tcg_ctx, size); 783 } else { 784 s->pool_cur = ptr_end; 785 return ptr; 786 } 787 } 788 789 void tcg_func_start(TCGContext *s); 790 791 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 792 793 void tb_target_set_jmp_target(const TranslationBlock *, int, 794 uintptr_t, uintptr_t); 795 796 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 797 798 #define TCG_CT_CONST 1 /* any constant of register size */ 799 800 typedef struct TCGArgConstraint { 801 unsigned ct : 16; 802 unsigned alias_index : 4; 803 unsigned sort_index : 4; 804 unsigned pair_index : 4; 805 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 806 bool oalias : 1; 807 bool ialias : 1; 808 bool newreg : 1; 809 TCGRegSet regs; 810 } TCGArgConstraint; 811 812 #define TCG_MAX_OP_ARGS 16 813 814 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 815 enum { 816 /* Instruction exits the translation block. */ 817 TCG_OPF_BB_EXIT = 0x01, 818 /* Instruction defines the end of a basic block. */ 819 TCG_OPF_BB_END = 0x02, 820 /* Instruction clobbers call registers and potentially update globals. */ 821 TCG_OPF_CALL_CLOBBER = 0x04, 822 /* Instruction has side effects: it cannot be removed if its outputs 823 are not used, and might trigger exceptions. */ 824 TCG_OPF_SIDE_EFFECTS = 0x08, 825 /* Instruction operands are 64-bits (otherwise 32-bits). */ 826 TCG_OPF_64BIT = 0x10, 827 /* Instruction is optional and not implemented by the host, or insn 828 is generic and should not be implemented by the host. */ 829 TCG_OPF_NOT_PRESENT = 0x20, 830 /* Instruction operands are vectors. */ 831 TCG_OPF_VECTOR = 0x40, 832 /* Instruction is a conditional branch. */ 833 TCG_OPF_COND_BRANCH = 0x80 834 }; 835 836 typedef struct TCGOpDef { 837 const char *name; 838 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 839 uint8_t flags; 840 TCGArgConstraint *args_ct; 841 } TCGOpDef; 842 843 extern TCGOpDef tcg_op_defs[]; 844 extern const size_t tcg_op_defs_max; 845 846 typedef struct TCGTargetOpDef { 847 TCGOpcode op; 848 const char *args_ct_str[TCG_MAX_OP_ARGS]; 849 } TCGTargetOpDef; 850 851 bool tcg_op_supported(TCGOpcode op); 852 853 void tcg_gen_call0(void *func, TCGHelperInfo *, TCGTemp *ret); 854 void tcg_gen_call1(void *func, TCGHelperInfo *, TCGTemp *ret, TCGTemp *); 855 void tcg_gen_call2(void *func, TCGHelperInfo *, TCGTemp *ret, 856 TCGTemp *, TCGTemp *); 857 void tcg_gen_call3(void *func, TCGHelperInfo *, TCGTemp *ret, 858 TCGTemp *, TCGTemp *, TCGTemp *); 859 void tcg_gen_call4(void *func, TCGHelperInfo *, TCGTemp *ret, 860 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); 861 void tcg_gen_call5(void *func, TCGHelperInfo *, TCGTemp *ret, 862 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); 863 void tcg_gen_call6(void *func, TCGHelperInfo *, TCGTemp *ret, 864 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, 865 TCGTemp *, TCGTemp *); 866 void tcg_gen_call7(void *func, TCGHelperInfo *, TCGTemp *ret, 867 TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, 868 TCGTemp *, TCGTemp *, TCGTemp *); 869 870 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 871 void tcg_op_remove(TCGContext *s, TCGOp *op); 872 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 873 TCGOpcode opc, unsigned nargs); 874 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 875 TCGOpcode opc, unsigned nargs); 876 877 /** 878 * tcg_remove_ops_after: 879 * @op: target operation 880 * 881 * Discard any opcodes emitted since @op. Expected usage is to save 882 * a starting point with tcg_last_op(), speculatively emit opcodes, 883 * then decide whether or not to keep those opcodes after the fact. 884 */ 885 void tcg_remove_ops_after(TCGOp *op); 886 887 void tcg_optimize(TCGContext *s); 888 889 TCGLabel *gen_new_label(void); 890 891 /** 892 * label_arg 893 * @l: label 894 * 895 * Encode a label for storage in the TCG opcode stream. 896 */ 897 898 static inline TCGArg label_arg(TCGLabel *l) 899 { 900 return (uintptr_t)l; 901 } 902 903 /** 904 * arg_label 905 * @i: value 906 * 907 * The opposite of label_arg. Retrieve a label from the 908 * encoding of the TCG opcode stream. 909 */ 910 911 static inline TCGLabel *arg_label(TCGArg i) 912 { 913 return (TCGLabel *)(uintptr_t)i; 914 } 915 916 /** 917 * tcg_ptr_byte_diff 918 * @a, @b: addresses to be differenced 919 * 920 * There are many places within the TCG backends where we need a byte 921 * difference between two pointers. While this can be accomplished 922 * with local casting, it's easy to get wrong -- especially if one is 923 * concerned with the signedness of the result. 924 * 925 * This version relies on GCC's void pointer arithmetic to get the 926 * correct result. 927 */ 928 929 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 930 { 931 return a - b; 932 } 933 934 /** 935 * tcg_pcrel_diff 936 * @s: the tcg context 937 * @target: address of the target 938 * 939 * Produce a pc-relative difference, from the current code_ptr 940 * to the destination address. 941 */ 942 943 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 944 { 945 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 946 } 947 948 /** 949 * tcg_tbrel_diff 950 * @s: the tcg context 951 * @target: address of the target 952 * 953 * Produce a difference, from the beginning of the current TB code 954 * to the destination address. 955 */ 956 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 957 { 958 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 959 } 960 961 /** 962 * tcg_current_code_size 963 * @s: the tcg context 964 * 965 * Compute the current code size within the translation block. 966 * This is used to fill in qemu's data structures for goto_tb. 967 */ 968 969 static inline size_t tcg_current_code_size(TCGContext *s) 970 { 971 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 972 } 973 974 /** 975 * tcg_qemu_tb_exec: 976 * @env: pointer to CPUArchState for the CPU 977 * @tb_ptr: address of generated code for the TB to execute 978 * 979 * Start executing code from a given translation block. 980 * Where translation blocks have been linked, execution 981 * may proceed from the given TB into successive ones. 982 * Control eventually returns only when some action is needed 983 * from the top-level loop: either control must pass to a TB 984 * which has not yet been directly linked, or an asynchronous 985 * event such as an interrupt needs handling. 986 * 987 * Return: The return value is the value passed to the corresponding 988 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 989 * The value is either zero or a 4-byte aligned pointer to that TB combined 990 * with additional information in its two least significant bits. The 991 * additional information is encoded as follows: 992 * 0, 1: the link between this TB and the next is via the specified 993 * TB index (0 or 1). That is, we left the TB via (the equivalent 994 * of) "goto_tb <index>". The main loop uses this to determine 995 * how to link the TB just executed to the next. 996 * 2: we are using instruction counting code generation, and we 997 * did not start executing this TB because the instruction counter 998 * would hit zero midway through it. In this case the pointer 999 * returned is the TB we were about to execute, and the caller must 1000 * arrange to execute the remaining count of instructions. 1001 * 3: we stopped because the CPU's exit_request flag was set 1002 * (usually meaning that there is an interrupt that needs to be 1003 * handled). The pointer returned is the TB we were about to execute 1004 * when we noticed the pending exit request. 1005 * 1006 * If the bottom two bits indicate an exit-via-index then the CPU 1007 * state is correctly synchronised and ready for execution of the next 1008 * TB (and in particular the guest PC is the address to execute next). 1009 * Otherwise, we gave up on execution of this TB before it started, and 1010 * the caller must fix up the CPU state by calling the CPU's 1011 * synchronize_from_tb() method with the TB pointer we return (falling 1012 * back to calling the CPU's set_pc method with tb->pb if no 1013 * synchronize_from_tb() method exists). 1014 * 1015 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1016 * to this default (which just calls the prologue.code emitted by 1017 * tcg_target_qemu_prologue()). 1018 */ 1019 #define TB_EXIT_MASK 3 1020 #define TB_EXIT_IDX0 0 1021 #define TB_EXIT_IDX1 1 1022 #define TB_EXIT_IDXMAX 1 1023 #define TB_EXIT_REQUESTED 3 1024 1025 #ifdef CONFIG_TCG_INTERPRETER 1026 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1027 #else 1028 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1029 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1030 #endif 1031 1032 void tcg_register_jit(const void *buf, size_t buf_size); 1033 1034 #if TCG_TARGET_MAYBE_vec 1035 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1036 return > 0 if it is directly supportable; 1037 return < 0 if we must call tcg_expand_vec_op. */ 1038 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1039 #else 1040 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1041 { 1042 return 0; 1043 } 1044 #endif 1045 1046 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1047 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1048 1049 /* Replicate a constant C according to the log2 of the element size. */ 1050 uint64_t dup_const(unsigned vece, uint64_t c); 1051 1052 #define dup_const(VECE, C) \ 1053 (__builtin_constant_p(VECE) \ 1054 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1055 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1056 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1057 : (VECE) == MO_64 ? (uint64_t)(C) \ 1058 : (qemu_build_not_reached_always(), 0)) \ 1059 : dup_const(VECE, C)) 1060 1061 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1062 { 1063 #ifdef CONFIG_DEBUG_TCG 1064 const TCGOpcode *o = tcg_ctx->vecop_list; 1065 tcg_ctx->vecop_list = n; 1066 return o; 1067 #else 1068 return NULL; 1069 #endif 1070 } 1071 1072 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1073 void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs); 1074 1075 #endif /* TCG_H */ 1076