1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_H 26 #define TCG_H 27 28 #include "cpu.h" 29 #include "exec/memop.h" 30 #include "exec/memopidx.h" 31 #include "qemu/bitops.h" 32 #include "qemu/plugin.h" 33 #include "qemu/queue.h" 34 #include "tcg/tcg-mo.h" 35 #include "tcg-target-reg-bits.h" 36 #include "tcg-target.h" 37 #include "tcg/tcg-cond.h" 38 #include "tcg/debug-assert.h" 39 40 /* XXX: make safe guess about sizes */ 41 #define MAX_OP_PER_INSTR 266 42 43 #define MAX_CALL_IARGS 7 44 45 #define CPU_TEMP_BUF_NLONGS 128 46 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) 47 48 #if TCG_TARGET_REG_BITS == 32 49 typedef int32_t tcg_target_long; 50 typedef uint32_t tcg_target_ulong; 51 #define TCG_PRIlx PRIx32 52 #define TCG_PRIld PRId32 53 #elif TCG_TARGET_REG_BITS == 64 54 typedef int64_t tcg_target_long; 55 typedef uint64_t tcg_target_ulong; 56 #define TCG_PRIlx PRIx64 57 #define TCG_PRIld PRId64 58 #else 59 #error unsupported 60 #endif 61 62 #if TCG_TARGET_NB_REGS <= 32 63 typedef uint32_t TCGRegSet; 64 #elif TCG_TARGET_NB_REGS <= 64 65 typedef uint64_t TCGRegSet; 66 #else 67 #error unsupported 68 #endif 69 70 #if TCG_TARGET_REG_BITS == 32 71 /* Turn some undef macros into false macros. */ 72 #define TCG_TARGET_HAS_extrl_i64_i32 0 73 #define TCG_TARGET_HAS_extrh_i64_i32 0 74 #define TCG_TARGET_HAS_div_i64 0 75 #define TCG_TARGET_HAS_rem_i64 0 76 #define TCG_TARGET_HAS_div2_i64 0 77 #define TCG_TARGET_HAS_rot_i64 0 78 #define TCG_TARGET_HAS_ext8s_i64 0 79 #define TCG_TARGET_HAS_ext16s_i64 0 80 #define TCG_TARGET_HAS_ext32s_i64 0 81 #define TCG_TARGET_HAS_ext8u_i64 0 82 #define TCG_TARGET_HAS_ext16u_i64 0 83 #define TCG_TARGET_HAS_ext32u_i64 0 84 #define TCG_TARGET_HAS_bswap16_i64 0 85 #define TCG_TARGET_HAS_bswap32_i64 0 86 #define TCG_TARGET_HAS_bswap64_i64 0 87 #define TCG_TARGET_HAS_neg_i64 0 88 #define TCG_TARGET_HAS_not_i64 0 89 #define TCG_TARGET_HAS_andc_i64 0 90 #define TCG_TARGET_HAS_orc_i64 0 91 #define TCG_TARGET_HAS_eqv_i64 0 92 #define TCG_TARGET_HAS_nand_i64 0 93 #define TCG_TARGET_HAS_nor_i64 0 94 #define TCG_TARGET_HAS_clz_i64 0 95 #define TCG_TARGET_HAS_ctz_i64 0 96 #define TCG_TARGET_HAS_ctpop_i64 0 97 #define TCG_TARGET_HAS_deposit_i64 0 98 #define TCG_TARGET_HAS_extract_i64 0 99 #define TCG_TARGET_HAS_sextract_i64 0 100 #define TCG_TARGET_HAS_extract2_i64 0 101 #define TCG_TARGET_HAS_movcond_i64 0 102 #define TCG_TARGET_HAS_add2_i64 0 103 #define TCG_TARGET_HAS_sub2_i64 0 104 #define TCG_TARGET_HAS_mulu2_i64 0 105 #define TCG_TARGET_HAS_muls2_i64 0 106 #define TCG_TARGET_HAS_muluh_i64 0 107 #define TCG_TARGET_HAS_mulsh_i64 0 108 /* Turn some undef macros into true macros. */ 109 #define TCG_TARGET_HAS_add2_i32 1 110 #define TCG_TARGET_HAS_sub2_i32 1 111 #endif 112 113 #ifndef TCG_TARGET_deposit_i32_valid 114 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 115 #endif 116 #ifndef TCG_TARGET_deposit_i64_valid 117 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 118 #endif 119 #ifndef TCG_TARGET_extract_i32_valid 120 #define TCG_TARGET_extract_i32_valid(ofs, len) 1 121 #endif 122 #ifndef TCG_TARGET_extract_i64_valid 123 #define TCG_TARGET_extract_i64_valid(ofs, len) 1 124 #endif 125 126 /* Only one of DIV or DIV2 should be defined. */ 127 #if defined(TCG_TARGET_HAS_div_i32) 128 #define TCG_TARGET_HAS_div2_i32 0 129 #elif defined(TCG_TARGET_HAS_div2_i32) 130 #define TCG_TARGET_HAS_div_i32 0 131 #define TCG_TARGET_HAS_rem_i32 0 132 #endif 133 #if defined(TCG_TARGET_HAS_div_i64) 134 #define TCG_TARGET_HAS_div2_i64 0 135 #elif defined(TCG_TARGET_HAS_div2_i64) 136 #define TCG_TARGET_HAS_div_i64 0 137 #define TCG_TARGET_HAS_rem_i64 0 138 #endif 139 140 #if !defined(TCG_TARGET_HAS_v64) \ 141 && !defined(TCG_TARGET_HAS_v128) \ 142 && !defined(TCG_TARGET_HAS_v256) 143 #define TCG_TARGET_MAYBE_vec 0 144 #define TCG_TARGET_HAS_abs_vec 0 145 #define TCG_TARGET_HAS_neg_vec 0 146 #define TCG_TARGET_HAS_not_vec 0 147 #define TCG_TARGET_HAS_andc_vec 0 148 #define TCG_TARGET_HAS_orc_vec 0 149 #define TCG_TARGET_HAS_nand_vec 0 150 #define TCG_TARGET_HAS_nor_vec 0 151 #define TCG_TARGET_HAS_eqv_vec 0 152 #define TCG_TARGET_HAS_roti_vec 0 153 #define TCG_TARGET_HAS_rots_vec 0 154 #define TCG_TARGET_HAS_rotv_vec 0 155 #define TCG_TARGET_HAS_shi_vec 0 156 #define TCG_TARGET_HAS_shs_vec 0 157 #define TCG_TARGET_HAS_shv_vec 0 158 #define TCG_TARGET_HAS_mul_vec 0 159 #define TCG_TARGET_HAS_sat_vec 0 160 #define TCG_TARGET_HAS_minmax_vec 0 161 #define TCG_TARGET_HAS_bitsel_vec 0 162 #define TCG_TARGET_HAS_cmpsel_vec 0 163 #else 164 #define TCG_TARGET_MAYBE_vec 1 165 #endif 166 #ifndef TCG_TARGET_HAS_v64 167 #define TCG_TARGET_HAS_v64 0 168 #endif 169 #ifndef TCG_TARGET_HAS_v128 170 #define TCG_TARGET_HAS_v128 0 171 #endif 172 #ifndef TCG_TARGET_HAS_v256 173 #define TCG_TARGET_HAS_v256 0 174 #endif 175 176 #ifndef TARGET_INSN_START_EXTRA_WORDS 177 # define TARGET_INSN_START_WORDS 1 178 #else 179 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) 180 #endif 181 182 typedef enum TCGOpcode { 183 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, 184 #include "tcg/tcg-opc.h" 185 #undef DEF 186 NB_OPS, 187 } TCGOpcode; 188 189 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) 190 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) 191 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) 192 193 #ifndef TCG_TARGET_INSN_UNIT_SIZE 194 # error "Missing TCG_TARGET_INSN_UNIT_SIZE" 195 #elif TCG_TARGET_INSN_UNIT_SIZE == 1 196 typedef uint8_t tcg_insn_unit; 197 #elif TCG_TARGET_INSN_UNIT_SIZE == 2 198 typedef uint16_t tcg_insn_unit; 199 #elif TCG_TARGET_INSN_UNIT_SIZE == 4 200 typedef uint32_t tcg_insn_unit; 201 #elif TCG_TARGET_INSN_UNIT_SIZE == 8 202 typedef uint64_t tcg_insn_unit; 203 #else 204 /* The port better have done this. */ 205 #endif 206 207 typedef struct TCGRelocation TCGRelocation; 208 struct TCGRelocation { 209 QSIMPLEQ_ENTRY(TCGRelocation) next; 210 tcg_insn_unit *ptr; 211 intptr_t addend; 212 int type; 213 }; 214 215 typedef struct TCGOp TCGOp; 216 typedef struct TCGLabelUse TCGLabelUse; 217 struct TCGLabelUse { 218 QSIMPLEQ_ENTRY(TCGLabelUse) next; 219 TCGOp *op; 220 }; 221 222 typedef struct TCGLabel TCGLabel; 223 struct TCGLabel { 224 bool present; 225 bool has_value; 226 uint16_t id; 227 union { 228 uintptr_t value; 229 const tcg_insn_unit *value_ptr; 230 } u; 231 QSIMPLEQ_HEAD(, TCGLabelUse) branches; 232 QSIMPLEQ_HEAD(, TCGRelocation) relocs; 233 QSIMPLEQ_ENTRY(TCGLabel) next; 234 }; 235 236 typedef struct TCGPool { 237 struct TCGPool *next; 238 int size; 239 uint8_t data[] __attribute__ ((aligned)); 240 } TCGPool; 241 242 #define TCG_POOL_CHUNK_SIZE 32768 243 244 #define TCG_MAX_TEMPS 512 245 #define TCG_MAX_INSNS 512 246 247 /* when the size of the arguments of a called function is smaller than 248 this value, they are statically allocated in the TB stack frame */ 249 #define TCG_STATIC_CALL_ARGS_SIZE 128 250 251 typedef enum TCGType { 252 TCG_TYPE_I32, 253 TCG_TYPE_I64, 254 TCG_TYPE_I128, 255 256 TCG_TYPE_V64, 257 TCG_TYPE_V128, 258 TCG_TYPE_V256, 259 260 /* Number of different types (integer not enum) */ 261 #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) 262 263 /* An alias for the size of the host register. */ 264 #if TCG_TARGET_REG_BITS == 32 265 TCG_TYPE_REG = TCG_TYPE_I32, 266 #else 267 TCG_TYPE_REG = TCG_TYPE_I64, 268 #endif 269 270 /* An alias for the size of the native pointer. */ 271 #if UINTPTR_MAX == UINT32_MAX 272 TCG_TYPE_PTR = TCG_TYPE_I32, 273 #else 274 TCG_TYPE_PTR = TCG_TYPE_I64, 275 #endif 276 } TCGType; 277 278 /** 279 * tcg_type_size 280 * @t: type 281 * 282 * Return the size of the type in bytes. 283 */ 284 static inline int tcg_type_size(TCGType t) 285 { 286 unsigned i = t; 287 if (i >= TCG_TYPE_V64) { 288 tcg_debug_assert(i < TCG_TYPE_COUNT); 289 i -= TCG_TYPE_V64 - 1; 290 } 291 return 4 << i; 292 } 293 294 /** 295 * get_alignment_bits 296 * @memop: MemOp value 297 * 298 * Extract the alignment size from the memop. 299 */ 300 static inline unsigned get_alignment_bits(MemOp memop) 301 { 302 unsigned a = memop & MO_AMASK; 303 304 if (a == MO_UNALN) { 305 /* No alignment required. */ 306 a = 0; 307 } else if (a == MO_ALIGN) { 308 /* A natural alignment requirement. */ 309 a = memop & MO_SIZE; 310 } else { 311 /* A specific alignment requirement. */ 312 a = a >> MO_ASHIFT; 313 } 314 #if defined(CONFIG_SOFTMMU) 315 /* The requested alignment cannot overlap the TLB flags. */ 316 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); 317 #endif 318 return a; 319 } 320 321 typedef tcg_target_ulong TCGArg; 322 323 /* Define type and accessor macros for TCG variables. 324 325 TCG variables are the inputs and outputs of TCG ops, as described 326 in tcg/README. Target CPU front-end code uses these types to deal 327 with TCG variables as it emits TCG code via the tcg_gen_* functions. 328 They come in several flavours: 329 * TCGv_i32 : 32 bit integer type 330 * TCGv_i64 : 64 bit integer type 331 * TCGv_i128 : 128 bit integer type 332 * TCGv_ptr : a host pointer type 333 * TCGv_vec : a host vector type; the exact size is not exposed 334 to the CPU front-end code. 335 * TCGv : an integer type the same size as target_ulong 336 (an alias for either TCGv_i32 or TCGv_i64) 337 The compiler's type checking will complain if you mix them 338 up and pass the wrong sized TCGv to a function. 339 340 Users of tcg_gen_* don't need to know about any of the internal 341 details of these, and should treat them as opaque types. 342 You won't be able to look inside them in a debugger either. 343 344 Internal implementation details follow: 345 346 Note that there is no definition of the structs TCGv_i32_d etc anywhere. 347 This is deliberate, because the values we store in variables of type 348 TCGv_i32 are not really pointers-to-structures. They're just small 349 integers, but keeping them in pointer types like this means that the 350 compiler will complain if you accidentally pass a TCGv_i32 to a 351 function which takes a TCGv_i64, and so on. Only the internals of 352 TCG need to care about the actual contents of the types. */ 353 354 typedef struct TCGv_i32_d *TCGv_i32; 355 typedef struct TCGv_i64_d *TCGv_i64; 356 typedef struct TCGv_i128_d *TCGv_i128; 357 typedef struct TCGv_ptr_d *TCGv_ptr; 358 typedef struct TCGv_vec_d *TCGv_vec; 359 typedef TCGv_ptr TCGv_env; 360 #if TARGET_LONG_BITS == 32 361 #define TCGv TCGv_i32 362 #elif TARGET_LONG_BITS == 64 363 #define TCGv TCGv_i64 364 #else 365 #error Unhandled TARGET_LONG_BITS value 366 #endif 367 368 /* call flags */ 369 /* Helper does not read globals (either directly or through an exception). It 370 implies TCG_CALL_NO_WRITE_GLOBALS. */ 371 #define TCG_CALL_NO_READ_GLOBALS 0x0001 372 /* Helper does not write globals */ 373 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 374 /* Helper can be safely suppressed if the return value is not used. */ 375 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 376 /* Helper is G_NORETURN. */ 377 #define TCG_CALL_NO_RETURN 0x0008 378 /* Helper is part of Plugins. */ 379 #define TCG_CALL_PLUGIN 0x0010 380 381 /* convenience version of most used call flags */ 382 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS 383 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS 384 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS 385 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) 386 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) 387 388 /* 389 * Flags for the bswap opcodes. 390 * If IZ, the input is zero-extended, otherwise unknown. 391 * If OZ or OS, the output is zero- or sign-extended respectively, 392 * otherwise the high bits are undefined. 393 */ 394 enum { 395 TCG_BSWAP_IZ = 1, 396 TCG_BSWAP_OZ = 2, 397 TCG_BSWAP_OS = 4, 398 }; 399 400 typedef enum TCGTempVal { 401 TEMP_VAL_DEAD, 402 TEMP_VAL_REG, 403 TEMP_VAL_MEM, 404 TEMP_VAL_CONST, 405 } TCGTempVal; 406 407 typedef enum TCGTempKind { 408 /* 409 * Temp is dead at the end of the extended basic block (EBB), 410 * the single-entry multiple-exit region that falls through 411 * conditional branches. 412 */ 413 TEMP_EBB, 414 /* Temp is live across the entire translation block, but dead at end. */ 415 TEMP_TB, 416 /* Temp is live across the entire translation block, and between them. */ 417 TEMP_GLOBAL, 418 /* Temp is in a fixed register. */ 419 TEMP_FIXED, 420 /* Temp is a fixed constant. */ 421 TEMP_CONST, 422 } TCGTempKind; 423 424 typedef struct TCGTemp { 425 TCGReg reg:8; 426 TCGTempVal val_type:8; 427 TCGType base_type:8; 428 TCGType type:8; 429 TCGTempKind kind:3; 430 unsigned int indirect_reg:1; 431 unsigned int indirect_base:1; 432 unsigned int mem_coherent:1; 433 unsigned int mem_allocated:1; 434 unsigned int temp_allocated:1; 435 unsigned int temp_subindex:1; 436 437 int64_t val; 438 struct TCGTemp *mem_base; 439 intptr_t mem_offset; 440 const char *name; 441 442 /* Pass-specific information that can be stored for a temporary. 443 One word worth of integer data, and one pointer to data 444 allocated separately. */ 445 uintptr_t state; 446 void *state_ptr; 447 } TCGTemp; 448 449 typedef struct TCGContext TCGContext; 450 451 typedef struct TCGTempSet { 452 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; 453 } TCGTempSet; 454 455 /* 456 * With 1 128-bit output, a 32-bit host requires 4 output parameters, 457 * which leaves a maximum of 28 other slots. Which is enough for 7 458 * 128-bit operands. 459 */ 460 #define DEAD_ARG (1 << 4) 461 #define SYNC_ARG (1 << 0) 462 typedef uint32_t TCGLifeData; 463 464 struct TCGOp { 465 TCGOpcode opc : 8; 466 unsigned nargs : 8; 467 468 /* Parameters for this opcode. See below. */ 469 unsigned param1 : 8; 470 unsigned param2 : 8; 471 472 /* Lifetime data of the operands. */ 473 TCGLifeData life; 474 475 /* Next and previous opcodes. */ 476 QTAILQ_ENTRY(TCGOp) link; 477 478 /* Register preferences for the output(s). */ 479 TCGRegSet output_pref[2]; 480 481 /* Arguments for the opcode. */ 482 TCGArg args[]; 483 }; 484 485 #define TCGOP_CALLI(X) (X)->param1 486 #define TCGOP_CALLO(X) (X)->param2 487 488 #define TCGOP_VECL(X) (X)->param1 489 #define TCGOP_VECE(X) (X)->param2 490 491 /* Make sure operands fit in the bitfields above. */ 492 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); 493 494 static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) 495 { 496 return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; 497 } 498 499 typedef struct TCGProfile { 500 int64_t cpu_exec_time; 501 int64_t tb_count1; 502 int64_t tb_count; 503 int64_t op_count; /* total insn count */ 504 int op_count_max; /* max insn per TB */ 505 int temp_count_max; 506 int64_t temp_count; 507 int64_t del_op_count; 508 int64_t code_in_len; 509 int64_t code_out_len; 510 int64_t search_out_len; 511 int64_t interm_time; 512 int64_t code_time; 513 int64_t la_time; 514 int64_t opt_time; 515 int64_t restore_count; 516 int64_t restore_time; 517 int64_t table_op_count[NB_OPS]; 518 } TCGProfile; 519 520 struct TCGContext { 521 uint8_t *pool_cur, *pool_end; 522 TCGPool *pool_first, *pool_current, *pool_first_large; 523 int nb_labels; 524 int nb_globals; 525 int nb_temps; 526 int nb_indirects; 527 int nb_ops; 528 TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ 529 530 #ifdef CONFIG_SOFTMMU 531 int tlb_fast_offset; 532 int page_mask; 533 uint8_t page_bits; 534 uint8_t tlb_dyn_max_bits; 535 #endif 536 537 TCGRegSet reserved_regs; 538 intptr_t current_frame_offset; 539 intptr_t frame_start; 540 intptr_t frame_end; 541 TCGTemp *frame_temp; 542 543 TranslationBlock *gen_tb; /* tb for which code is being generated */ 544 tcg_insn_unit *code_buf; /* pointer for start of tb */ 545 tcg_insn_unit *code_ptr; /* pointer for running end of tb */ 546 547 #ifdef CONFIG_PROFILER 548 TCGProfile prof; 549 #endif 550 551 #ifdef CONFIG_DEBUG_TCG 552 int goto_tb_issue_mask; 553 const TCGOpcode *vecop_list; 554 #endif 555 556 /* Code generation. Note that we specifically do not use tcg_insn_unit 557 here, because there's too much arithmetic throughout that relies 558 on addition and subtraction working on bytes. Rely on the GCC 559 extension that allows arithmetic on void*. */ 560 void *code_gen_buffer; 561 size_t code_gen_buffer_size; 562 void *code_gen_ptr; 563 void *data_gen_ptr; 564 565 /* Threshold to flush the translated code buffer. */ 566 void *code_gen_highwater; 567 568 /* Track which vCPU triggers events */ 569 CPUState *cpu; /* *_trans */ 570 571 /* These structures are private to tcg-target.c.inc. */ 572 #ifdef TCG_TARGET_NEED_LDST_LABELS 573 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; 574 #endif 575 #ifdef TCG_TARGET_NEED_POOL_LABELS 576 struct TCGLabelPoolData *pool_labels; 577 #endif 578 579 TCGLabel *exitreq_label; 580 581 #ifdef CONFIG_PLUGIN 582 /* 583 * We keep one plugin_tb struct per TCGContext. Note that on every TB 584 * translation we clear but do not free its contents; this way we 585 * avoid a lot of malloc/free churn, since after a few TB's it's 586 * unlikely that we'll need to allocate either more instructions or more 587 * space for instructions (for variable-instruction-length ISAs). 588 */ 589 struct qemu_plugin_tb *plugin_tb; 590 591 /* descriptor of the instruction being translated */ 592 struct qemu_plugin_insn *plugin_insn; 593 #endif 594 595 GHashTable *const_table[TCG_TYPE_COUNT]; 596 TCGTempSet free_temps[TCG_TYPE_COUNT]; 597 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ 598 599 QTAILQ_HEAD(, TCGOp) ops, free_ops; 600 QSIMPLEQ_HEAD(, TCGLabel) labels; 601 602 /* Tells which temporary holds a given register. 603 It does not take into account fixed registers */ 604 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; 605 606 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; 607 uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; 608 609 /* Exit to translator on overflow. */ 610 sigjmp_buf jmp_trans; 611 }; 612 613 static inline bool temp_readonly(TCGTemp *ts) 614 { 615 return ts->kind >= TEMP_FIXED; 616 } 617 618 extern __thread TCGContext *tcg_ctx; 619 extern const void *tcg_code_gen_epilogue; 620 extern uintptr_t tcg_splitwx_diff; 621 extern TCGv_env cpu_env; 622 623 bool in_code_gen_buffer(const void *p); 624 625 #ifdef CONFIG_DEBUG_TCG 626 const void *tcg_splitwx_to_rx(void *rw); 627 void *tcg_splitwx_to_rw(const void *rx); 628 #else 629 static inline const void *tcg_splitwx_to_rx(void *rw) 630 { 631 return rw ? rw + tcg_splitwx_diff : NULL; 632 } 633 634 static inline void *tcg_splitwx_to_rw(const void *rx) 635 { 636 return rx ? (void *)rx - tcg_splitwx_diff : NULL; 637 } 638 #endif 639 640 static inline size_t temp_idx(TCGTemp *ts) 641 { 642 ptrdiff_t n = ts - tcg_ctx->temps; 643 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); 644 return n; 645 } 646 647 static inline TCGArg temp_arg(TCGTemp *ts) 648 { 649 return (uintptr_t)ts; 650 } 651 652 static inline TCGTemp *arg_temp(TCGArg a) 653 { 654 return (TCGTemp *)(uintptr_t)a; 655 } 656 657 /* Using the offset of a temporary, relative to TCGContext, rather than 658 its index means that we don't use 0. That leaves offset 0 free for 659 a NULL representation without having to leave index 0 unused. */ 660 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) 661 { 662 uintptr_t o = (uintptr_t)v; 663 TCGTemp *t = (void *)tcg_ctx + o; 664 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); 665 return t; 666 } 667 668 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) 669 { 670 return tcgv_i32_temp((TCGv_i32)v); 671 } 672 673 static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) 674 { 675 return tcgv_i32_temp((TCGv_i32)v); 676 } 677 678 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) 679 { 680 return tcgv_i32_temp((TCGv_i32)v); 681 } 682 683 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) 684 { 685 return tcgv_i32_temp((TCGv_i32)v); 686 } 687 688 static inline TCGArg tcgv_i32_arg(TCGv_i32 v) 689 { 690 return temp_arg(tcgv_i32_temp(v)); 691 } 692 693 static inline TCGArg tcgv_i64_arg(TCGv_i64 v) 694 { 695 return temp_arg(tcgv_i64_temp(v)); 696 } 697 698 static inline TCGArg tcgv_i128_arg(TCGv_i128 v) 699 { 700 return temp_arg(tcgv_i128_temp(v)); 701 } 702 703 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) 704 { 705 return temp_arg(tcgv_ptr_temp(v)); 706 } 707 708 static inline TCGArg tcgv_vec_arg(TCGv_vec v) 709 { 710 return temp_arg(tcgv_vec_temp(v)); 711 } 712 713 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) 714 { 715 (void)temp_idx(t); /* trigger embedded assert */ 716 return (TCGv_i32)((void *)t - (void *)tcg_ctx); 717 } 718 719 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) 720 { 721 return (TCGv_i64)temp_tcgv_i32(t); 722 } 723 724 static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) 725 { 726 return (TCGv_i128)temp_tcgv_i32(t); 727 } 728 729 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) 730 { 731 return (TCGv_ptr)temp_tcgv_i32(t); 732 } 733 734 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) 735 { 736 return (TCGv_vec)temp_tcgv_i32(t); 737 } 738 739 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) 740 { 741 return op->args[arg]; 742 } 743 744 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) 745 { 746 op->args[arg] = v; 747 } 748 749 static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) 750 { 751 if (TCG_TARGET_REG_BITS == 64) { 752 return tcg_get_insn_param(op, arg); 753 } else { 754 return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, 755 tcg_get_insn_param(op, arg * 2 + 1)); 756 } 757 } 758 759 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) 760 { 761 if (TCG_TARGET_REG_BITS == 64) { 762 tcg_set_insn_param(op, arg, v); 763 } else { 764 tcg_set_insn_param(op, arg * 2, v); 765 tcg_set_insn_param(op, arg * 2 + 1, v >> 32); 766 } 767 } 768 769 /* The last op that was emitted. */ 770 static inline TCGOp *tcg_last_op(void) 771 { 772 return QTAILQ_LAST(&tcg_ctx->ops); 773 } 774 775 /* Test for whether to terminate the TB for using too many opcodes. */ 776 static inline bool tcg_op_buf_full(void) 777 { 778 /* This is not a hard limit, it merely stops translation when 779 * we have produced "enough" opcodes. We want to limit TB size 780 * such that a RISC host can reasonably use a 16-bit signed 781 * branch within the TB. We also need to be mindful of the 782 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] 783 * and TCGContext.gen_insn_end_off[]. 784 */ 785 return tcg_ctx->nb_ops >= 4000; 786 } 787 788 /* pool based memory allocation */ 789 790 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ 791 void *tcg_malloc_internal(TCGContext *s, int size); 792 void tcg_pool_reset(TCGContext *s); 793 TranslationBlock *tcg_tb_alloc(TCGContext *s); 794 795 void tcg_region_reset_all(void); 796 797 size_t tcg_code_size(void); 798 size_t tcg_code_capacity(void); 799 800 void tcg_tb_insert(TranslationBlock *tb); 801 void tcg_tb_remove(TranslationBlock *tb); 802 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); 803 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); 804 size_t tcg_nb_tbs(void); 805 806 /* user-mode: Called with mmap_lock held. */ 807 static inline void *tcg_malloc(int size) 808 { 809 TCGContext *s = tcg_ctx; 810 uint8_t *ptr, *ptr_end; 811 812 /* ??? This is a weak placeholder for minimum malloc alignment. */ 813 size = QEMU_ALIGN_UP(size, 8); 814 815 ptr = s->pool_cur; 816 ptr_end = ptr + size; 817 if (unlikely(ptr_end > s->pool_end)) { 818 return tcg_malloc_internal(tcg_ctx, size); 819 } else { 820 s->pool_cur = ptr_end; 821 return ptr; 822 } 823 } 824 825 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); 826 void tcg_register_thread(void); 827 void tcg_prologue_init(TCGContext *s); 828 void tcg_func_start(TCGContext *s); 829 830 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); 831 832 void tb_target_set_jmp_target(const TranslationBlock *, int, 833 uintptr_t, uintptr_t); 834 835 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); 836 837 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, 838 intptr_t, const char *); 839 TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); 840 TCGv_vec tcg_temp_new_vec(TCGType type); 841 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); 842 843 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, 844 const char *name) 845 { 846 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); 847 return temp_tcgv_i32(t); 848 } 849 850 static inline TCGv_i32 tcg_temp_new_i32(void) 851 { 852 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); 853 return temp_tcgv_i32(t); 854 } 855 856 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, 857 const char *name) 858 { 859 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); 860 return temp_tcgv_i64(t); 861 } 862 863 static inline TCGv_i64 tcg_temp_new_i64(void) 864 { 865 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); 866 return temp_tcgv_i64(t); 867 } 868 869 static inline TCGv_i128 tcg_temp_new_i128(void) 870 { 871 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); 872 return temp_tcgv_i128(t); 873 } 874 875 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, 876 const char *name) 877 { 878 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); 879 return temp_tcgv_ptr(t); 880 } 881 882 static inline TCGv_ptr tcg_temp_new_ptr(void) 883 { 884 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); 885 return temp_tcgv_ptr(t); 886 } 887 888 int64_t tcg_cpu_exec_time(void); 889 void tcg_dump_info(GString *buf); 890 void tcg_dump_op_count(GString *buf); 891 892 #define TCG_CT_CONST 1 /* any constant of register size */ 893 894 typedef struct TCGArgConstraint { 895 unsigned ct : 16; 896 unsigned alias_index : 4; 897 unsigned sort_index : 4; 898 unsigned pair_index : 4; 899 unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ 900 bool oalias : 1; 901 bool ialias : 1; 902 bool newreg : 1; 903 TCGRegSet regs; 904 } TCGArgConstraint; 905 906 #define TCG_MAX_OP_ARGS 16 907 908 /* Bits for TCGOpDef->flags, 8 bits available, all used. */ 909 enum { 910 /* Instruction exits the translation block. */ 911 TCG_OPF_BB_EXIT = 0x01, 912 /* Instruction defines the end of a basic block. */ 913 TCG_OPF_BB_END = 0x02, 914 /* Instruction clobbers call registers and potentially update globals. */ 915 TCG_OPF_CALL_CLOBBER = 0x04, 916 /* Instruction has side effects: it cannot be removed if its outputs 917 are not used, and might trigger exceptions. */ 918 TCG_OPF_SIDE_EFFECTS = 0x08, 919 /* Instruction operands are 64-bits (otherwise 32-bits). */ 920 TCG_OPF_64BIT = 0x10, 921 /* Instruction is optional and not implemented by the host, or insn 922 is generic and should not be implemened by the host. */ 923 TCG_OPF_NOT_PRESENT = 0x20, 924 /* Instruction operands are vectors. */ 925 TCG_OPF_VECTOR = 0x40, 926 /* Instruction is a conditional branch. */ 927 TCG_OPF_COND_BRANCH = 0x80 928 }; 929 930 typedef struct TCGOpDef { 931 const char *name; 932 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; 933 uint8_t flags; 934 TCGArgConstraint *args_ct; 935 } TCGOpDef; 936 937 extern TCGOpDef tcg_op_defs[]; 938 extern const size_t tcg_op_defs_max; 939 940 typedef struct TCGTargetOpDef { 941 TCGOpcode op; 942 const char *args_ct_str[TCG_MAX_OP_ARGS]; 943 } TCGTargetOpDef; 944 945 bool tcg_op_supported(TCGOpcode op); 946 947 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); 948 949 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); 950 void tcg_op_remove(TCGContext *s, TCGOp *op); 951 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, 952 TCGOpcode opc, unsigned nargs); 953 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, 954 TCGOpcode opc, unsigned nargs); 955 956 /** 957 * tcg_remove_ops_after: 958 * @op: target operation 959 * 960 * Discard any opcodes emitted since @op. Expected usage is to save 961 * a starting point with tcg_last_op(), speculatively emit opcodes, 962 * then decide whether or not to keep those opcodes after the fact. 963 */ 964 void tcg_remove_ops_after(TCGOp *op); 965 966 void tcg_optimize(TCGContext *s); 967 968 /* 969 * Locate or create a read-only temporary that is a constant. 970 * This kind of temporary need not be freed, but for convenience 971 * will be silently ignored by tcg_temp_free_*. 972 */ 973 TCGTemp *tcg_constant_internal(TCGType type, int64_t val); 974 975 static inline TCGv_i32 tcg_constant_i32(int32_t val) 976 { 977 return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); 978 } 979 980 static inline TCGv_i64 tcg_constant_i64(int64_t val) 981 { 982 return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); 983 } 984 985 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); 986 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); 987 988 #if UINTPTR_MAX == UINT32_MAX 989 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) 990 #else 991 # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) 992 #endif 993 994 TCGLabel *gen_new_label(void); 995 996 /** 997 * label_arg 998 * @l: label 999 * 1000 * Encode a label for storage in the TCG opcode stream. 1001 */ 1002 1003 static inline TCGArg label_arg(TCGLabel *l) 1004 { 1005 return (uintptr_t)l; 1006 } 1007 1008 /** 1009 * arg_label 1010 * @i: value 1011 * 1012 * The opposite of label_arg. Retrieve a label from the 1013 * encoding of the TCG opcode stream. 1014 */ 1015 1016 static inline TCGLabel *arg_label(TCGArg i) 1017 { 1018 return (TCGLabel *)(uintptr_t)i; 1019 } 1020 1021 /** 1022 * tcg_ptr_byte_diff 1023 * @a, @b: addresses to be differenced 1024 * 1025 * There are many places within the TCG backends where we need a byte 1026 * difference between two pointers. While this can be accomplished 1027 * with local casting, it's easy to get wrong -- especially if one is 1028 * concerned with the signedness of the result. 1029 * 1030 * This version relies on GCC's void pointer arithmetic to get the 1031 * correct result. 1032 */ 1033 1034 static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) 1035 { 1036 return a - b; 1037 } 1038 1039 /** 1040 * tcg_pcrel_diff 1041 * @s: the tcg context 1042 * @target: address of the target 1043 * 1044 * Produce a pc-relative difference, from the current code_ptr 1045 * to the destination address. 1046 */ 1047 1048 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) 1049 { 1050 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); 1051 } 1052 1053 /** 1054 * tcg_tbrel_diff 1055 * @s: the tcg context 1056 * @target: address of the target 1057 * 1058 * Produce a difference, from the beginning of the current TB code 1059 * to the destination address. 1060 */ 1061 static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) 1062 { 1063 return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); 1064 } 1065 1066 /** 1067 * tcg_current_code_size 1068 * @s: the tcg context 1069 * 1070 * Compute the current code size within the translation block. 1071 * This is used to fill in qemu's data structures for goto_tb. 1072 */ 1073 1074 static inline size_t tcg_current_code_size(TCGContext *s) 1075 { 1076 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); 1077 } 1078 1079 /** 1080 * tcg_qemu_tb_exec: 1081 * @env: pointer to CPUArchState for the CPU 1082 * @tb_ptr: address of generated code for the TB to execute 1083 * 1084 * Start executing code from a given translation block. 1085 * Where translation blocks have been linked, execution 1086 * may proceed from the given TB into successive ones. 1087 * Control eventually returns only when some action is needed 1088 * from the top-level loop: either control must pass to a TB 1089 * which has not yet been directly linked, or an asynchronous 1090 * event such as an interrupt needs handling. 1091 * 1092 * Return: The return value is the value passed to the corresponding 1093 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. 1094 * The value is either zero or a 4-byte aligned pointer to that TB combined 1095 * with additional information in its two least significant bits. The 1096 * additional information is encoded as follows: 1097 * 0, 1: the link between this TB and the next is via the specified 1098 * TB index (0 or 1). That is, we left the TB via (the equivalent 1099 * of) "goto_tb <index>". The main loop uses this to determine 1100 * how to link the TB just executed to the next. 1101 * 2: we are using instruction counting code generation, and we 1102 * did not start executing this TB because the instruction counter 1103 * would hit zero midway through it. In this case the pointer 1104 * returned is the TB we were about to execute, and the caller must 1105 * arrange to execute the remaining count of instructions. 1106 * 3: we stopped because the CPU's exit_request flag was set 1107 * (usually meaning that there is an interrupt that needs to be 1108 * handled). The pointer returned is the TB we were about to execute 1109 * when we noticed the pending exit request. 1110 * 1111 * If the bottom two bits indicate an exit-via-index then the CPU 1112 * state is correctly synchronised and ready for execution of the next 1113 * TB (and in particular the guest PC is the address to execute next). 1114 * Otherwise, we gave up on execution of this TB before it started, and 1115 * the caller must fix up the CPU state by calling the CPU's 1116 * synchronize_from_tb() method with the TB pointer we return (falling 1117 * back to calling the CPU's set_pc method with tb->pb if no 1118 * synchronize_from_tb() method exists). 1119 * 1120 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec 1121 * to this default (which just calls the prologue.code emitted by 1122 * tcg_target_qemu_prologue()). 1123 */ 1124 #define TB_EXIT_MASK 3 1125 #define TB_EXIT_IDX0 0 1126 #define TB_EXIT_IDX1 1 1127 #define TB_EXIT_IDXMAX 1 1128 #define TB_EXIT_REQUESTED 3 1129 1130 #ifdef CONFIG_TCG_INTERPRETER 1131 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); 1132 #else 1133 typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); 1134 extern tcg_prologue_fn *tcg_qemu_tb_exec; 1135 #endif 1136 1137 void tcg_register_jit(const void *buf, size_t buf_size); 1138 1139 #if TCG_TARGET_MAYBE_vec 1140 /* Return zero if the tuple (opc, type, vece) is unsupportable; 1141 return > 0 if it is directly supportable; 1142 return < 0 if we must call tcg_expand_vec_op. */ 1143 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); 1144 #else 1145 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) 1146 { 1147 return 0; 1148 } 1149 #endif 1150 1151 /* Expand the tuple (opc, type, vece) on the given arguments. */ 1152 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); 1153 1154 /* Replicate a constant C accoring to the log2 of the element size. */ 1155 uint64_t dup_const(unsigned vece, uint64_t c); 1156 1157 #define dup_const(VECE, C) \ 1158 (__builtin_constant_p(VECE) \ 1159 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ 1160 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ 1161 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ 1162 : (VECE) == MO_64 ? (uint64_t)(C) \ 1163 : (qemu_build_not_reached_always(), 0)) \ 1164 : dup_const(VECE, C)) 1165 1166 #if TARGET_LONG_BITS == 64 1167 # define dup_const_tl dup_const 1168 #else 1169 # define dup_const_tl(VECE, C) \ 1170 (__builtin_constant_p(VECE) \ 1171 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 1172 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 1173 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 1174 : (qemu_build_not_reached_always(), 0)) \ 1175 : (target_long)dup_const(VECE, C)) 1176 #endif 1177 1178 #ifdef CONFIG_DEBUG_TCG 1179 void tcg_assert_listed_vecop(TCGOpcode); 1180 #else 1181 static inline void tcg_assert_listed_vecop(TCGOpcode op) { } 1182 #endif 1183 1184 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) 1185 { 1186 #ifdef CONFIG_DEBUG_TCG 1187 const TCGOpcode *o = tcg_ctx->vecop_list; 1188 tcg_ctx->vecop_list = n; 1189 return o; 1190 #else 1191 return NULL; 1192 #endif 1193 } 1194 1195 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); 1196 1197 #endif /* TCG_H */ 1198