1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29 /* predefined ops */ 30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) 31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 32 33 /* variable number of parameters */ 34 DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) 35 36 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 37 DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT) 38 39 DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 40 41 DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT) 42 43 DEF(add, 1, 2, 0, TCG_OPF_INT) 44 DEF(and, 1, 2, 0, TCG_OPF_INT) 45 DEF(andc, 1, 2, 0, TCG_OPF_INT) 46 DEF(clz, 1, 2, 0, TCG_OPF_INT) 47 DEF(ctpop, 1, 1, 0, TCG_OPF_INT) 48 DEF(ctz, 1, 2, 0, TCG_OPF_INT) 49 DEF(divs, 1, 2, 0, TCG_OPF_INT) 50 DEF(divs2, 2, 3, 0, TCG_OPF_INT) 51 DEF(divu, 1, 2, 0, TCG_OPF_INT) 52 DEF(divu2, 2, 3, 0, TCG_OPF_INT) 53 DEF(eqv, 1, 2, 0, TCG_OPF_INT) 54 DEF(mul, 1, 2, 0, TCG_OPF_INT) 55 DEF(muls2, 2, 2, 0, TCG_OPF_INT) 56 DEF(mulsh, 1, 2, 0, TCG_OPF_INT) 57 DEF(mulu2, 2, 2, 0, TCG_OPF_INT) 58 DEF(muluh, 1, 2, 0, TCG_OPF_INT) 59 DEF(nand, 1, 2, 0, TCG_OPF_INT) 60 DEF(neg, 1, 1, 0, TCG_OPF_INT) 61 DEF(negsetcond, 1, 2, 1, TCG_OPF_INT) 62 DEF(nor, 1, 2, 0, TCG_OPF_INT) 63 DEF(not, 1, 1, 0, TCG_OPF_INT) 64 DEF(or, 1, 2, 0, TCG_OPF_INT) 65 DEF(orc, 1, 2, 0, TCG_OPF_INT) 66 DEF(rems, 1, 2, 0, TCG_OPF_INT) 67 DEF(remu, 1, 2, 0, TCG_OPF_INT) 68 DEF(rotl, 1, 2, 0, TCG_OPF_INT) 69 DEF(rotr, 1, 2, 0, TCG_OPF_INT) 70 DEF(sar, 1, 2, 0, TCG_OPF_INT) 71 DEF(setcond, 1, 2, 1, TCG_OPF_INT) 72 DEF(shl, 1, 2, 0, TCG_OPF_INT) 73 DEF(shr, 1, 2, 0, TCG_OPF_INT) 74 DEF(sub, 1, 2, 0, TCG_OPF_INT) 75 DEF(xor, 1, 2, 0, TCG_OPF_INT) 76 77 DEF(movcond_i32, 1, 4, 1, 0) 78 /* load/store */ 79 DEF(ld8u_i32, 1, 1, 1, 0) 80 DEF(ld8s_i32, 1, 1, 1, 0) 81 DEF(ld16u_i32, 1, 1, 1, 0) 82 DEF(ld16s_i32, 1, 1, 1, 0) 83 DEF(ld_i32, 1, 1, 1, 0) 84 DEF(st8_i32, 0, 2, 1, 0) 85 DEF(st16_i32, 0, 2, 1, 0) 86 DEF(st_i32, 0, 2, 1, 0) 87 /* shifts/rotates */ 88 DEF(deposit_i32, 1, 2, 2, 0) 89 DEF(extract_i32, 1, 1, 2, 0) 90 DEF(sextract_i32, 1, 1, 2, 0) 91 DEF(extract2_i32, 1, 2, 1, 0) 92 93 DEF(add2_i32, 2, 4, 0, 0) 94 DEF(sub2_i32, 2, 4, 0, 0) 95 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) 96 DEF(setcond2_i32, 1, 4, 1, 0) 97 98 DEF(bswap16_i32, 1, 1, 1, 0) 99 DEF(bswap32_i32, 1, 1, 1, 0) 100 101 DEF(movcond_i64, 1, 4, 1, 0) 102 /* load/store */ 103 DEF(ld8u_i64, 1, 1, 1, 0) 104 DEF(ld8s_i64, 1, 1, 1, 0) 105 DEF(ld16u_i64, 1, 1, 1, 0) 106 DEF(ld16s_i64, 1, 1, 1, 0) 107 DEF(ld32u_i64, 1, 1, 1, 0) 108 DEF(ld32s_i64, 1, 1, 1, 0) 109 DEF(ld_i64, 1, 1, 1, 0) 110 DEF(st8_i64, 0, 2, 1, 0) 111 DEF(st16_i64, 0, 2, 1, 0) 112 DEF(st32_i64, 0, 2, 1, 0) 113 DEF(st_i64, 0, 2, 1, 0) 114 /* shifts/rotates */ 115 DEF(deposit_i64, 1, 2, 2, 0) 116 DEF(extract_i64, 1, 1, 2, 0) 117 DEF(sextract_i64, 1, 1, 2, 0) 118 DEF(extract2_i64, 1, 2, 1, 0) 119 120 /* size changing ops */ 121 DEF(ext_i32_i64, 1, 1, 0, 0) 122 DEF(extu_i32_i64, 1, 1, 0, 0) 123 DEF(extrl_i64_i32, 1, 1, 0, 0) 124 DEF(extrh_i64_i32, 1, 1, 0, 0) 125 126 DEF(bswap16_i64, 1, 1, 1, 0) 127 DEF(bswap32_i64, 1, 1, 1, 0) 128 DEF(bswap64_i64, 1, 1, 1, 0) 129 130 DEF(add2_i64, 2, 4, 0, 0) 131 DEF(sub2_i64, 2, 4, 0, 0) 132 133 #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) 134 135 /* There are tcg_ctx->insn_start_words here, not just one. */ 136 DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) 137 138 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 139 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 140 DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) 141 142 DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 143 DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) 144 145 DEF(qemu_ld_i32, 1, 1, 1, 146 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 147 DEF(qemu_st_i32, 0, 1 + 1, 1, 148 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 149 DEF(qemu_ld_i64, DATA64_ARGS, 1, 1, 150 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 151 DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1, 152 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 153 154 /* Only used by i386 to cope with stupid register constraints. */ 155 DEF(qemu_st8_i32, 0, 1 + 1, 1, 156 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 157 158 /* Only for 64-bit hosts at the moment. */ 159 DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 160 DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 161 162 /* Host vector support. */ 163 164 DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) 165 166 DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR) 167 DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR) 168 169 DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR) 170 DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR) 171 DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR) 172 173 DEF(add_vec, 1, 2, 0, TCG_OPF_VECTOR) 174 DEF(sub_vec, 1, 2, 0, TCG_OPF_VECTOR) 175 DEF(mul_vec, 1, 2, 0, TCG_OPF_VECTOR) 176 DEF(neg_vec, 1, 1, 0, TCG_OPF_VECTOR) 177 DEF(abs_vec, 1, 1, 0, TCG_OPF_VECTOR) 178 DEF(ssadd_vec, 1, 2, 0, TCG_OPF_VECTOR) 179 DEF(usadd_vec, 1, 2, 0, TCG_OPF_VECTOR) 180 DEF(sssub_vec, 1, 2, 0, TCG_OPF_VECTOR) 181 DEF(ussub_vec, 1, 2, 0, TCG_OPF_VECTOR) 182 DEF(smin_vec, 1, 2, 0, TCG_OPF_VECTOR) 183 DEF(umin_vec, 1, 2, 0, TCG_OPF_VECTOR) 184 DEF(smax_vec, 1, 2, 0, TCG_OPF_VECTOR) 185 DEF(umax_vec, 1, 2, 0, TCG_OPF_VECTOR) 186 187 DEF(and_vec, 1, 2, 0, TCG_OPF_VECTOR) 188 DEF(or_vec, 1, 2, 0, TCG_OPF_VECTOR) 189 DEF(xor_vec, 1, 2, 0, TCG_OPF_VECTOR) 190 DEF(andc_vec, 1, 2, 0, TCG_OPF_VECTOR) 191 DEF(orc_vec, 1, 2, 0, TCG_OPF_VECTOR) 192 DEF(nand_vec, 1, 2, 0, TCG_OPF_VECTOR) 193 DEF(nor_vec, 1, 2, 0, TCG_OPF_VECTOR) 194 DEF(eqv_vec, 1, 2, 0, TCG_OPF_VECTOR) 195 DEF(not_vec, 1, 1, 0, TCG_OPF_VECTOR) 196 197 DEF(shli_vec, 1, 1, 1, TCG_OPF_VECTOR) 198 DEF(shri_vec, 1, 1, 1, TCG_OPF_VECTOR) 199 DEF(sari_vec, 1, 1, 1, TCG_OPF_VECTOR) 200 DEF(rotli_vec, 1, 1, 1, TCG_OPF_VECTOR) 201 202 DEF(shls_vec, 1, 2, 0, TCG_OPF_VECTOR) 203 DEF(shrs_vec, 1, 2, 0, TCG_OPF_VECTOR) 204 DEF(sars_vec, 1, 2, 0, TCG_OPF_VECTOR) 205 DEF(rotls_vec, 1, 2, 0, TCG_OPF_VECTOR) 206 207 DEF(shlv_vec, 1, 2, 0, TCG_OPF_VECTOR) 208 DEF(shrv_vec, 1, 2, 0, TCG_OPF_VECTOR) 209 DEF(sarv_vec, 1, 2, 0, TCG_OPF_VECTOR) 210 DEF(rotlv_vec, 1, 2, 0, TCG_OPF_VECTOR) 211 DEF(rotrv_vec, 1, 2, 0, TCG_OPF_VECTOR) 212 213 DEF(cmp_vec, 1, 2, 1, TCG_OPF_VECTOR) 214 215 DEF(bitsel_vec, 1, 3, 0, TCG_OPF_VECTOR) 216 DEF(cmpsel_vec, 1, 4, 1, TCG_OPF_VECTOR) 217 218 DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) 219 220 #include "tcg-target-opc.h.inc" 221 222 #undef DATA64_ARGS 223 #undef DEF 224