1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29 /* predefined ops */ 30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) 31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 32 33 /* variable number of parameters */ 34 DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) 35 36 DEF(br, 0, 0, 1, TCG_OPF_BB_END) 37 38 #define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0) 39 #if TCG_TARGET_REG_BITS == 32 40 # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT 41 #else 42 # define IMPL64 TCG_OPF_64BIT 43 #endif 44 45 DEF(mb, 0, 0, 1, 0) 46 47 DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) 48 DEF(setcond_i32, 1, 2, 1, 0) 49 DEF(negsetcond_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_negsetcond_i32)) 50 DEF(movcond_i32, 1, 4, 1, 0) 51 /* load/store */ 52 DEF(ld8u_i32, 1, 1, 1, 0) 53 DEF(ld8s_i32, 1, 1, 1, 0) 54 DEF(ld16u_i32, 1, 1, 1, 0) 55 DEF(ld16s_i32, 1, 1, 1, 0) 56 DEF(ld_i32, 1, 1, 1, 0) 57 DEF(st8_i32, 0, 2, 1, 0) 58 DEF(st16_i32, 0, 2, 1, 0) 59 DEF(st_i32, 0, 2, 1, 0) 60 /* arith */ 61 DEF(add_i32, 1, 2, 0, 0) 62 DEF(sub_i32, 1, 2, 0, 0) 63 DEF(mul_i32, 1, 2, 0, 0) 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 68 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) 69 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) 70 DEF(and_i32, 1, 2, 0, 0) 71 DEF(or_i32, 1, 2, 0, 0) 72 DEF(xor_i32, 1, 2, 0, 0) 73 /* shifts/rotates */ 74 DEF(shl_i32, 1, 2, 0, 0) 75 DEF(shr_i32, 1, 2, 0, 0) 76 DEF(sar_i32, 1, 2, 0, 0) 77 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 78 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 79 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) 80 DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32)) 81 DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32)) 82 DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32)) 83 84 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) 85 86 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32)) 87 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32)) 88 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32)) 89 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32)) 90 DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32)) 91 DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32)) 92 DEF(brcond2_i32, 0, 4, 2, 93 TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32)) 94 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) 95 96 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32)) 97 DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32)) 98 DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32)) 99 DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32)) 100 DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32)) 101 DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32)) 102 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 103 DEF(neg_i32, 1, 1, 0, 0) 104 DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32)) 105 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 106 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 107 DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32)) 108 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) 109 DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32)) 110 DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) 111 DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) 112 113 DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) 114 DEF(setcond_i64, 1, 2, 1, IMPL64) 115 DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond_i64)) 116 DEF(movcond_i64, 1, 4, 1, IMPL64) 117 /* load/store */ 118 DEF(ld8u_i64, 1, 1, 1, IMPL64) 119 DEF(ld8s_i64, 1, 1, 1, IMPL64) 120 DEF(ld16u_i64, 1, 1, 1, IMPL64) 121 DEF(ld16s_i64, 1, 1, 1, IMPL64) 122 DEF(ld32u_i64, 1, 1, 1, IMPL64) 123 DEF(ld32s_i64, 1, 1, 1, IMPL64) 124 DEF(ld_i64, 1, 1, 1, IMPL64) 125 DEF(st8_i64, 0, 2, 1, IMPL64) 126 DEF(st16_i64, 0, 2, 1, IMPL64) 127 DEF(st32_i64, 0, 2, 1, IMPL64) 128 DEF(st_i64, 0, 2, 1, IMPL64) 129 /* arith */ 130 DEF(add_i64, 1, 2, 0, IMPL64) 131 DEF(sub_i64, 1, 2, 0, IMPL64) 132 DEF(mul_i64, 1, 2, 0, IMPL64) 133 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) 134 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) 135 DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) 136 DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) 137 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) 138 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) 139 DEF(and_i64, 1, 2, 0, IMPL64) 140 DEF(or_i64, 1, 2, 0, IMPL64) 141 DEF(xor_i64, 1, 2, 0, IMPL64) 142 /* shifts/rotates */ 143 DEF(shl_i64, 1, 2, 0, IMPL64) 144 DEF(shr_i64, 1, 2, 0, IMPL64) 145 DEF(sar_i64, 1, 2, 0, IMPL64) 146 DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) 147 DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) 148 DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) 149 DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64)) 150 DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64)) 151 DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64)) 152 153 /* size changing ops */ 154 DEF(ext_i32_i64, 1, 1, 0, IMPL64) 155 DEF(extu_i32_i64, 1, 1, 0, IMPL64) 156 DEF(extrl_i64_i32, 1, 1, 0, 157 IMPL(TCG_TARGET_HAS_extr_i64_i32) 158 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) 159 DEF(extrh_i64_i32, 1, 1, 0, 160 IMPL(TCG_TARGET_HAS_extr_i64_i32) 161 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) 162 163 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64) 164 DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) 165 DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) 166 DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64)) 167 DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64)) 168 DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64)) 169 DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64)) 170 DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64)) 171 DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64)) 172 DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64)) 173 DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64)) 174 DEF(neg_i64, 1, 1, 0, IMPL64) 175 DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64)) 176 DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) 177 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) 178 DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64)) 179 DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64)) 180 DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64)) 181 DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64)) 182 DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64)) 183 184 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) 185 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) 186 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64)) 187 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64)) 188 DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64)) 189 DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) 190 191 #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) 192 193 /* There are tcg_ctx->insn_start_words here, not just one. */ 194 DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) 195 196 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) 197 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) 198 DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) 199 200 DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 201 DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) 202 203 /* Replicate ld/st ops for 32 and 64-bit guest addresses. */ 204 DEF(qemu_ld_a32_i32, 1, 1, 1, 205 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 206 DEF(qemu_st_a32_i32, 0, 1 + 1, 1, 207 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 208 DEF(qemu_ld_a32_i64, DATA64_ARGS, 1, 1, 209 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) 210 DEF(qemu_st_a32_i64, 0, DATA64_ARGS + 1, 1, 211 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) 212 213 DEF(qemu_ld_a64_i32, 1, DATA64_ARGS, 1, 214 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 215 DEF(qemu_st_a64_i32, 0, 1 + DATA64_ARGS, 1, 216 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 217 DEF(qemu_ld_a64_i64, DATA64_ARGS, DATA64_ARGS, 1, 218 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) 219 DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1, 220 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) 221 222 /* Only used by i386 to cope with stupid register constraints. */ 223 DEF(qemu_st8_a32_i32, 0, 1 + 1, 1, 224 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | 225 IMPL(TCG_TARGET_HAS_qemu_st8_i32)) 226 DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1, 227 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | 228 IMPL(TCG_TARGET_HAS_qemu_st8_i32)) 229 230 /* Only for 64-bit hosts at the moment. */ 231 DEF(qemu_ld_a32_i128, 2, 1, 1, 232 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | 233 IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) 234 DEF(qemu_ld_a64_i128, 2, 1, 1, 235 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | 236 IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) 237 DEF(qemu_st_a32_i128, 0, 3, 1, 238 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | 239 IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) 240 DEF(qemu_st_a64_i128, 0, 3, 1, 241 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | 242 IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) 243 244 /* Host vector support. */ 245 246 #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) 247 248 DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) 249 250 DEF(dup_vec, 1, 1, 0, IMPLVEC) 251 DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) 252 253 DEF(ld_vec, 1, 1, 1, IMPLVEC) 254 DEF(st_vec, 0, 2, 1, IMPLVEC) 255 DEF(dupm_vec, 1, 1, 1, IMPLVEC) 256 257 DEF(add_vec, 1, 2, 0, IMPLVEC) 258 DEF(sub_vec, 1, 2, 0, IMPLVEC) 259 DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) 260 DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) 261 DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec)) 262 DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) 263 DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) 264 DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) 265 DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) 266 DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) 267 DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) 268 DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) 269 DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) 270 271 DEF(and_vec, 1, 2, 0, IMPLVEC) 272 DEF(or_vec, 1, 2, 0, IMPLVEC) 273 DEF(xor_vec, 1, 2, 0, IMPLVEC) 274 DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec)) 275 DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec)) 276 DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec)) 277 DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec)) 278 DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec)) 279 DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec)) 280 281 DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) 282 DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) 283 DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) 284 DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) 285 286 DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) 287 DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) 288 DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) 289 DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec)) 290 291 DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) 292 DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) 293 DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) 294 DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) 295 DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) 296 297 DEF(cmp_vec, 1, 2, 1, IMPLVEC) 298 299 DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) 300 DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) 301 302 DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) 303 304 #if TCG_TARGET_MAYBE_vec 305 #include "tcg-target.opc.h" 306 #endif 307 308 #ifdef TCG_TARGET_INTERPRETER 309 /* These opcodes are only for use between the tci generator and interpreter. */ 310 DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) 311 DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) 312 #endif 313 314 #undef DATA64_ARGS 315 #undef IMPL 316 #undef IMPL64 317 #undef IMPLVEC 318 #undef DEF 319