1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29 /* predefined ops */ 30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) 31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 32 33 /* variable number of parameters */ 34 DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) 35 36 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 37 38 DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 39 40 DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT) 41 42 DEF(add, 1, 2, 0, TCG_OPF_INT) 43 DEF(and, 1, 2, 0, TCG_OPF_INT) 44 DEF(andc, 1, 2, 0, TCG_OPF_INT) 45 DEF(divs, 1, 2, 0, TCG_OPF_INT) 46 DEF(divs2, 2, 3, 0, TCG_OPF_INT) 47 DEF(divu, 1, 2, 0, TCG_OPF_INT) 48 DEF(divu2, 2, 3, 0, TCG_OPF_INT) 49 DEF(eqv, 1, 2, 0, TCG_OPF_INT) 50 DEF(mul, 1, 2, 0, TCG_OPF_INT) 51 DEF(mulsh, 1, 2, 0, TCG_OPF_INT) 52 DEF(muluh, 1, 2, 0, TCG_OPF_INT) 53 DEF(nand, 1, 2, 0, TCG_OPF_INT) 54 DEF(neg, 1, 1, 0, TCG_OPF_INT) 55 DEF(nor, 1, 2, 0, TCG_OPF_INT) 56 DEF(not, 1, 1, 0, TCG_OPF_INT) 57 DEF(or, 1, 2, 0, TCG_OPF_INT) 58 DEF(orc, 1, 2, 0, TCG_OPF_INT) 59 DEF(rems, 1, 2, 0, TCG_OPF_INT) 60 DEF(sub, 1, 2, 0, TCG_OPF_INT) 61 DEF(xor, 1, 2, 0, TCG_OPF_INT) 62 63 DEF(setcond_i32, 1, 2, 1, 0) 64 DEF(negsetcond_i32, 1, 2, 1, 0) 65 DEF(movcond_i32, 1, 4, 1, 0) 66 /* load/store */ 67 DEF(ld8u_i32, 1, 1, 1, 0) 68 DEF(ld8s_i32, 1, 1, 1, 0) 69 DEF(ld16u_i32, 1, 1, 1, 0) 70 DEF(ld16s_i32, 1, 1, 1, 0) 71 DEF(ld_i32, 1, 1, 1, 0) 72 DEF(st8_i32, 0, 2, 1, 0) 73 DEF(st16_i32, 0, 2, 1, 0) 74 DEF(st_i32, 0, 2, 1, 0) 75 /* arith */ 76 DEF(remu_i32, 1, 2, 0, 0) 77 /* shifts/rotates */ 78 DEF(shl_i32, 1, 2, 0, 0) 79 DEF(shr_i32, 1, 2, 0, 0) 80 DEF(sar_i32, 1, 2, 0, 0) 81 DEF(rotl_i32, 1, 2, 0, 0) 82 DEF(rotr_i32, 1, 2, 0, 0) 83 DEF(deposit_i32, 1, 2, 2, 0) 84 DEF(extract_i32, 1, 1, 2, 0) 85 DEF(sextract_i32, 1, 1, 2, 0) 86 DEF(extract2_i32, 1, 2, 1, 0) 87 88 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) 89 90 DEF(add2_i32, 2, 4, 0, 0) 91 DEF(sub2_i32, 2, 4, 0, 0) 92 DEF(mulu2_i32, 2, 2, 0, 0) 93 DEF(muls2_i32, 2, 2, 0, 0) 94 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) 95 DEF(setcond2_i32, 1, 4, 1, 0) 96 97 DEF(bswap16_i32, 1, 1, 1, 0) 98 DEF(bswap32_i32, 1, 1, 1, 0) 99 DEF(clz_i32, 1, 2, 0, 0) 100 DEF(ctz_i32, 1, 2, 0, 0) 101 DEF(ctpop_i32, 1, 1, 0, 0) 102 103 DEF(setcond_i64, 1, 2, 1, 0) 104 DEF(negsetcond_i64, 1, 2, 1, 0) 105 DEF(movcond_i64, 1, 4, 1, 0) 106 /* load/store */ 107 DEF(ld8u_i64, 1, 1, 1, 0) 108 DEF(ld8s_i64, 1, 1, 1, 0) 109 DEF(ld16u_i64, 1, 1, 1, 0) 110 DEF(ld16s_i64, 1, 1, 1, 0) 111 DEF(ld32u_i64, 1, 1, 1, 0) 112 DEF(ld32s_i64, 1, 1, 1, 0) 113 DEF(ld_i64, 1, 1, 1, 0) 114 DEF(st8_i64, 0, 2, 1, 0) 115 DEF(st16_i64, 0, 2, 1, 0) 116 DEF(st32_i64, 0, 2, 1, 0) 117 DEF(st_i64, 0, 2, 1, 0) 118 /* arith */ 119 DEF(remu_i64, 1, 2, 0, 0) 120 /* shifts/rotates */ 121 DEF(shl_i64, 1, 2, 0, 0) 122 DEF(shr_i64, 1, 2, 0, 0) 123 DEF(sar_i64, 1, 2, 0, 0) 124 DEF(rotl_i64, 1, 2, 0, 0) 125 DEF(rotr_i64, 1, 2, 0, 0) 126 DEF(deposit_i64, 1, 2, 2, 0) 127 DEF(extract_i64, 1, 1, 2, 0) 128 DEF(sextract_i64, 1, 1, 2, 0) 129 DEF(extract2_i64, 1, 2, 1, 0) 130 131 /* size changing ops */ 132 DEF(ext_i32_i64, 1, 1, 0, 0) 133 DEF(extu_i32_i64, 1, 1, 0, 0) 134 DEF(extrl_i64_i32, 1, 1, 0, 0) 135 DEF(extrh_i64_i32, 1, 1, 0, 0) 136 137 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) 138 DEF(bswap16_i64, 1, 1, 1, 0) 139 DEF(bswap32_i64, 1, 1, 1, 0) 140 DEF(bswap64_i64, 1, 1, 1, 0) 141 DEF(clz_i64, 1, 2, 0, 0) 142 DEF(ctz_i64, 1, 2, 0, 0) 143 DEF(ctpop_i64, 1, 1, 0, 0) 144 145 DEF(add2_i64, 2, 4, 0, 0) 146 DEF(sub2_i64, 2, 4, 0, 0) 147 DEF(mulu2_i64, 2, 2, 0, 0) 148 DEF(muls2_i64, 2, 2, 0, 0) 149 150 #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) 151 152 /* There are tcg_ctx->insn_start_words here, not just one. */ 153 DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) 154 155 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 156 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 157 DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) 158 159 DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 160 DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) 161 162 DEF(qemu_ld_i32, 1, 1, 1, 163 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 164 DEF(qemu_st_i32, 0, 1 + 1, 1, 165 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 166 DEF(qemu_ld_i64, DATA64_ARGS, 1, 1, 167 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 168 DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1, 169 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 170 171 /* Only used by i386 to cope with stupid register constraints. */ 172 DEF(qemu_st8_i32, 0, 1 + 1, 1, 173 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 174 175 /* Only for 64-bit hosts at the moment. */ 176 DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 177 DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 178 179 /* Host vector support. */ 180 181 DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) 182 183 DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR) 184 DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR) 185 186 DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR) 187 DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR) 188 DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR) 189 190 DEF(add_vec, 1, 2, 0, TCG_OPF_VECTOR) 191 DEF(sub_vec, 1, 2, 0, TCG_OPF_VECTOR) 192 DEF(mul_vec, 1, 2, 0, TCG_OPF_VECTOR) 193 DEF(neg_vec, 1, 1, 0, TCG_OPF_VECTOR) 194 DEF(abs_vec, 1, 1, 0, TCG_OPF_VECTOR) 195 DEF(ssadd_vec, 1, 2, 0, TCG_OPF_VECTOR) 196 DEF(usadd_vec, 1, 2, 0, TCG_OPF_VECTOR) 197 DEF(sssub_vec, 1, 2, 0, TCG_OPF_VECTOR) 198 DEF(ussub_vec, 1, 2, 0, TCG_OPF_VECTOR) 199 DEF(smin_vec, 1, 2, 0, TCG_OPF_VECTOR) 200 DEF(umin_vec, 1, 2, 0, TCG_OPF_VECTOR) 201 DEF(smax_vec, 1, 2, 0, TCG_OPF_VECTOR) 202 DEF(umax_vec, 1, 2, 0, TCG_OPF_VECTOR) 203 204 DEF(and_vec, 1, 2, 0, TCG_OPF_VECTOR) 205 DEF(or_vec, 1, 2, 0, TCG_OPF_VECTOR) 206 DEF(xor_vec, 1, 2, 0, TCG_OPF_VECTOR) 207 DEF(andc_vec, 1, 2, 0, TCG_OPF_VECTOR) 208 DEF(orc_vec, 1, 2, 0, TCG_OPF_VECTOR) 209 DEF(nand_vec, 1, 2, 0, TCG_OPF_VECTOR) 210 DEF(nor_vec, 1, 2, 0, TCG_OPF_VECTOR) 211 DEF(eqv_vec, 1, 2, 0, TCG_OPF_VECTOR) 212 DEF(not_vec, 1, 1, 0, TCG_OPF_VECTOR) 213 214 DEF(shli_vec, 1, 1, 1, TCG_OPF_VECTOR) 215 DEF(shri_vec, 1, 1, 1, TCG_OPF_VECTOR) 216 DEF(sari_vec, 1, 1, 1, TCG_OPF_VECTOR) 217 DEF(rotli_vec, 1, 1, 1, TCG_OPF_VECTOR) 218 219 DEF(shls_vec, 1, 2, 0, TCG_OPF_VECTOR) 220 DEF(shrs_vec, 1, 2, 0, TCG_OPF_VECTOR) 221 DEF(sars_vec, 1, 2, 0, TCG_OPF_VECTOR) 222 DEF(rotls_vec, 1, 2, 0, TCG_OPF_VECTOR) 223 224 DEF(shlv_vec, 1, 2, 0, TCG_OPF_VECTOR) 225 DEF(shrv_vec, 1, 2, 0, TCG_OPF_VECTOR) 226 DEF(sarv_vec, 1, 2, 0, TCG_OPF_VECTOR) 227 DEF(rotlv_vec, 1, 2, 0, TCG_OPF_VECTOR) 228 DEF(rotrv_vec, 1, 2, 0, TCG_OPF_VECTOR) 229 230 DEF(cmp_vec, 1, 2, 1, TCG_OPF_VECTOR) 231 232 DEF(bitsel_vec, 1, 3, 0, TCG_OPF_VECTOR) 233 DEF(cmpsel_vec, 1, 4, 1, TCG_OPF_VECTOR) 234 235 DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) 236 237 #include "tcg-target-opc.h.inc" 238 239 #undef DATA64_ARGS 240 #undef DEF 241