1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29 /* predefined ops */ 30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) 31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 32 33 /* variable number of parameters */ 34 DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) 35 36 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 37 DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT) 38 39 DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 40 41 DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT) 42 43 DEF(add, 1, 2, 0, TCG_OPF_INT) 44 DEF(and, 1, 2, 0, TCG_OPF_INT) 45 DEF(andc, 1, 2, 0, TCG_OPF_INT) 46 DEF(bswap16, 1, 1, 1, TCG_OPF_INT) 47 DEF(bswap32, 1, 1, 1, TCG_OPF_INT) 48 DEF(bswap64, 1, 1, 1, TCG_OPF_INT) 49 DEF(clz, 1, 2, 0, TCG_OPF_INT) 50 DEF(ctpop, 1, 1, 0, TCG_OPF_INT) 51 DEF(ctz, 1, 2, 0, TCG_OPF_INT) 52 DEF(deposit, 1, 2, 2, TCG_OPF_INT) 53 DEF(divs, 1, 2, 0, TCG_OPF_INT) 54 DEF(divs2, 2, 3, 0, TCG_OPF_INT) 55 DEF(divu, 1, 2, 0, TCG_OPF_INT) 56 DEF(divu2, 2, 3, 0, TCG_OPF_INT) 57 DEF(eqv, 1, 2, 0, TCG_OPF_INT) 58 DEF(extract, 1, 1, 2, TCG_OPF_INT) 59 DEF(extract2, 1, 2, 1, TCG_OPF_INT) 60 DEF(movcond, 1, 4, 1, TCG_OPF_INT) 61 DEF(mul, 1, 2, 0, TCG_OPF_INT) 62 DEF(muls2, 2, 2, 0, TCG_OPF_INT) 63 DEF(mulsh, 1, 2, 0, TCG_OPF_INT) 64 DEF(mulu2, 2, 2, 0, TCG_OPF_INT) 65 DEF(muluh, 1, 2, 0, TCG_OPF_INT) 66 DEF(nand, 1, 2, 0, TCG_OPF_INT) 67 DEF(neg, 1, 1, 0, TCG_OPF_INT) 68 DEF(negsetcond, 1, 2, 1, TCG_OPF_INT) 69 DEF(nor, 1, 2, 0, TCG_OPF_INT) 70 DEF(not, 1, 1, 0, TCG_OPF_INT) 71 DEF(or, 1, 2, 0, TCG_OPF_INT) 72 DEF(orc, 1, 2, 0, TCG_OPF_INT) 73 DEF(rems, 1, 2, 0, TCG_OPF_INT) 74 DEF(remu, 1, 2, 0, TCG_OPF_INT) 75 DEF(rotl, 1, 2, 0, TCG_OPF_INT) 76 DEF(rotr, 1, 2, 0, TCG_OPF_INT) 77 DEF(sar, 1, 2, 0, TCG_OPF_INT) 78 DEF(setcond, 1, 2, 1, TCG_OPF_INT) 79 DEF(sextract, 1, 1, 2, TCG_OPF_INT) 80 DEF(shl, 1, 2, 0, TCG_OPF_INT) 81 DEF(shr, 1, 2, 0, TCG_OPF_INT) 82 DEF(sub, 1, 2, 0, TCG_OPF_INT) 83 DEF(xor, 1, 2, 0, TCG_OPF_INT) 84 85 /* load/store */ 86 DEF(ld8u_i32, 1, 1, 1, 0) 87 DEF(ld8s_i32, 1, 1, 1, 0) 88 DEF(ld16u_i32, 1, 1, 1, 0) 89 DEF(ld16s_i32, 1, 1, 1, 0) 90 DEF(ld_i32, 1, 1, 1, 0) 91 DEF(st8_i32, 0, 2, 1, 0) 92 DEF(st16_i32, 0, 2, 1, 0) 93 DEF(st_i32, 0, 2, 1, 0) 94 95 DEF(add2_i32, 2, 4, 0, 0) 96 DEF(sub2_i32, 2, 4, 0, 0) 97 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) 98 DEF(setcond2_i32, 1, 4, 1, 0) 99 100 /* load/store */ 101 DEF(ld8u_i64, 1, 1, 1, 0) 102 DEF(ld8s_i64, 1, 1, 1, 0) 103 DEF(ld16u_i64, 1, 1, 1, 0) 104 DEF(ld16s_i64, 1, 1, 1, 0) 105 DEF(ld32u_i64, 1, 1, 1, 0) 106 DEF(ld32s_i64, 1, 1, 1, 0) 107 DEF(ld_i64, 1, 1, 1, 0) 108 DEF(st8_i64, 0, 2, 1, 0) 109 DEF(st16_i64, 0, 2, 1, 0) 110 DEF(st32_i64, 0, 2, 1, 0) 111 DEF(st_i64, 0, 2, 1, 0) 112 113 /* size changing ops */ 114 DEF(ext_i32_i64, 1, 1, 0, 0) 115 DEF(extu_i32_i64, 1, 1, 0, 0) 116 DEF(extrl_i64_i32, 1, 1, 0, 0) 117 DEF(extrh_i64_i32, 1, 1, 0, 0) 118 119 DEF(add2_i64, 2, 4, 0, 0) 120 DEF(sub2_i64, 2, 4, 0, 0) 121 122 #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) 123 124 /* There are tcg_ctx->insn_start_words here, not just one. */ 125 DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) 126 127 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 128 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 129 DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) 130 131 DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT) 132 DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT) 133 134 DEF(qemu_ld_i32, 1, 1, 1, 135 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 136 DEF(qemu_st_i32, 0, 1 + 1, 1, 137 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 138 DEF(qemu_ld_i64, DATA64_ARGS, 1, 1, 139 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 140 DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1, 141 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 142 143 /* Only used by i386 to cope with stupid register constraints. */ 144 DEF(qemu_st8_i32, 0, 1 + 1, 1, 145 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 146 147 /* Only for 64-bit hosts at the moment. */ 148 DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 149 DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 150 151 /* Host vector support. */ 152 153 DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) 154 155 DEF(dup_vec, 1, 1, 0, TCG_OPF_VECTOR) 156 DEF(dup2_vec, 1, 2, 0, TCG_OPF_VECTOR) 157 158 DEF(ld_vec, 1, 1, 1, TCG_OPF_VECTOR) 159 DEF(st_vec, 0, 2, 1, TCG_OPF_VECTOR) 160 DEF(dupm_vec, 1, 1, 1, TCG_OPF_VECTOR) 161 162 DEF(add_vec, 1, 2, 0, TCG_OPF_VECTOR) 163 DEF(sub_vec, 1, 2, 0, TCG_OPF_VECTOR) 164 DEF(mul_vec, 1, 2, 0, TCG_OPF_VECTOR) 165 DEF(neg_vec, 1, 1, 0, TCG_OPF_VECTOR) 166 DEF(abs_vec, 1, 1, 0, TCG_OPF_VECTOR) 167 DEF(ssadd_vec, 1, 2, 0, TCG_OPF_VECTOR) 168 DEF(usadd_vec, 1, 2, 0, TCG_OPF_VECTOR) 169 DEF(sssub_vec, 1, 2, 0, TCG_OPF_VECTOR) 170 DEF(ussub_vec, 1, 2, 0, TCG_OPF_VECTOR) 171 DEF(smin_vec, 1, 2, 0, TCG_OPF_VECTOR) 172 DEF(umin_vec, 1, 2, 0, TCG_OPF_VECTOR) 173 DEF(smax_vec, 1, 2, 0, TCG_OPF_VECTOR) 174 DEF(umax_vec, 1, 2, 0, TCG_OPF_VECTOR) 175 176 DEF(and_vec, 1, 2, 0, TCG_OPF_VECTOR) 177 DEF(or_vec, 1, 2, 0, TCG_OPF_VECTOR) 178 DEF(xor_vec, 1, 2, 0, TCG_OPF_VECTOR) 179 DEF(andc_vec, 1, 2, 0, TCG_OPF_VECTOR) 180 DEF(orc_vec, 1, 2, 0, TCG_OPF_VECTOR) 181 DEF(nand_vec, 1, 2, 0, TCG_OPF_VECTOR) 182 DEF(nor_vec, 1, 2, 0, TCG_OPF_VECTOR) 183 DEF(eqv_vec, 1, 2, 0, TCG_OPF_VECTOR) 184 DEF(not_vec, 1, 1, 0, TCG_OPF_VECTOR) 185 186 DEF(shli_vec, 1, 1, 1, TCG_OPF_VECTOR) 187 DEF(shri_vec, 1, 1, 1, TCG_OPF_VECTOR) 188 DEF(sari_vec, 1, 1, 1, TCG_OPF_VECTOR) 189 DEF(rotli_vec, 1, 1, 1, TCG_OPF_VECTOR) 190 191 DEF(shls_vec, 1, 2, 0, TCG_OPF_VECTOR) 192 DEF(shrs_vec, 1, 2, 0, TCG_OPF_VECTOR) 193 DEF(sars_vec, 1, 2, 0, TCG_OPF_VECTOR) 194 DEF(rotls_vec, 1, 2, 0, TCG_OPF_VECTOR) 195 196 DEF(shlv_vec, 1, 2, 0, TCG_OPF_VECTOR) 197 DEF(shrv_vec, 1, 2, 0, TCG_OPF_VECTOR) 198 DEF(sarv_vec, 1, 2, 0, TCG_OPF_VECTOR) 199 DEF(rotlv_vec, 1, 2, 0, TCG_OPF_VECTOR) 200 DEF(rotrv_vec, 1, 2, 0, TCG_OPF_VECTOR) 201 202 DEF(cmp_vec, 1, 2, 1, TCG_OPF_VECTOR) 203 204 DEF(bitsel_vec, 1, 3, 0, TCG_OPF_VECTOR) 205 DEF(cmpsel_vec, 1, 4, 1, TCG_OPF_VECTOR) 206 207 DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) 208 209 #include "tcg-target-opc.h.inc" 210 211 #undef DATA64_ARGS 212 #undef DEF 213