1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef TCG_TCG_OP_H 26 #define TCG_TCG_OP_H 27 28 #include "tcg/tcg.h" 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 /* Basic output routines. Not for general consumption. */ 33 34 void tcg_gen_op1(TCGOpcode, TCGArg); 35 void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); 36 void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); 37 void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); 38 void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); 39 void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); 40 41 void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); 42 void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); 43 void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); 44 45 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) 46 { 47 tcg_gen_op1(opc, tcgv_i32_arg(a1)); 48 } 49 50 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) 51 { 52 tcg_gen_op1(opc, tcgv_i64_arg(a1)); 53 } 54 55 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) 56 { 57 tcg_gen_op1(opc, a1); 58 } 59 60 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) 61 { 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); 63 } 64 65 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) 66 { 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); 68 } 69 70 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) 71 { 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); 73 } 74 75 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) 76 { 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); 78 } 79 80 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) 81 { 82 tcg_gen_op2(opc, a1, a2); 83 } 84 85 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, 86 TCGv_i32 a2, TCGv_i32 a3) 87 { 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); 89 } 90 91 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, 92 TCGv_i64 a2, TCGv_i64 a3) 93 { 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); 95 } 96 97 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, 98 TCGv_i32 a2, TCGArg a3) 99 { 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); 101 } 102 103 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, 104 TCGv_i64 a2, TCGArg a3) 105 { 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); 107 } 108 109 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, 110 TCGv_ptr base, TCGArg offset) 111 { 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); 113 } 114 115 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, 116 TCGv_ptr base, TCGArg offset) 117 { 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); 119 } 120 121 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 122 TCGv_i32 a3, TCGv_i32 a4) 123 { 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 125 tcgv_i32_arg(a3), tcgv_i32_arg(a4)); 126 } 127 128 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 129 TCGv_i64 a3, TCGv_i64 a4) 130 { 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 132 tcgv_i64_arg(a3), tcgv_i64_arg(a4)); 133 } 134 135 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 136 TCGv_i32 a3, TCGArg a4) 137 { 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 139 tcgv_i32_arg(a3), a4); 140 } 141 142 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 143 TCGv_i64 a3, TCGArg a4) 144 { 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 146 tcgv_i64_arg(a3), a4); 147 } 148 149 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 150 TCGArg a3, TCGArg a4) 151 { 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); 153 } 154 155 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 156 TCGArg a3, TCGArg a4) 157 { 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); 159 } 160 161 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) 163 { 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); 166 } 167 168 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) 170 { 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); 173 } 174 175 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) 177 { 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); 180 } 181 182 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) 184 { 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); 187 } 188 189 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 190 TCGv_i32 a3, TCGArg a4, TCGArg a5) 191 { 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 193 tcgv_i32_arg(a3), a4, a5); 194 } 195 196 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 197 TCGv_i64 a3, TCGArg a4, TCGArg a5) 198 { 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 200 tcgv_i64_arg(a3), a4, a5); 201 } 202 203 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 204 TCGv_i32 a3, TCGv_i32 a4, 205 TCGv_i32 a5, TCGv_i32 a6) 206 { 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), 209 tcgv_i32_arg(a6)); 210 } 211 212 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 213 TCGv_i64 a3, TCGv_i64 a4, 214 TCGv_i64 a5, TCGv_i64 a6) 215 { 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), 218 tcgv_i64_arg(a6)); 219 } 220 221 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 222 TCGv_i32 a3, TCGv_i32 a4, 223 TCGv_i32 a5, TCGArg a6) 224 { 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); 227 } 228 229 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 230 TCGv_i64 a3, TCGv_i64 a4, 231 TCGv_i64 a5, TCGArg a6) 232 { 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); 235 } 236 237 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, 238 TCGv_i32 a3, TCGv_i32 a4, 239 TCGArg a5, TCGArg a6) 240 { 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), 242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); 243 } 244 245 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, 246 TCGv_i64 a3, TCGv_i64 a4, 247 TCGArg a5, TCGArg a6) 248 { 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), 250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); 251 } 252 253 254 /* Generic ops. */ 255 256 static inline void gen_set_label(TCGLabel *l) 257 { 258 l->present = 1; 259 tcg_gen_op1(INDEX_op_set_label, label_arg(l)); 260 } 261 262 static inline void tcg_gen_br(TCGLabel *l) 263 { 264 l->refs++; 265 tcg_gen_op1(INDEX_op_br, label_arg(l)); 266 } 267 268 void tcg_gen_mb(TCGBar); 269 270 /* Helper calls. */ 271 272 /* 32 bit ops */ 273 274 void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); 275 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 276 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); 277 void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 278 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 279 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 280 void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 281 void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 282 void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 283 void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 284 void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 285 void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 286 void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 287 void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 288 void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 289 void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 290 void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 291 void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 292 void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 293 void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 294 void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 295 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 296 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); 297 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); 298 void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); 299 void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); 300 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 301 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 302 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); 303 void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); 304 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, 305 unsigned int ofs, unsigned int len); 306 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, 307 unsigned int ofs, unsigned int len); 308 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, 309 unsigned int ofs, unsigned int len); 310 void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, 311 unsigned int ofs, unsigned int len); 312 void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, 313 unsigned int ofs); 314 void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); 315 void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); 316 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, 317 TCGv_i32 arg1, TCGv_i32 arg2); 318 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, 319 TCGv_i32 arg1, int32_t arg2); 320 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, 321 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); 322 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 323 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); 324 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, 325 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); 326 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 327 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 328 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); 329 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); 330 void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); 331 void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); 332 void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); 333 void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); 334 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); 335 void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); 336 void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 337 void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 338 void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 339 void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); 340 void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); 341 342 /* Replicate a value of size @vece from @in to all the lanes in @out */ 343 void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); 344 345 static inline void tcg_gen_discard_i32(TCGv_i32 arg) 346 { 347 tcg_gen_op1_i32(INDEX_op_discard, arg); 348 } 349 350 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) 351 { 352 if (ret != arg) { 353 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); 354 } 355 } 356 357 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, 358 tcg_target_long offset) 359 { 360 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); 361 } 362 363 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, 364 tcg_target_long offset) 365 { 366 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); 367 } 368 369 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, 370 tcg_target_long offset) 371 { 372 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); 373 } 374 375 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, 376 tcg_target_long offset) 377 { 378 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); 379 } 380 381 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, 382 tcg_target_long offset) 383 { 384 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); 385 } 386 387 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, 388 tcg_target_long offset) 389 { 390 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); 391 } 392 393 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, 394 tcg_target_long offset) 395 { 396 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); 397 } 398 399 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, 400 tcg_target_long offset) 401 { 402 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); 403 } 404 405 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 406 { 407 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); 408 } 409 410 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 411 { 412 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); 413 } 414 415 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 416 { 417 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); 418 } 419 420 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 421 { 422 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); 423 } 424 425 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 426 { 427 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); 428 } 429 430 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 431 { 432 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); 433 } 434 435 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 436 { 437 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); 438 } 439 440 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 441 { 442 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); 443 } 444 445 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 446 { 447 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); 448 } 449 450 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) 451 { 452 if (TCG_TARGET_HAS_neg_i32) { 453 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); 454 } else { 455 tcg_gen_subfi_i32(ret, 0, arg); 456 } 457 } 458 459 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) 460 { 461 if (TCG_TARGET_HAS_not_i32) { 462 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); 463 } else { 464 tcg_gen_xori_i32(ret, arg, -1); 465 } 466 } 467 468 /* 64 bit ops */ 469 470 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); 471 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 472 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); 473 void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 474 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 475 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 476 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 477 void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 478 void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 479 void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 480 void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 481 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 482 void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 483 void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 484 void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 485 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 486 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 487 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 488 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 489 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 490 void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 491 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 492 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); 493 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); 494 void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); 495 void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); 496 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 497 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 498 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 499 void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); 500 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, 501 unsigned int ofs, unsigned int len); 502 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, 503 unsigned int ofs, unsigned int len); 504 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, 505 unsigned int ofs, unsigned int len); 506 void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, 507 unsigned int ofs, unsigned int len); 508 void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, 509 unsigned int ofs); 510 void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); 511 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); 512 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, 513 TCGv_i64 arg1, TCGv_i64 arg2); 514 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, 515 TCGv_i64 arg1, int64_t arg2); 516 void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, 517 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); 518 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 519 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); 520 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, 521 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); 522 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 523 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 524 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); 525 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); 526 void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); 527 void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); 528 void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); 529 void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); 530 void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); 531 void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); 532 void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); 533 void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); 534 void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); 535 void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); 536 void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); 537 void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 538 void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 539 void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 540 void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); 541 void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); 542 543 /* Replicate a value of size @vece from @in to all the lanes in @out */ 544 void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); 545 546 #if TCG_TARGET_REG_BITS == 64 547 static inline void tcg_gen_discard_i64(TCGv_i64 arg) 548 { 549 tcg_gen_op1_i64(INDEX_op_discard, arg); 550 } 551 552 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) 553 { 554 if (ret != arg) { 555 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); 556 } 557 } 558 559 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, 560 tcg_target_long offset) 561 { 562 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); 563 } 564 565 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, 566 tcg_target_long offset) 567 { 568 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); 569 } 570 571 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, 572 tcg_target_long offset) 573 { 574 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); 575 } 576 577 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, 578 tcg_target_long offset) 579 { 580 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); 581 } 582 583 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, 584 tcg_target_long offset) 585 { 586 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); 587 } 588 589 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, 590 tcg_target_long offset) 591 { 592 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); 593 } 594 595 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, 596 tcg_target_long offset) 597 { 598 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); 599 } 600 601 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, 602 tcg_target_long offset) 603 { 604 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); 605 } 606 607 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, 608 tcg_target_long offset) 609 { 610 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); 611 } 612 613 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, 614 tcg_target_long offset) 615 { 616 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); 617 } 618 619 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, 620 tcg_target_long offset) 621 { 622 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); 623 } 624 625 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 626 { 627 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); 628 } 629 630 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 631 { 632 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); 633 } 634 635 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 636 { 637 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); 638 } 639 640 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 641 { 642 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); 643 } 644 645 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 646 { 647 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); 648 } 649 650 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 651 { 652 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); 653 } 654 655 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 656 { 657 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); 658 } 659 660 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 661 { 662 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); 663 } 664 665 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) 666 { 667 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); 668 } 669 #else /* TCG_TARGET_REG_BITS == 32 */ 670 void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 671 void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 672 void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 673 674 void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 675 void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 676 677 void tcg_gen_discard_i64(TCGv_i64 arg); 678 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); 679 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 680 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 681 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 682 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 683 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 684 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 685 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); 686 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); 687 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 688 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 689 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 690 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 691 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 692 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 693 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); 694 #endif /* TCG_TARGET_REG_BITS */ 695 696 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) 697 { 698 if (TCG_TARGET_HAS_neg_i64) { 699 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); 700 } else { 701 tcg_gen_subfi_i64(ret, 0, arg); 702 } 703 } 704 705 /* Size changing operations. */ 706 707 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); 708 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); 709 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); 710 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); 711 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); 712 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); 713 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); 714 715 void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); 716 void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); 717 void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); 718 719 static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) 720 { 721 tcg_gen_deposit_i64(ret, lo, hi, 32, 32); 722 } 723 724 /* QEMU specific operations. */ 725 726 #ifndef TARGET_LONG_BITS 727 #error must include QEMU headers 728 #endif 729 730 #if TARGET_INSN_START_WORDS == 1 731 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 732 static inline void tcg_gen_insn_start(target_ulong pc) 733 { 734 tcg_gen_op1(INDEX_op_insn_start, pc); 735 } 736 # else 737 static inline void tcg_gen_insn_start(target_ulong pc) 738 { 739 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); 740 } 741 # endif 742 #elif TARGET_INSN_START_WORDS == 2 743 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 744 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) 745 { 746 tcg_gen_op2(INDEX_op_insn_start, pc, a1); 747 } 748 # else 749 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) 750 { 751 tcg_gen_op4(INDEX_op_insn_start, 752 (uint32_t)pc, (uint32_t)(pc >> 32), 753 (uint32_t)a1, (uint32_t)(a1 >> 32)); 754 } 755 # endif 756 #elif TARGET_INSN_START_WORDS == 3 757 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 758 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, 759 target_ulong a2) 760 { 761 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); 762 } 763 # else 764 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, 765 target_ulong a2) 766 { 767 tcg_gen_op6(INDEX_op_insn_start, 768 (uint32_t)pc, (uint32_t)(pc >> 32), 769 (uint32_t)a1, (uint32_t)(a1 >> 32), 770 (uint32_t)a2, (uint32_t)(a2 >> 32)); 771 } 772 # endif 773 #else 774 # error "Unhandled number of operands to insn_start" 775 #endif 776 777 /** 778 * tcg_gen_exit_tb() - output exit_tb TCG operation 779 * @tb: The TranslationBlock from which we are exiting 780 * @idx: Direct jump slot index, or exit request 781 * 782 * See tcg/README for more info about this TCG operation. 783 * See also tcg.h and the block comment above TB_EXIT_MASK. 784 * 785 * For a normal exit from the TB, back to the main loop, @tb should 786 * be NULL and @idx should be 0. Otherwise, @tb should be valid and 787 * @idx should be one of the TB_EXIT_ values. 788 */ 789 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); 790 791 /** 792 * tcg_gen_goto_tb() - output goto_tb TCG operation 793 * @idx: Direct jump slot index (0 or 1) 794 * 795 * See tcg/README for more info about this TCG operation. 796 * 797 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within 798 * the pages this TB resides in because we don't take care of direct jumps when 799 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a 800 * static address translation, so the destination address is always valid, TBs 801 * are always invalidated properly, and direct jumps are reset when mapping 802 * changes. 803 */ 804 void tcg_gen_goto_tb(unsigned idx); 805 806 /** 807 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid 808 * @addr: Guest address of the target TB 809 * 810 * If the TB is not valid, jump to the epilogue. 811 * 812 * This operation is optional. If the TCG backend does not implement goto_ptr, 813 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. 814 */ 815 void tcg_gen_lookup_and_goto_ptr(void); 816 817 static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type, 818 unsigned wr) 819 { 820 tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr); 821 } 822 823 static inline void tcg_gen_plugin_cb_end(void) 824 { 825 tcg_emit_op(INDEX_op_plugin_cb_end, 0); 826 } 827 828 #if TARGET_LONG_BITS == 32 829 #define tcg_temp_new() tcg_temp_new_i32() 830 #define tcg_global_mem_new tcg_global_mem_new_i32 831 #define tcg_temp_local_new() tcg_temp_local_new_i32() 832 #define tcg_temp_free tcg_temp_free_i32 833 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 834 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 835 #else 836 #define tcg_temp_new() tcg_temp_new_i64() 837 #define tcg_global_mem_new tcg_global_mem_new_i64 838 #define tcg_temp_local_new() tcg_temp_local_new_i64() 839 #define tcg_temp_free tcg_temp_free_i64 840 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 841 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 842 #endif 843 844 void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); 845 void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); 846 void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); 847 void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); 848 void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); 849 void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); 850 851 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) 852 { 853 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); 854 } 855 856 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) 857 { 858 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); 859 } 860 861 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) 862 { 863 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); 864 } 865 866 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) 867 { 868 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); 869 } 870 871 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) 872 { 873 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); 874 } 875 876 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) 877 { 878 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); 879 } 880 881 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) 882 { 883 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ); 884 } 885 886 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) 887 { 888 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); 889 } 890 891 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) 892 { 893 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); 894 } 895 896 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) 897 { 898 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); 899 } 900 901 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) 902 { 903 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ); 904 } 905 906 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, 907 TCGArg, MemOp); 908 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, 909 TCGArg, MemOp); 910 void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, 911 TCGArg, MemOp); 912 913 void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, 914 TCGArg, MemOp); 915 void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, 916 TCGArg, MemOp); 917 void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, 918 TCGArg, MemOp); 919 920 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 921 void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 922 923 void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 924 void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 925 void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 926 void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 927 void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 928 void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 929 void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 930 void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 931 void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 932 void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 933 void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 934 void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 935 void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 936 void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 937 void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 938 void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 939 940 void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 941 void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 942 void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 943 void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 944 void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 945 void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 946 void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 947 void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 948 void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 949 void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 950 void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 951 void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 952 void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 953 void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 954 void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); 955 void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); 956 957 void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); 958 void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); 959 void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); 960 void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); 961 void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); 962 void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 963 void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 964 void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 965 void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 966 void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 967 void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 968 void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 969 void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 970 void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 971 void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 972 void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 973 void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); 974 void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); 975 void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); 976 void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 977 void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 978 void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 979 void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 980 void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 981 void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 982 void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 983 void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); 984 985 void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 986 void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 987 void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 988 void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 989 void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); 990 991 void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 992 void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 993 void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 994 void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); 995 996 void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 997 void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 998 void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 999 void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 1000 void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); 1001 1002 void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, 1003 TCGv_vec a, TCGv_vec b); 1004 1005 void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, 1006 TCGv_vec b, TCGv_vec c); 1007 void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, 1008 TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); 1009 1010 void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); 1011 void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); 1012 void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); 1013 1014 #if TARGET_LONG_BITS == 64 1015 #define tcg_gen_movi_tl tcg_gen_movi_i64 1016 #define tcg_gen_mov_tl tcg_gen_mov_i64 1017 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 1018 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 1019 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 1020 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 1021 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 1022 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 1023 #define tcg_gen_ld_tl tcg_gen_ld_i64 1024 #define tcg_gen_st8_tl tcg_gen_st8_i64 1025 #define tcg_gen_st16_tl tcg_gen_st16_i64 1026 #define tcg_gen_st32_tl tcg_gen_st32_i64 1027 #define tcg_gen_st_tl tcg_gen_st_i64 1028 #define tcg_gen_add_tl tcg_gen_add_i64 1029 #define tcg_gen_addi_tl tcg_gen_addi_i64 1030 #define tcg_gen_sub_tl tcg_gen_sub_i64 1031 #define tcg_gen_neg_tl tcg_gen_neg_i64 1032 #define tcg_gen_abs_tl tcg_gen_abs_i64 1033 #define tcg_gen_subfi_tl tcg_gen_subfi_i64 1034 #define tcg_gen_subi_tl tcg_gen_subi_i64 1035 #define tcg_gen_and_tl tcg_gen_and_i64 1036 #define tcg_gen_andi_tl tcg_gen_andi_i64 1037 #define tcg_gen_or_tl tcg_gen_or_i64 1038 #define tcg_gen_ori_tl tcg_gen_ori_i64 1039 #define tcg_gen_xor_tl tcg_gen_xor_i64 1040 #define tcg_gen_xori_tl tcg_gen_xori_i64 1041 #define tcg_gen_not_tl tcg_gen_not_i64 1042 #define tcg_gen_shl_tl tcg_gen_shl_i64 1043 #define tcg_gen_shli_tl tcg_gen_shli_i64 1044 #define tcg_gen_shr_tl tcg_gen_shr_i64 1045 #define tcg_gen_shri_tl tcg_gen_shri_i64 1046 #define tcg_gen_sar_tl tcg_gen_sar_i64 1047 #define tcg_gen_sari_tl tcg_gen_sari_i64 1048 #define tcg_gen_brcond_tl tcg_gen_brcond_i64 1049 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 1050 #define tcg_gen_setcond_tl tcg_gen_setcond_i64 1051 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 1052 #define tcg_gen_mul_tl tcg_gen_mul_i64 1053 #define tcg_gen_muli_tl tcg_gen_muli_i64 1054 #define tcg_gen_div_tl tcg_gen_div_i64 1055 #define tcg_gen_rem_tl tcg_gen_rem_i64 1056 #define tcg_gen_divu_tl tcg_gen_divu_i64 1057 #define tcg_gen_remu_tl tcg_gen_remu_i64 1058 #define tcg_gen_discard_tl tcg_gen_discard_i64 1059 #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 1060 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 1061 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 1062 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 1063 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 1064 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 1065 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 1066 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 1067 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 1068 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 1069 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 1070 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 1071 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 1072 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 1073 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 1074 #define tcg_gen_bswap_tl tcg_gen_bswap64_i64 1075 #define tcg_gen_hswap_tl tcg_gen_hswap_i64 1076 #define tcg_gen_wswap_tl tcg_gen_wswap_i64 1077 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 1078 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 1079 #define tcg_gen_andc_tl tcg_gen_andc_i64 1080 #define tcg_gen_eqv_tl tcg_gen_eqv_i64 1081 #define tcg_gen_nand_tl tcg_gen_nand_i64 1082 #define tcg_gen_nor_tl tcg_gen_nor_i64 1083 #define tcg_gen_orc_tl tcg_gen_orc_i64 1084 #define tcg_gen_clz_tl tcg_gen_clz_i64 1085 #define tcg_gen_ctz_tl tcg_gen_ctz_i64 1086 #define tcg_gen_clzi_tl tcg_gen_clzi_i64 1087 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 1088 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 1089 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 1090 #define tcg_gen_rotl_tl tcg_gen_rotl_i64 1091 #define tcg_gen_rotli_tl tcg_gen_rotli_i64 1092 #define tcg_gen_rotr_tl tcg_gen_rotr_i64 1093 #define tcg_gen_rotri_tl tcg_gen_rotri_i64 1094 #define tcg_gen_deposit_tl tcg_gen_deposit_i64 1095 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 1096 #define tcg_gen_extract_tl tcg_gen_extract_i64 1097 #define tcg_gen_sextract_tl tcg_gen_sextract_i64 1098 #define tcg_gen_extract2_tl tcg_gen_extract2_i64 1099 #define tcg_const_tl tcg_const_i64 1100 #define tcg_constant_tl tcg_constant_i64 1101 #define tcg_const_local_tl tcg_const_local_i64 1102 #define tcg_gen_movcond_tl tcg_gen_movcond_i64 1103 #define tcg_gen_add2_tl tcg_gen_add2_i64 1104 #define tcg_gen_sub2_tl tcg_gen_sub2_i64 1105 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 1106 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 1107 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 1108 #define tcg_gen_smin_tl tcg_gen_smin_i64 1109 #define tcg_gen_umin_tl tcg_gen_umin_i64 1110 #define tcg_gen_smax_tl tcg_gen_smax_i64 1111 #define tcg_gen_umax_tl tcg_gen_umax_i64 1112 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 1113 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 1114 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 1115 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 1116 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 1117 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 1118 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64 1119 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64 1120 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64 1121 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64 1122 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 1123 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 1124 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 1125 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 1126 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64 1127 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 1128 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 1129 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 1130 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec 1131 #define tcg_gen_dup_tl tcg_gen_dup_i64 1132 #else 1133 #define tcg_gen_movi_tl tcg_gen_movi_i32 1134 #define tcg_gen_mov_tl tcg_gen_mov_i32 1135 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 1136 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 1137 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 1138 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 1139 #define tcg_gen_ld32u_tl tcg_gen_ld_i32 1140 #define tcg_gen_ld32s_tl tcg_gen_ld_i32 1141 #define tcg_gen_ld_tl tcg_gen_ld_i32 1142 #define tcg_gen_st8_tl tcg_gen_st8_i32 1143 #define tcg_gen_st16_tl tcg_gen_st16_i32 1144 #define tcg_gen_st32_tl tcg_gen_st_i32 1145 #define tcg_gen_st_tl tcg_gen_st_i32 1146 #define tcg_gen_add_tl tcg_gen_add_i32 1147 #define tcg_gen_addi_tl tcg_gen_addi_i32 1148 #define tcg_gen_sub_tl tcg_gen_sub_i32 1149 #define tcg_gen_neg_tl tcg_gen_neg_i32 1150 #define tcg_gen_abs_tl tcg_gen_abs_i32 1151 #define tcg_gen_subfi_tl tcg_gen_subfi_i32 1152 #define tcg_gen_subi_tl tcg_gen_subi_i32 1153 #define tcg_gen_and_tl tcg_gen_and_i32 1154 #define tcg_gen_andi_tl tcg_gen_andi_i32 1155 #define tcg_gen_or_tl tcg_gen_or_i32 1156 #define tcg_gen_ori_tl tcg_gen_ori_i32 1157 #define tcg_gen_xor_tl tcg_gen_xor_i32 1158 #define tcg_gen_xori_tl tcg_gen_xori_i32 1159 #define tcg_gen_not_tl tcg_gen_not_i32 1160 #define tcg_gen_shl_tl tcg_gen_shl_i32 1161 #define tcg_gen_shli_tl tcg_gen_shli_i32 1162 #define tcg_gen_shr_tl tcg_gen_shr_i32 1163 #define tcg_gen_shri_tl tcg_gen_shri_i32 1164 #define tcg_gen_sar_tl tcg_gen_sar_i32 1165 #define tcg_gen_sari_tl tcg_gen_sari_i32 1166 #define tcg_gen_brcond_tl tcg_gen_brcond_i32 1167 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 1168 #define tcg_gen_setcond_tl tcg_gen_setcond_i32 1169 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 1170 #define tcg_gen_mul_tl tcg_gen_mul_i32 1171 #define tcg_gen_muli_tl tcg_gen_muli_i32 1172 #define tcg_gen_div_tl tcg_gen_div_i32 1173 #define tcg_gen_rem_tl tcg_gen_rem_i32 1174 #define tcg_gen_divu_tl tcg_gen_divu_i32 1175 #define tcg_gen_remu_tl tcg_gen_remu_i32 1176 #define tcg_gen_discard_tl tcg_gen_discard_i32 1177 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 1178 #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 1179 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 1180 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 1181 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 1182 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 1183 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 1184 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 1185 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 1186 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 1187 #define tcg_gen_ext32u_tl tcg_gen_mov_i32 1188 #define tcg_gen_ext32s_tl tcg_gen_mov_i32 1189 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 1190 #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S) 1191 #define tcg_gen_bswap_tl tcg_gen_bswap32_i32 1192 #define tcg_gen_hswap_tl tcg_gen_hswap_i32 1193 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 1194 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 1195 #define tcg_gen_andc_tl tcg_gen_andc_i32 1196 #define tcg_gen_eqv_tl tcg_gen_eqv_i32 1197 #define tcg_gen_nand_tl tcg_gen_nand_i32 1198 #define tcg_gen_nor_tl tcg_gen_nor_i32 1199 #define tcg_gen_orc_tl tcg_gen_orc_i32 1200 #define tcg_gen_clz_tl tcg_gen_clz_i32 1201 #define tcg_gen_ctz_tl tcg_gen_ctz_i32 1202 #define tcg_gen_clzi_tl tcg_gen_clzi_i32 1203 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 1204 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 1205 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 1206 #define tcg_gen_rotl_tl tcg_gen_rotl_i32 1207 #define tcg_gen_rotli_tl tcg_gen_rotli_i32 1208 #define tcg_gen_rotr_tl tcg_gen_rotr_i32 1209 #define tcg_gen_rotri_tl tcg_gen_rotri_i32 1210 #define tcg_gen_deposit_tl tcg_gen_deposit_i32 1211 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 1212 #define tcg_gen_extract_tl tcg_gen_extract_i32 1213 #define tcg_gen_sextract_tl tcg_gen_sextract_i32 1214 #define tcg_gen_extract2_tl tcg_gen_extract2_i32 1215 #define tcg_const_tl tcg_const_i32 1216 #define tcg_constant_tl tcg_constant_i32 1217 #define tcg_const_local_tl tcg_const_local_i32 1218 #define tcg_gen_movcond_tl tcg_gen_movcond_i32 1219 #define tcg_gen_add2_tl tcg_gen_add2_i32 1220 #define tcg_gen_sub2_tl tcg_gen_sub2_i32 1221 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 1222 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 1223 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 1224 #define tcg_gen_smin_tl tcg_gen_smin_i32 1225 #define tcg_gen_umin_tl tcg_gen_umin_i32 1226 #define tcg_gen_smax_tl tcg_gen_smax_i32 1227 #define tcg_gen_umax_tl tcg_gen_umax_i32 1228 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 1229 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 1230 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 1231 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 1232 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 1233 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 1234 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32 1235 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32 1236 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32 1237 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32 1238 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 1239 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 1240 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 1241 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 1242 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32 1243 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 1244 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 1245 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 1246 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec 1247 #define tcg_gen_dup_tl tcg_gen_dup_i32 1248 #endif 1249 1250 #if UINTPTR_MAX == UINT32_MAX 1251 # define PTR i32 1252 # define NAT TCGv_i32 1253 #else 1254 # define PTR i64 1255 # define NAT TCGv_i64 1256 #endif 1257 1258 static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) 1259 { 1260 glue(tcg_gen_ld_,PTR)((NAT)r, a, o); 1261 } 1262 1263 static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) 1264 { 1265 glue(tcg_gen_st_, PTR)((NAT)r, a, o); 1266 } 1267 1268 static inline void tcg_gen_discard_ptr(TCGv_ptr a) 1269 { 1270 glue(tcg_gen_discard_,PTR)((NAT)a); 1271 } 1272 1273 static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) 1274 { 1275 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); 1276 } 1277 1278 static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) 1279 { 1280 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); 1281 } 1282 1283 static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) 1284 { 1285 glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); 1286 } 1287 1288 static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, 1289 intptr_t b, TCGLabel *label) 1290 { 1291 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); 1292 } 1293 1294 static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) 1295 { 1296 #if UINTPTR_MAX == UINT32_MAX 1297 tcg_gen_mov_i32((NAT)r, a); 1298 #else 1299 tcg_gen_ext_i32_i64((NAT)r, a); 1300 #endif 1301 } 1302 1303 static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) 1304 { 1305 #if UINTPTR_MAX == UINT32_MAX 1306 tcg_gen_extrl_i64_i32((NAT)r, a); 1307 #else 1308 tcg_gen_mov_i64((NAT)r, a); 1309 #endif 1310 } 1311 1312 static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) 1313 { 1314 #if UINTPTR_MAX == UINT32_MAX 1315 tcg_gen_extu_i32_i64(r, (NAT)a); 1316 #else 1317 tcg_gen_mov_i64(r, (NAT)a); 1318 #endif 1319 } 1320 1321 static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) 1322 { 1323 #if UINTPTR_MAX == UINT32_MAX 1324 tcg_gen_mov_i32(r, (NAT)a); 1325 #else 1326 tcg_gen_extrl_i64_i32(r, (NAT)a); 1327 #endif 1328 } 1329 1330 #undef PTR 1331 #undef NAT 1332 1333 #endif /* TCG_TCG_OP_H */ 1334