1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Target dependent opcode generation functions. 4 * 5 * Copyright (c) 2008 Fabrice Bellard 6 */ 7 8 #ifndef TCG_TCG_OP_H 9 #define TCG_TCG_OP_H 10 11 #include "tcg/tcg-op-common.h" 12 13 #ifndef TARGET_LONG_BITS 14 #error must include QEMU headers 15 #endif 16 17 #if TARGET_LONG_BITS == 32 18 # define TCG_TYPE_TL TCG_TYPE_I32 19 #elif TARGET_LONG_BITS == 64 20 # define TCG_TYPE_TL TCG_TYPE_I64 21 #else 22 # error 23 #endif 24 25 #ifndef TARGET_INSN_START_EXTRA_WORDS 26 static inline void tcg_gen_insn_start(target_ulong pc) 27 { 28 TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS); 29 tcg_set_insn_start_param(op, 0, pc); 30 } 31 #elif TARGET_INSN_START_EXTRA_WORDS == 1 32 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) 33 { 34 TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS); 35 tcg_set_insn_start_param(op, 0, pc); 36 tcg_set_insn_start_param(op, 1, a1); 37 } 38 #elif TARGET_INSN_START_EXTRA_WORDS == 2 39 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, 40 target_ulong a2) 41 { 42 TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG_BITS); 43 tcg_set_insn_start_param(op, 0, pc); 44 tcg_set_insn_start_param(op, 1, a1); 45 tcg_set_insn_start_param(op, 2, a2); 46 } 47 #else 48 #error Unhandled TARGET_INSN_START_EXTRA_WORDS value 49 #endif 50 51 #if TARGET_LONG_BITS == 32 52 typedef TCGv_i32 TCGv; 53 #define tcg_temp_new() tcg_temp_new_i32() 54 #define tcg_global_mem_new tcg_global_mem_new_i32 55 #define tcg_temp_free tcg_temp_free_i32 56 #define tcgv_tl_temp tcgv_i32_temp 57 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 58 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 59 #elif TARGET_LONG_BITS == 64 60 typedef TCGv_i64 TCGv; 61 #define tcg_temp_new() tcg_temp_new_i64() 62 #define tcg_global_mem_new tcg_global_mem_new_i64 63 #define tcg_temp_free tcg_temp_free_i64 64 #define tcgv_tl_temp tcgv_i64_temp 65 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 66 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 67 #else 68 #error Unhandled TARGET_LONG_BITS value 69 #endif 70 71 static inline void 72 tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) 73 { 74 tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); 75 } 76 77 static inline void 78 tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) 79 { 80 tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); 81 } 82 83 static inline void 84 tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) 85 { 86 tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); 87 } 88 89 static inline void 90 tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) 91 { 92 tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); 93 } 94 95 static inline void 96 tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) 97 { 98 tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); 99 } 100 101 static inline void 102 tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) 103 { 104 tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); 105 } 106 107 #define DEF_ATOMIC2(N, S) \ 108 static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \ 109 TCGArg i, MemOp m) \ 110 { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); } 111 112 #define DEF_ATOMIC3(N, S) \ 113 static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \ 114 TCGv_##S n, TCGArg i, MemOp m) \ 115 { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); } 116 117 DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) 118 DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64) 119 DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128) 120 121 DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32) 122 DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64) 123 DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128) 124 125 DEF_ATOMIC2(tcg_gen_atomic_xchg, i32) 126 DEF_ATOMIC2(tcg_gen_atomic_xchg, i64) 127 128 DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32) 129 DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64) 130 DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32) 131 DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64) 132 DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32) 133 DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64) 134 DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32) 135 DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64) 136 DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32) 137 DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64) 138 DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32) 139 DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64) 140 DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32) 141 DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64) 142 DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32) 143 DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64) 144 145 DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32) 146 DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64) 147 DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32) 148 DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64) 149 DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32) 150 DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64) 151 DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32) 152 DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64) 153 DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32) 154 DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64) 155 DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32) 156 DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64) 157 DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32) 158 DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64) 159 DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32) 160 DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) 161 162 #undef DEF_ATOMIC2 163 #undef DEF_ATOMIC3 164 165 #if TARGET_LONG_BITS == 64 166 #define tcg_gen_movi_tl tcg_gen_movi_i64 167 #define tcg_gen_mov_tl tcg_gen_mov_i64 168 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 169 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 170 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 171 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 172 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 173 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 174 #define tcg_gen_ld_tl tcg_gen_ld_i64 175 #define tcg_gen_st8_tl tcg_gen_st8_i64 176 #define tcg_gen_st16_tl tcg_gen_st16_i64 177 #define tcg_gen_st32_tl tcg_gen_st32_i64 178 #define tcg_gen_st_tl tcg_gen_st_i64 179 #define tcg_gen_add_tl tcg_gen_add_i64 180 #define tcg_gen_addi_tl tcg_gen_addi_i64 181 #define tcg_gen_sub_tl tcg_gen_sub_i64 182 #define tcg_gen_neg_tl tcg_gen_neg_i64 183 #define tcg_gen_abs_tl tcg_gen_abs_i64 184 #define tcg_gen_subfi_tl tcg_gen_subfi_i64 185 #define tcg_gen_subi_tl tcg_gen_subi_i64 186 #define tcg_gen_and_tl tcg_gen_and_i64 187 #define tcg_gen_andi_tl tcg_gen_andi_i64 188 #define tcg_gen_or_tl tcg_gen_or_i64 189 #define tcg_gen_ori_tl tcg_gen_ori_i64 190 #define tcg_gen_xor_tl tcg_gen_xor_i64 191 #define tcg_gen_xori_tl tcg_gen_xori_i64 192 #define tcg_gen_not_tl tcg_gen_not_i64 193 #define tcg_gen_shl_tl tcg_gen_shl_i64 194 #define tcg_gen_shli_tl tcg_gen_shli_i64 195 #define tcg_gen_shr_tl tcg_gen_shr_i64 196 #define tcg_gen_shri_tl tcg_gen_shri_i64 197 #define tcg_gen_sar_tl tcg_gen_sar_i64 198 #define tcg_gen_sari_tl tcg_gen_sari_i64 199 #define tcg_gen_brcond_tl tcg_gen_brcond_i64 200 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 201 #define tcg_gen_setcond_tl tcg_gen_setcond_i64 202 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 203 #define tcg_gen_mul_tl tcg_gen_mul_i64 204 #define tcg_gen_muli_tl tcg_gen_muli_i64 205 #define tcg_gen_div_tl tcg_gen_div_i64 206 #define tcg_gen_rem_tl tcg_gen_rem_i64 207 #define tcg_gen_divu_tl tcg_gen_divu_i64 208 #define tcg_gen_remu_tl tcg_gen_remu_i64 209 #define tcg_gen_discard_tl tcg_gen_discard_i64 210 #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 211 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 212 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 213 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 214 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 215 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 216 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 217 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 218 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 219 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 220 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 221 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 222 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 223 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 224 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 225 #define tcg_gen_bswap_tl tcg_gen_bswap64_i64 226 #define tcg_gen_hswap_tl tcg_gen_hswap_i64 227 #define tcg_gen_wswap_tl tcg_gen_wswap_i64 228 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 229 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 230 #define tcg_gen_andc_tl tcg_gen_andc_i64 231 #define tcg_gen_eqv_tl tcg_gen_eqv_i64 232 #define tcg_gen_nand_tl tcg_gen_nand_i64 233 #define tcg_gen_nor_tl tcg_gen_nor_i64 234 #define tcg_gen_orc_tl tcg_gen_orc_i64 235 #define tcg_gen_clz_tl tcg_gen_clz_i64 236 #define tcg_gen_ctz_tl tcg_gen_ctz_i64 237 #define tcg_gen_clzi_tl tcg_gen_clzi_i64 238 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 239 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 240 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 241 #define tcg_gen_rotl_tl tcg_gen_rotl_i64 242 #define tcg_gen_rotli_tl tcg_gen_rotli_i64 243 #define tcg_gen_rotr_tl tcg_gen_rotr_i64 244 #define tcg_gen_rotri_tl tcg_gen_rotri_i64 245 #define tcg_gen_deposit_tl tcg_gen_deposit_i64 246 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 247 #define tcg_gen_extract_tl tcg_gen_extract_i64 248 #define tcg_gen_sextract_tl tcg_gen_sextract_i64 249 #define tcg_gen_extract2_tl tcg_gen_extract2_i64 250 #define tcg_constant_tl tcg_constant_i64 251 #define tcg_gen_movcond_tl tcg_gen_movcond_i64 252 #define tcg_gen_add2_tl tcg_gen_add2_i64 253 #define tcg_gen_sub2_tl tcg_gen_sub2_i64 254 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 255 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 256 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 257 #define tcg_gen_smin_tl tcg_gen_smin_i64 258 #define tcg_gen_umin_tl tcg_gen_umin_i64 259 #define tcg_gen_smax_tl tcg_gen_smax_i64 260 #define tcg_gen_umax_tl tcg_gen_umax_i64 261 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 262 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 263 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 264 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 265 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 266 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 267 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64 268 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64 269 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64 270 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64 271 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 272 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 273 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 274 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 275 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64 276 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 277 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 278 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 279 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec 280 #define tcg_gen_dup_tl tcg_gen_dup_i64 281 #define dup_const_tl dup_const 282 #else 283 #define tcg_gen_movi_tl tcg_gen_movi_i32 284 #define tcg_gen_mov_tl tcg_gen_mov_i32 285 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 286 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 287 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 288 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 289 #define tcg_gen_ld32u_tl tcg_gen_ld_i32 290 #define tcg_gen_ld32s_tl tcg_gen_ld_i32 291 #define tcg_gen_ld_tl tcg_gen_ld_i32 292 #define tcg_gen_st8_tl tcg_gen_st8_i32 293 #define tcg_gen_st16_tl tcg_gen_st16_i32 294 #define tcg_gen_st32_tl tcg_gen_st_i32 295 #define tcg_gen_st_tl tcg_gen_st_i32 296 #define tcg_gen_add_tl tcg_gen_add_i32 297 #define tcg_gen_addi_tl tcg_gen_addi_i32 298 #define tcg_gen_sub_tl tcg_gen_sub_i32 299 #define tcg_gen_neg_tl tcg_gen_neg_i32 300 #define tcg_gen_abs_tl tcg_gen_abs_i32 301 #define tcg_gen_subfi_tl tcg_gen_subfi_i32 302 #define tcg_gen_subi_tl tcg_gen_subi_i32 303 #define tcg_gen_and_tl tcg_gen_and_i32 304 #define tcg_gen_andi_tl tcg_gen_andi_i32 305 #define tcg_gen_or_tl tcg_gen_or_i32 306 #define tcg_gen_ori_tl tcg_gen_ori_i32 307 #define tcg_gen_xor_tl tcg_gen_xor_i32 308 #define tcg_gen_xori_tl tcg_gen_xori_i32 309 #define tcg_gen_not_tl tcg_gen_not_i32 310 #define tcg_gen_shl_tl tcg_gen_shl_i32 311 #define tcg_gen_shli_tl tcg_gen_shli_i32 312 #define tcg_gen_shr_tl tcg_gen_shr_i32 313 #define tcg_gen_shri_tl tcg_gen_shri_i32 314 #define tcg_gen_sar_tl tcg_gen_sar_i32 315 #define tcg_gen_sari_tl tcg_gen_sari_i32 316 #define tcg_gen_brcond_tl tcg_gen_brcond_i32 317 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 318 #define tcg_gen_setcond_tl tcg_gen_setcond_i32 319 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 320 #define tcg_gen_mul_tl tcg_gen_mul_i32 321 #define tcg_gen_muli_tl tcg_gen_muli_i32 322 #define tcg_gen_div_tl tcg_gen_div_i32 323 #define tcg_gen_rem_tl tcg_gen_rem_i32 324 #define tcg_gen_divu_tl tcg_gen_divu_i32 325 #define tcg_gen_remu_tl tcg_gen_remu_i32 326 #define tcg_gen_discard_tl tcg_gen_discard_i32 327 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 328 #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 329 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 330 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 331 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 332 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 333 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 334 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 335 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 336 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 337 #define tcg_gen_ext32u_tl tcg_gen_mov_i32 338 #define tcg_gen_ext32s_tl tcg_gen_mov_i32 339 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 340 #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S) 341 #define tcg_gen_bswap_tl tcg_gen_bswap32_i32 342 #define tcg_gen_hswap_tl tcg_gen_hswap_i32 343 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 344 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 345 #define tcg_gen_andc_tl tcg_gen_andc_i32 346 #define tcg_gen_eqv_tl tcg_gen_eqv_i32 347 #define tcg_gen_nand_tl tcg_gen_nand_i32 348 #define tcg_gen_nor_tl tcg_gen_nor_i32 349 #define tcg_gen_orc_tl tcg_gen_orc_i32 350 #define tcg_gen_clz_tl tcg_gen_clz_i32 351 #define tcg_gen_ctz_tl tcg_gen_ctz_i32 352 #define tcg_gen_clzi_tl tcg_gen_clzi_i32 353 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 354 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 355 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 356 #define tcg_gen_rotl_tl tcg_gen_rotl_i32 357 #define tcg_gen_rotli_tl tcg_gen_rotli_i32 358 #define tcg_gen_rotr_tl tcg_gen_rotr_i32 359 #define tcg_gen_rotri_tl tcg_gen_rotri_i32 360 #define tcg_gen_deposit_tl tcg_gen_deposit_i32 361 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 362 #define tcg_gen_extract_tl tcg_gen_extract_i32 363 #define tcg_gen_sextract_tl tcg_gen_sextract_i32 364 #define tcg_gen_extract2_tl tcg_gen_extract2_i32 365 #define tcg_constant_tl tcg_constant_i32 366 #define tcg_gen_movcond_tl tcg_gen_movcond_i32 367 #define tcg_gen_add2_tl tcg_gen_add2_i32 368 #define tcg_gen_sub2_tl tcg_gen_sub2_i32 369 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 370 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 371 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 372 #define tcg_gen_smin_tl tcg_gen_smin_i32 373 #define tcg_gen_umin_tl tcg_gen_umin_i32 374 #define tcg_gen_smax_tl tcg_gen_smax_i32 375 #define tcg_gen_umax_tl tcg_gen_umax_i32 376 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 377 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 378 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 379 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 380 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 381 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 382 #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32 383 #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32 384 #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32 385 #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32 386 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 387 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 388 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 389 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 390 #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32 391 #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 392 #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 393 #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 394 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec 395 #define tcg_gen_dup_tl tcg_gen_dup_i32 396 397 #define dup_const_tl(VECE, C) \ 398 (__builtin_constant_p(VECE) \ 399 ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ 400 : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ 401 : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ 402 : (qemu_build_not_reached_always(), 0)) \ 403 : (target_long)dup_const(VECE, C)) 404 405 #endif /* TARGET_LONG_BITS == 64 */ 406 #endif /* TCG_TCG_OP_H */ 407