1 #ifndef QEMU_ARCH_INIT_H 2 #define QEMU_ARCH_INIT_H 3 4 5 enum { 6 QEMU_ARCH_ALL = -1, 7 QEMU_ARCH_ALPHA = (1 << 0), 8 QEMU_ARCH_ARM = (1 << 1), 9 QEMU_ARCH_CRIS = (1 << 2), 10 QEMU_ARCH_I386 = (1 << 3), 11 QEMU_ARCH_M68K = (1 << 4), 12 QEMU_ARCH_LM32 = (1 << 5), 13 QEMU_ARCH_MICROBLAZE = (1 << 6), 14 QEMU_ARCH_MIPS = (1 << 7), 15 QEMU_ARCH_PPC = (1 << 8), 16 QEMU_ARCH_S390X = (1 << 9), 17 QEMU_ARCH_SH4 = (1 << 10), 18 QEMU_ARCH_SPARC = (1 << 11), 19 QEMU_ARCH_XTENSA = (1 << 12), 20 QEMU_ARCH_OPENRISC = (1 << 13), 21 QEMU_ARCH_UNICORE32 = (1 << 14), 22 QEMU_ARCH_MOXIE = (1 << 15), 23 QEMU_ARCH_TRICORE = (1 << 16), 24 QEMU_ARCH_NIOS2 = (1 << 17), 25 QEMU_ARCH_HPPA = (1 << 18), 26 QEMU_ARCH_RISCV = (1 << 19), 27 QEMU_ARCH_RX = (1 << 20), 28 QEMU_ARCH_AVR = (1 << 21), 29 30 QEMU_ARCH_NONE = (1 << 31), 31 }; 32 33 extern const uint32_t arch_type; 34 35 int kvm_available(void); 36 int xen_available(void); 37 38 /* default virtio transport per architecture */ 39 #define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \ 40 QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \ 41 QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \ 42 QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \ 43 QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA) 44 #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X) 45 #define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K) 46 47 #endif 48