1*ef17dd6aSVivek Goyal /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ 2*ef17dd6aSVivek Goyal /* 3*ef17dd6aSVivek Goyal * Copyright (C) 2021 Intel Corporation 4*ef17dd6aSVivek Goyal * Author: Johannes Berg <johannes@sipsolutions.net> 5*ef17dd6aSVivek Goyal */ 6*ef17dd6aSVivek Goyal #ifndef _LINUX_VIRTIO_PCIDEV_H 7*ef17dd6aSVivek Goyal #define _LINUX_VIRTIO_PCIDEV_H 8*ef17dd6aSVivek Goyal #include "standard-headers/linux/types.h" 9*ef17dd6aSVivek Goyal 10*ef17dd6aSVivek Goyal /** 11*ef17dd6aSVivek Goyal * enum virtio_pcidev_ops - virtual PCI device operations 12*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_RESERVED: reserved to catch errors 13*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_CFG_READ: read config space, size is 1, 2, 4 or 8; 14*ef17dd6aSVivek Goyal * the @data field should be filled in by the device (in little endian). 15*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_CFG_WRITE: write config space, size is 1, 2, 4 or 8; 16*ef17dd6aSVivek Goyal * the @data field contains the data to write (in little endian). 17*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_MMIO_READ: read BAR mem/pio, size can be variable; 18*ef17dd6aSVivek Goyal * the @data field should be filled in by the device (in little endian). 19*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_MMIO_WRITE: write BAR mem/pio, size can be variable; 20*ef17dd6aSVivek Goyal * the @data field contains the data to write (in little endian). 21*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_MMIO_MEMSET: memset MMIO, size is variable but 22*ef17dd6aSVivek Goyal * the @data field only has one byte (unlike @VIRTIO_PCIDEV_OP_MMIO_WRITE) 23*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for 24*ef17dd6aSVivek Goyal * the number 25*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports 26*ef17dd6aSVivek Goyal * the 16- or 32-bit write that would otherwise be done into memory, 27*ef17dd6aSVivek Goyal * analogous to the write messages (@VIRTIO_PCIDEV_OP_MMIO_WRITE) above 28*ef17dd6aSVivek Goyal * @VIRTIO_PCIDEV_OP_PME: Dummy message whose content is ignored (and should be 29*ef17dd6aSVivek Goyal * all zeroes) to signal the PME# pin. 30*ef17dd6aSVivek Goyal */ 31*ef17dd6aSVivek Goyal enum virtio_pcidev_ops { 32*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_RESERVED = 0, 33*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_CFG_READ, 34*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_CFG_WRITE, 35*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_MMIO_READ, 36*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_MMIO_WRITE, 37*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_MMIO_MEMSET, 38*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_INT, 39*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_MSI, 40*ef17dd6aSVivek Goyal VIRTIO_PCIDEV_OP_PME, 41*ef17dd6aSVivek Goyal }; 42*ef17dd6aSVivek Goyal 43*ef17dd6aSVivek Goyal /** 44*ef17dd6aSVivek Goyal * struct virtio_pcidev_msg - virtio PCI device operation 45*ef17dd6aSVivek Goyal * @op: the operation to do 46*ef17dd6aSVivek Goyal * @bar: the bar (only with BAR read/write messages) 47*ef17dd6aSVivek Goyal * @reserved: reserved 48*ef17dd6aSVivek Goyal * @size: the size of the read/write (in bytes) 49*ef17dd6aSVivek Goyal * @addr: the address to read/write 50*ef17dd6aSVivek Goyal * @data: the data, normally @size long, but just one byte for 51*ef17dd6aSVivek Goyal * %VIRTIO_PCIDEV_OP_MMIO_MEMSET 52*ef17dd6aSVivek Goyal * 53*ef17dd6aSVivek Goyal * Note: the fields are all in native (CPU) endian, however, the 54*ef17dd6aSVivek Goyal * @data values will often be in little endian (see the ops above.) 55*ef17dd6aSVivek Goyal */ 56*ef17dd6aSVivek Goyal struct virtio_pcidev_msg { 57*ef17dd6aSVivek Goyal uint8_t op; 58*ef17dd6aSVivek Goyal uint8_t bar; 59*ef17dd6aSVivek Goyal uint16_t reserved; 60*ef17dd6aSVivek Goyal uint32_t size; 61*ef17dd6aSVivek Goyal uint64_t addr; 62*ef17dd6aSVivek Goyal uint8_t data[]; 63*ef17dd6aSVivek Goyal }; 64*ef17dd6aSVivek Goyal 65*ef17dd6aSVivek Goyal #endif /* _LINUX_VIRTIO_PCIDEV_H */ 66