1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 33 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 34 35 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ 36 37 /* color index */ 38 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 39 40 /* 8 bpp Red */ 41 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 42 43 /* 16 bpp Red */ 44 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 45 46 /* 16 bpp RG */ 47 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 48 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 49 50 /* 32 bpp RG */ 51 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 52 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 53 54 /* 8 bpp RGB */ 55 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 56 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 57 58 /* 16 bpp RGB */ 59 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 60 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 61 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 62 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 63 64 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 65 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 66 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 67 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 68 69 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 70 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 71 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 72 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 73 74 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 75 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 76 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 77 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 78 79 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 80 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 81 82 /* 24 bpp RGB */ 83 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 84 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 85 86 /* 32 bpp RGB */ 87 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 88 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 89 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 90 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 91 92 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 93 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 94 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 95 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 96 97 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 98 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 99 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 100 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 101 102 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 103 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 104 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 105 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 106 107 /* packed YCbCr */ 108 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 109 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 110 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 111 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 112 113 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 114 115 /* 116 * 2 plane RGB + A 117 * index 0 = RGB plane, same format as the corresponding non _A8 format has 118 * index 1 = A plane, [7:0] A 119 */ 120 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 121 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 122 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 123 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 124 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 125 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 126 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 127 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 128 129 /* 130 * 2 plane YCbCr 131 * index 0 = Y plane, [7:0] Y 132 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 133 * or 134 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 135 */ 136 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 137 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 138 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 139 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 140 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 141 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 142 143 /* 144 * 3 plane YCbCr 145 * index 0: Y plane, [7:0] Y 146 * index 1: Cb plane, [7:0] Cb 147 * index 2: Cr plane, [7:0] Cr 148 * or 149 * index 1: Cr plane, [7:0] Cr 150 * index 2: Cb plane, [7:0] Cb 151 */ 152 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 153 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 154 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 155 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 156 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 157 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 158 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 159 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 160 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 161 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 162 163 164 /* 165 * Format Modifiers: 166 * 167 * Format modifiers describe, typically, a re-ordering or modification 168 * of the data in a plane of an FB. This can be used to express tiled/ 169 * swizzled formats, or compression, or a combination of the two. 170 * 171 * The upper 8 bits of the format modifier are a vendor-id as assigned 172 * below. The lower 56 bits are assigned as vendor sees fit. 173 */ 174 175 /* Vendor Ids: */ 176 #define DRM_FORMAT_MOD_NONE 0 177 #define DRM_FORMAT_MOD_VENDOR_NONE 0 178 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 179 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 180 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 181 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 182 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 183 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 184 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 185 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 186 /* add more to the end as needed */ 187 188 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 189 190 #define fourcc_mod_code(vendor, val) \ 191 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 192 193 /* 194 * Format Modifier tokens: 195 * 196 * When adding a new token please document the layout with a code comment, 197 * similar to the fourcc codes above. drm_fourcc.h is considered the 198 * authoritative source for all of these. 199 */ 200 201 /* 202 * Invalid Modifier 203 * 204 * This modifier can be used as a sentinel to terminate the format modifiers 205 * list, or to initialize a variable with an invalid modifier. It might also be 206 * used to report an error back to userspace for certain APIs. 207 */ 208 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 209 210 /* 211 * Linear Layout 212 * 213 * Just plain linear layout. Note that this is different from no specifying any 214 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 215 * which tells the driver to also take driver-internal information into account 216 * and so might actually result in a tiled framebuffer. 217 */ 218 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 219 220 /* Intel framebuffer modifiers */ 221 222 /* 223 * Intel X-tiling layout 224 * 225 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 226 * in row-major layout. Within the tile bytes are laid out row-major, with 227 * a platform-dependent stride. On top of that the memory can apply 228 * platform-depending swizzling of some higher address bits into bit6. 229 * 230 * This format is highly platforms specific and not useful for cross-driver 231 * sharing. It exists since on a given platform it does uniquely identify the 232 * layout in a simple way for i915-specific userspace. 233 */ 234 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 235 236 /* 237 * Intel Y-tiling layout 238 * 239 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 240 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 241 * chunks column-major, with a platform-dependent height. On top of that the 242 * memory can apply platform-depending swizzling of some higher address bits 243 * into bit6. 244 * 245 * This format is highly platforms specific and not useful for cross-driver 246 * sharing. It exists since on a given platform it does uniquely identify the 247 * layout in a simple way for i915-specific userspace. 248 */ 249 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 250 251 /* 252 * Intel Yf-tiling layout 253 * 254 * This is a tiled layout using 4Kb tiles in row-major layout. 255 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 256 * are arranged in four groups (two wide, two high) with column-major layout. 257 * Each group therefore consits out of four 256 byte units, which are also laid 258 * out as 2x2 column-major. 259 * 256 byte units are made out of four 64 byte blocks of pixels, producing 260 * either a square block or a 2:1 unit. 261 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 262 * in pixel depends on the pixel depth. 263 */ 264 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 265 266 /* 267 * Intel color control surface (CCS) for render compression 268 * 269 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 270 * The main surface will be plane index 0 and must be Y/Yf-tiled, 271 * the CCS will be plane index 1. 272 * 273 * Each CCS tile matches a 1024x512 pixel area of the main surface. 274 * To match certain aspects of the 3D hardware the CCS is 275 * considered to be made up of normal 128Bx32 Y tiles, Thus 276 * the CCS pitch must be specified in multiples of 128 bytes. 277 * 278 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 279 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 280 * But that fact is not relevant unless the memory is accessed 281 * directly. 282 */ 283 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 284 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 285 286 /* 287 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 288 * 289 * Macroblocks are laid in a Z-shape, and each pixel data is following the 290 * standard NV12 style. 291 * As for NV12, an image is the result of two frame buffers: one for Y, 292 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 293 * Alignment requirements are (for each buffer): 294 * - multiple of 128 pixels for the width 295 * - multiple of 32 pixels for the height 296 * 297 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 298 */ 299 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 300 301 /* 302 * Qualcomm Compressed Format 303 * 304 * Refers to a compressed variant of the base format that is compressed. 305 * Implementation may be platform and base-format specific. 306 * 307 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 308 * Pixel data pitch/stride is aligned with macrotile width. 309 * Pixel data height is aligned with macrotile height. 310 * Entire pixel data buffer is aligned with 4k(bytes). 311 */ 312 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 313 314 /* Vivante framebuffer modifiers */ 315 316 /* 317 * Vivante 4x4 tiling layout 318 * 319 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 320 * layout. 321 */ 322 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 323 324 /* 325 * Vivante 64x64 super-tiling layout 326 * 327 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 328 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 329 * major layout. 330 * 331 * For more information: see 332 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 333 */ 334 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 335 336 /* 337 * Vivante 4x4 tiling layout for dual-pipe 338 * 339 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 340 * different base address. Offsets from the base addresses are therefore halved 341 * compared to the non-split tiled layout. 342 */ 343 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 344 345 /* 346 * Vivante 64x64 super-tiling layout for dual-pipe 347 * 348 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 349 * starts at a different base address. Offsets from the base addresses are 350 * therefore halved compared to the non-split super-tiled layout. 351 */ 352 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 353 354 /* NVIDIA frame buffer modifiers */ 355 356 /* 357 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 358 * 359 * Pixels are arranged in simple tiles of 16 x 16 bytes. 360 */ 361 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 362 363 /* 364 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later 365 * 366 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 367 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 368 * 369 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 370 * 371 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 372 * Valid values are: 373 * 374 * 0 == ONE_GOB 375 * 1 == TWO_GOBS 376 * 2 == FOUR_GOBS 377 * 3 == EIGHT_GOBS 378 * 4 == SIXTEEN_GOBS 379 * 5 == THIRTYTWO_GOBS 380 * 381 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 382 * in full detail. 383 */ 384 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 385 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) 386 387 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 388 fourcc_mod_code(NVIDIA, 0x10) 389 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 390 fourcc_mod_code(NVIDIA, 0x11) 391 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 392 fourcc_mod_code(NVIDIA, 0x12) 393 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 394 fourcc_mod_code(NVIDIA, 0x13) 395 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 396 fourcc_mod_code(NVIDIA, 0x14) 397 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 398 fourcc_mod_code(NVIDIA, 0x15) 399 400 /* 401 * Some Broadcom modifiers take parameters, for example the number of 402 * vertical lines in the image. Reserve the lower 32 bits for modifier 403 * type, and the next 24 bits for parameters. Top 8 bits are the 404 * vendor code. 405 */ 406 #define __fourcc_mod_broadcom_param_shift 8 407 #define __fourcc_mod_broadcom_param_bits 48 408 #define fourcc_mod_broadcom_code(val, params) \ 409 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 410 #define fourcc_mod_broadcom_param(m) \ 411 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 412 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 413 #define fourcc_mod_broadcom_mod(m) \ 414 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 415 __fourcc_mod_broadcom_param_shift)) 416 417 /* 418 * Broadcom VC4 "T" format 419 * 420 * This is the primary layout that the V3D GPU can texture from (it 421 * can't do linear). The T format has: 422 * 423 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 424 * pixels at 32 bit depth. 425 * 426 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 427 * 16x16 pixels). 428 * 429 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 430 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 431 * they're (TR, BR, BL, TL), where bottom left is start of memory. 432 * 433 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 434 * tiles) or right-to-left (odd rows of 4k tiles). 435 */ 436 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 437 438 /* 439 * Broadcom SAND format 440 * 441 * This is the native format that the H.264 codec block uses. For VC4 442 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 443 * 444 * The image can be considered to be split into columns, and the 445 * columns are placed consecutively into memory. The width of those 446 * columns can be either 32, 64, 128, or 256 pixels, but in practice 447 * only 128 pixel columns are used. 448 * 449 * The pitch between the start of each column is set to optimally 450 * switch between SDRAM banks. This is passed as the number of lines 451 * of column width in the modifier (we can't use the stride value due 452 * to various core checks that look at it , so you should set the 453 * stride to width*cpp). 454 * 455 * Note that the column height for this format modifier is the same 456 * for all of the planes, assuming that each column contains both Y 457 * and UV. Some SAND-using hardware stores UV in a separate tiled 458 * image from Y to reduce the column height, which is not supported 459 * with these modifiers. 460 */ 461 462 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 463 fourcc_mod_broadcom_code(2, v) 464 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 465 fourcc_mod_broadcom_code(3, v) 466 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 467 fourcc_mod_broadcom_code(4, v) 468 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 469 fourcc_mod_broadcom_code(5, v) 470 471 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 472 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 473 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 474 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 475 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 476 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 477 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 478 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 479 480 /* Broadcom UIF format 481 * 482 * This is the common format for the current Broadcom multimedia 483 * blocks, including V3D 3.x and newer, newer video codecs, and 484 * displays. 485 * 486 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 487 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 488 * stored in columns, with padding between the columns to ensure that 489 * moving from one column to the next doesn't hit the same SDRAM page 490 * bank. 491 * 492 * To calculate the padding, it is assumed that each hardware block 493 * and the software driving it knows the platform's SDRAM page size, 494 * number of banks, and XOR address, and that it's identical between 495 * all blocks using the format. This tiling modifier will use XOR as 496 * necessary to reduce the padding. If a hardware block can't do XOR, 497 * the assumption is that a no-XOR tiling modifier will be created. 498 */ 499 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 500 501 /* 502 * Arm Framebuffer Compression (AFBC) modifiers 503 * 504 * AFBC is a proprietary lossless image compression protocol and format. 505 * It provides fine-grained random access and minimizes the amount of data 506 * transferred between IP blocks. 507 * 508 * AFBC has several features which may be supported and/or used, which are 509 * represented using bits in the modifier. Not all combinations are valid, 510 * and different devices or use-cases may support different combinations. 511 */ 512 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) 513 514 /* 515 * AFBC superblock size 516 * 517 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 518 * size (in pixels) must be aligned to a multiple of the superblock size. 519 * Four lowest significant bits(LSBs) are reserved for block size. 520 */ 521 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 522 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 523 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 524 525 /* 526 * AFBC lossless colorspace transform 527 * 528 * Indicates that the buffer makes use of the AFBC lossless colorspace 529 * transform. 530 */ 531 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 532 533 /* 534 * AFBC block-split 535 * 536 * Indicates that the payload of each superblock is split. The second 537 * half of the payload is positioned at a predefined offset from the start 538 * of the superblock payload. 539 */ 540 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 541 542 /* 543 * AFBC sparse layout 544 * 545 * This flag indicates that the payload of each superblock must be stored at a 546 * predefined position relative to the other superblocks in the same AFBC 547 * buffer. This order is the same order used by the header buffer. In this mode 548 * each superblock is given the same amount of space as an uncompressed 549 * superblock of the particular format would require, rounding up to the next 550 * multiple of 128 bytes in size. 551 */ 552 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 553 554 /* 555 * AFBC copy-block restrict 556 * 557 * Buffers with this flag must obey the copy-block restriction. The restriction 558 * is such that there are no copy-blocks referring across the border of 8x8 559 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 560 */ 561 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 562 563 /* 564 * AFBC tiled layout 565 * 566 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 567 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 568 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 569 * larger bpp formats. The order between the tiles is scan line. 570 * When the tiled layout is used, the buffer size (in pixels) must be aligned 571 * to the tile size. 572 */ 573 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 574 575 /* 576 * AFBC solid color blocks 577 * 578 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 579 * can be reduced if a whole superblock is a single color. 580 */ 581 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 582 583 #if defined(__cplusplus) 584 } 585 #endif 586 587 #endif /* DRM_FOURCC_H */ 588