1 /*
2  * Copyright 2011 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26 
27 
28 #if defined(__cplusplus)
29 extern "C" {
30 #endif
31 
32 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
33 				 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
34 
35 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
36 
37 /* color index */
38 #define DRM_FORMAT_C8		fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
39 
40 /* 8 bpp Red */
41 #define DRM_FORMAT_R8		fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
42 
43 /* 16 bpp Red */
44 #define DRM_FORMAT_R16		fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
45 
46 /* 16 bpp RG */
47 #define DRM_FORMAT_RG88		fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
48 #define DRM_FORMAT_GR88		fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
49 
50 /* 32 bpp RG */
51 #define DRM_FORMAT_RG1616	fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
52 #define DRM_FORMAT_GR1616	fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
53 
54 /* 8 bpp RGB */
55 #define DRM_FORMAT_RGB332	fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
56 #define DRM_FORMAT_BGR233	fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
57 
58 /* 16 bpp RGB */
59 #define DRM_FORMAT_XRGB4444	fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
60 #define DRM_FORMAT_XBGR4444	fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
61 #define DRM_FORMAT_RGBX4444	fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
62 #define DRM_FORMAT_BGRX4444	fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
63 
64 #define DRM_FORMAT_ARGB4444	fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
65 #define DRM_FORMAT_ABGR4444	fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
66 #define DRM_FORMAT_RGBA4444	fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
67 #define DRM_FORMAT_BGRA4444	fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
68 
69 #define DRM_FORMAT_XRGB1555	fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
70 #define DRM_FORMAT_XBGR1555	fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
71 #define DRM_FORMAT_RGBX5551	fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
72 #define DRM_FORMAT_BGRX5551	fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
73 
74 #define DRM_FORMAT_ARGB1555	fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
75 #define DRM_FORMAT_ABGR1555	fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
76 #define DRM_FORMAT_RGBA5551	fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
77 #define DRM_FORMAT_BGRA5551	fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
78 
79 #define DRM_FORMAT_RGB565	fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
80 #define DRM_FORMAT_BGR565	fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
81 
82 /* 24 bpp RGB */
83 #define DRM_FORMAT_RGB888	fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
84 #define DRM_FORMAT_BGR888	fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
85 
86 /* 32 bpp RGB */
87 #define DRM_FORMAT_XRGB8888	fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
88 #define DRM_FORMAT_XBGR8888	fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
89 #define DRM_FORMAT_RGBX8888	fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
90 #define DRM_FORMAT_BGRX8888	fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
91 
92 #define DRM_FORMAT_ARGB8888	fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
93 #define DRM_FORMAT_ABGR8888	fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
94 #define DRM_FORMAT_RGBA8888	fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
95 #define DRM_FORMAT_BGRA8888	fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
96 
97 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
98 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
99 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
100 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
101 
102 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
103 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
104 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
105 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
106 
107 /* packed YCbCr */
108 #define DRM_FORMAT_YUYV		fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
109 #define DRM_FORMAT_YVYU		fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
110 #define DRM_FORMAT_UYVY		fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
111 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
112 
113 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
114 
115 /*
116  * 2 plane RGB + A
117  * index 0 = RGB plane, same format as the corresponding non _A8 format has
118  * index 1 = A plane, [7:0] A
119  */
120 #define DRM_FORMAT_XRGB8888_A8	fourcc_code('X', 'R', 'A', '8')
121 #define DRM_FORMAT_XBGR8888_A8	fourcc_code('X', 'B', 'A', '8')
122 #define DRM_FORMAT_RGBX8888_A8	fourcc_code('R', 'X', 'A', '8')
123 #define DRM_FORMAT_BGRX8888_A8	fourcc_code('B', 'X', 'A', '8')
124 #define DRM_FORMAT_RGB888_A8	fourcc_code('R', '8', 'A', '8')
125 #define DRM_FORMAT_BGR888_A8	fourcc_code('B', '8', 'A', '8')
126 #define DRM_FORMAT_RGB565_A8	fourcc_code('R', '5', 'A', '8')
127 #define DRM_FORMAT_BGR565_A8	fourcc_code('B', '5', 'A', '8')
128 
129 /*
130  * 2 plane YCbCr
131  * index 0 = Y plane, [7:0] Y
132  * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
133  * or
134  * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
135  */
136 #define DRM_FORMAT_NV12		fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
137 #define DRM_FORMAT_NV21		fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
138 #define DRM_FORMAT_NV16		fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
139 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
140 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
141 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
142 
143 /*
144  * 3 plane YCbCr
145  * index 0: Y plane, [7:0] Y
146  * index 1: Cb plane, [7:0] Cb
147  * index 2: Cr plane, [7:0] Cr
148  * or
149  * index 1: Cr plane, [7:0] Cr
150  * index 2: Cb plane, [7:0] Cb
151  */
152 #define DRM_FORMAT_YUV410	fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
153 #define DRM_FORMAT_YVU410	fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
154 #define DRM_FORMAT_YUV411	fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
155 #define DRM_FORMAT_YVU411	fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
156 #define DRM_FORMAT_YUV420	fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
157 #define DRM_FORMAT_YVU420	fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
158 #define DRM_FORMAT_YUV422	fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
159 #define DRM_FORMAT_YVU422	fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
160 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
161 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
162 
163 
164 /*
165  * Format Modifiers:
166  *
167  * Format modifiers describe, typically, a re-ordering or modification
168  * of the data in a plane of an FB.  This can be used to express tiled/
169  * swizzled formats, or compression, or a combination of the two.
170  *
171  * The upper 8 bits of the format modifier are a vendor-id as assigned
172  * below.  The lower 56 bits are assigned as vendor sees fit.
173  */
174 
175 /* Vendor Ids: */
176 #define DRM_FORMAT_MOD_NONE           0
177 #define DRM_FORMAT_MOD_VENDOR_NONE    0
178 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
179 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
180 #define DRM_FORMAT_MOD_VENDOR_NVIDIA  0x03
181 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
182 #define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
183 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
184 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
185 /* add more to the end as needed */
186 
187 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
188 
189 #define fourcc_mod_code(vendor, val) \
190 	((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
191 
192 /*
193  * Format Modifier tokens:
194  *
195  * When adding a new token please document the layout with a code comment,
196  * similar to the fourcc codes above. drm_fourcc.h is considered the
197  * authoritative source for all of these.
198  */
199 
200 /*
201  * Invalid Modifier
202  *
203  * This modifier can be used as a sentinel to terminate the format modifiers
204  * list, or to initialize a variable with an invalid modifier. It might also be
205  * used to report an error back to userspace for certain APIs.
206  */
207 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
208 
209 /*
210  * Linear Layout
211  *
212  * Just plain linear layout. Note that this is different from no specifying any
213  * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
214  * which tells the driver to also take driver-internal information into account
215  * and so might actually result in a tiled framebuffer.
216  */
217 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
218 
219 /* Intel framebuffer modifiers */
220 
221 /*
222  * Intel X-tiling layout
223  *
224  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
225  * in row-major layout. Within the tile bytes are laid out row-major, with
226  * a platform-dependent stride. On top of that the memory can apply
227  * platform-depending swizzling of some higher address bits into bit6.
228  *
229  * This format is highly platforms specific and not useful for cross-driver
230  * sharing. It exists since on a given platform it does uniquely identify the
231  * layout in a simple way for i915-specific userspace.
232  */
233 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
234 
235 /*
236  * Intel Y-tiling layout
237  *
238  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
239  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
240  * chunks column-major, with a platform-dependent height. On top of that the
241  * memory can apply platform-depending swizzling of some higher address bits
242  * into bit6.
243  *
244  * This format is highly platforms specific and not useful for cross-driver
245  * sharing. It exists since on a given platform it does uniquely identify the
246  * layout in a simple way for i915-specific userspace.
247  */
248 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
249 
250 /*
251  * Intel Yf-tiling layout
252  *
253  * This is a tiled layout using 4Kb tiles in row-major layout.
254  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
255  * are arranged in four groups (two wide, two high) with column-major layout.
256  * Each group therefore consits out of four 256 byte units, which are also laid
257  * out as 2x2 column-major.
258  * 256 byte units are made out of four 64 byte blocks of pixels, producing
259  * either a square block or a 2:1 unit.
260  * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
261  * in pixel depends on the pixel depth.
262  */
263 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
264 
265 /*
266  * Intel color control surface (CCS) for render compression
267  *
268  * The framebuffer format must be one of the 8:8:8:8 RGB formats.
269  * The main surface will be plane index 0 and must be Y/Yf-tiled,
270  * the CCS will be plane index 1.
271  *
272  * Each CCS tile matches a 1024x512 pixel area of the main surface.
273  * To match certain aspects of the 3D hardware the CCS is
274  * considered to be made up of normal 128Bx32 Y tiles, Thus
275  * the CCS pitch must be specified in multiples of 128 bytes.
276  *
277  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
278  * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
279  * But that fact is not relevant unless the memory is accessed
280  * directly.
281  */
282 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
283 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
284 
285 /*
286  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
287  *
288  * Macroblocks are laid in a Z-shape, and each pixel data is following the
289  * standard NV12 style.
290  * As for NV12, an image is the result of two frame buffers: one for Y,
291  * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
292  * Alignment requirements are (for each buffer):
293  * - multiple of 128 pixels for the width
294  * - multiple of  32 pixels for the height
295  *
296  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
297  */
298 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
299 
300 /* Vivante framebuffer modifiers */
301 
302 /*
303  * Vivante 4x4 tiling layout
304  *
305  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
306  * layout.
307  */
308 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
309 
310 /*
311  * Vivante 64x64 super-tiling layout
312  *
313  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
314  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
315  * major layout.
316  *
317  * For more information: see
318  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
319  */
320 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
321 
322 /*
323  * Vivante 4x4 tiling layout for dual-pipe
324  *
325  * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
326  * different base address. Offsets from the base addresses are therefore halved
327  * compared to the non-split tiled layout.
328  */
329 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
330 
331 /*
332  * Vivante 64x64 super-tiling layout for dual-pipe
333  *
334  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
335  * starts at a different base address. Offsets from the base addresses are
336  * therefore halved compared to the non-split super-tiled layout.
337  */
338 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
339 
340 /* NVIDIA frame buffer modifiers */
341 
342 /*
343  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
344  *
345  * Pixels are arranged in simple tiles of 16 x 16 bytes.
346  */
347 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
348 
349 /*
350  * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
351  *
352  * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
353  * vertically by a power of 2 (1 to 32 GOBs) to form a block.
354  *
355  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
356  *
357  * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
358  * Valid values are:
359  *
360  * 0 == ONE_GOB
361  * 1 == TWO_GOBS
362  * 2 == FOUR_GOBS
363  * 3 == EIGHT_GOBS
364  * 4 == SIXTEEN_GOBS
365  * 5 == THIRTYTWO_GOBS
366  *
367  * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
368  * in full detail.
369  */
370 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
371 	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
372 
373 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
374 	fourcc_mod_code(NVIDIA, 0x10)
375 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
376 	fourcc_mod_code(NVIDIA, 0x11)
377 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
378 	fourcc_mod_code(NVIDIA, 0x12)
379 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
380 	fourcc_mod_code(NVIDIA, 0x13)
381 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
382 	fourcc_mod_code(NVIDIA, 0x14)
383 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
384 	fourcc_mod_code(NVIDIA, 0x15)
385 
386 /*
387  * Broadcom VC4 "T" format
388  *
389  * This is the primary layout that the V3D GPU can texture from (it
390  * can't do linear).  The T format has:
391  *
392  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
393  *   pixels at 32 bit depth.
394  *
395  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
396  *   16x16 pixels).
397  *
398  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
399  *   even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
400  *   they're (TR, BR, BL, TL), where bottom left is start of memory.
401  *
402  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
403  *   tiles) or right-to-left (odd rows of 4k tiles).
404  */
405 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
406 
407 #if defined(__cplusplus)
408 }
409 #endif
410 
411 #endif /* DRM_FOURCC_H */
412