1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifer being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Modifiers must uniquely encode buffer layout. In other words, a buffer must 61 * match only a single modifier. A modifier must not be a subset of layouts of 62 * another modifier. For instance, it's incorrect to encode pitch alignment in 63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel 64 * aligned modifier. That said, modifiers can have implicit minimal 65 * requirements. 66 * 67 * For modifiers where the combination of fourcc code and modifier can alias, 68 * a canonical pair needs to be defined and used by all drivers. Preferred 69 * combinations are also encouraged where all combinations might lead to 70 * confusion and unnecessarily reduced interoperability. An example for the 71 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts. 72 * 73 * There are two kinds of modifier users: 74 * 75 * - Kernel and user-space drivers: for drivers it's important that modifiers 76 * don't alias, otherwise two drivers might support the same format but use 77 * different aliases, preventing them from sharing buffers in an efficient 78 * format. 79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users 80 * see modifiers as opaque tokens they can check for equality and intersect. 81 * These users musn't need to know to reason about the modifier value 82 * (i.e. they are not expected to extract information out of the modifier). 83 * 84 * Vendors should document their modifier usage in as much detail as 85 * possible, to ensure maximum compatibility across devices, drivers and 86 * applications. 87 * 88 * The authoritative list of format modifier codes is found in 89 * `include/uapi/drm/drm_fourcc.h` 90 */ 91 92 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 93 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 94 95 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ 96 97 /* Reserve 0 for the invalid format specifier */ 98 #define DRM_FORMAT_INVALID 0 99 100 /* color index */ 101 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 102 103 /* 8 bpp Red */ 104 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 105 106 /* 16 bpp Red */ 107 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 108 109 /* 16 bpp RG */ 110 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 111 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 112 113 /* 32 bpp RG */ 114 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 115 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 116 117 /* 8 bpp RGB */ 118 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 119 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 120 121 /* 16 bpp RGB */ 122 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 123 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 124 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 125 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 126 127 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 128 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 129 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 130 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 131 132 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 133 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 134 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 135 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 136 137 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 138 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 139 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 140 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 141 142 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 143 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 144 145 /* 24 bpp RGB */ 146 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 147 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 148 149 /* 32 bpp RGB */ 150 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 151 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 152 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 153 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 154 155 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 156 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 157 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 158 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 159 160 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 161 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 162 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 163 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 164 165 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 166 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 167 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 168 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 169 170 /* 64 bpp RGB */ 171 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 172 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 173 174 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 175 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 176 177 /* 178 * Floating point 64bpp RGB 179 * IEEE 754-2008 binary16 half-precision float 180 * [15:0] sign:exponent:mantissa 1:5:10 181 */ 182 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ 183 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ 184 185 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ 186 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ 187 188 /* 189 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits 190 * of unused padding per component: 191 */ 192 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */ 193 194 /* packed YCbCr */ 195 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 196 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 197 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 198 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 199 200 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 201 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 202 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ 203 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ 204 205 /* 206 * packed Y2xx indicate for each component, xx valid data occupy msb 207 * 16-xx padding occupy lsb 208 */ 209 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */ 210 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */ 211 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */ 212 213 /* 214 * packed Y4xx indicate for each component, xx valid data occupy msb 215 * 16-xx padding occupy lsb except Y410 216 */ 217 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */ 218 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 219 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */ 220 221 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */ 222 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */ 223 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */ 224 225 /* 226 * packed YCbCr420 2x2 tiled formats 227 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 228 */ 229 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 230 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 231 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 232 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 233 234 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 235 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 236 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 237 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 238 239 /* 240 * 1-plane YUV 4:2:0 241 * In these formats, the component ordering is specified (Y, followed by U 242 * then V), but the exact Linear layout is undefined. 243 * These formats can only be used with a non-Linear modifier. 244 */ 245 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') 246 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') 247 248 /* 249 * 2 plane RGB + A 250 * index 0 = RGB plane, same format as the corresponding non _A8 format has 251 * index 1 = A plane, [7:0] A 252 */ 253 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 254 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 255 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 256 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 257 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 258 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 259 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 260 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 261 262 /* 263 * 2 plane YCbCr 264 * index 0 = Y plane, [7:0] Y 265 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 266 * or 267 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 268 */ 269 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 270 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 271 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 272 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 273 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 274 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 275 /* 276 * 2 plane YCbCr 277 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian 278 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian 279 */ 280 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ 281 282 /* 283 * 2 plane YCbCr MSB aligned 284 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 285 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 286 */ 287 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */ 288 289 /* 290 * 2 plane YCbCr MSB aligned 291 * index 0 = Y plane, [15:0] Y:x [10:6] little endian 292 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian 293 */ 294 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ 295 296 /* 297 * 2 plane YCbCr MSB aligned 298 * index 0 = Y plane, [15:0] Y:x [12:4] little endian 299 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian 300 */ 301 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */ 302 303 /* 304 * 2 plane YCbCr MSB aligned 305 * index 0 = Y plane, [15:0] Y little endian 306 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian 307 */ 308 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ 309 310 /* 3 plane non-subsampled (444) YCbCr 311 * 16 bits per component, but only 10 bits are used and 6 bits are padded 312 * index 0: Y plane, [15:0] Y:x [10:6] little endian 313 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian 314 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian 315 */ 316 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') 317 318 /* 3 plane non-subsampled (444) YCrCb 319 * 16 bits per component, but only 10 bits are used and 6 bits are padded 320 * index 0: Y plane, [15:0] Y:x [10:6] little endian 321 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian 322 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian 323 */ 324 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') 325 326 /* 327 * 3 plane YCbCr 328 * index 0: Y plane, [7:0] Y 329 * index 1: Cb plane, [7:0] Cb 330 * index 2: Cr plane, [7:0] Cr 331 * or 332 * index 1: Cr plane, [7:0] Cr 333 * index 2: Cb plane, [7:0] Cb 334 */ 335 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 336 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 337 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 338 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 339 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 340 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 341 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 342 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 343 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 344 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 345 346 347 /* 348 * Format Modifiers: 349 * 350 * Format modifiers describe, typically, a re-ordering or modification 351 * of the data in a plane of an FB. This can be used to express tiled/ 352 * swizzled formats, or compression, or a combination of the two. 353 * 354 * The upper 8 bits of the format modifier are a vendor-id as assigned 355 * below. The lower 56 bits are assigned as vendor sees fit. 356 */ 357 358 /* Vendor Ids: */ 359 #define DRM_FORMAT_MOD_VENDOR_NONE 0 360 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 361 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 362 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 363 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 364 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 365 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 366 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 367 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 368 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 369 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a 370 371 /* add more to the end as needed */ 372 373 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 374 375 #define fourcc_mod_code(vendor, val) \ 376 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 377 378 /* 379 * Format Modifier tokens: 380 * 381 * When adding a new token please document the layout with a code comment, 382 * similar to the fourcc codes above. drm_fourcc.h is considered the 383 * authoritative source for all of these. 384 * 385 * Generic modifier names: 386 * 387 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names 388 * for layouts which are common across multiple vendors. To preserve 389 * compatibility, in cases where a vendor-specific definition already exists and 390 * a generic name for it is desired, the common name is a purely symbolic alias 391 * and must use the same numerical value as the original definition. 392 * 393 * Note that generic names should only be used for modifiers which describe 394 * generic layouts (such as pixel re-ordering), which may have 395 * independently-developed support across multiple vendors. 396 * 397 * In future cases where a generic layout is identified before merging with a 398 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor 399 * 'NONE' could be considered. This should only be for obvious, exceptional 400 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only 401 * apply to a single vendor. 402 * 403 * Generic names should not be used for cases where multiple hardware vendors 404 * have implementations of the same standardised compression scheme (such as 405 * AFBC). In those cases, all implementations should use the same format 406 * modifier(s), reflecting the vendor of the standard. 407 */ 408 409 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE 410 411 /* 412 * Invalid Modifier 413 * 414 * This modifier can be used as a sentinel to terminate the format modifiers 415 * list, or to initialize a variable with an invalid modifier. It might also be 416 * used to report an error back to userspace for certain APIs. 417 */ 418 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 419 420 /* 421 * Linear Layout 422 * 423 * Just plain linear layout. Note that this is different from no specifying any 424 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 425 * which tells the driver to also take driver-internal information into account 426 * and so might actually result in a tiled framebuffer. 427 */ 428 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 429 430 /* 431 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead 432 * 433 * The "none" format modifier doesn't actually mean that the modifier is 434 * implicit, instead it means that the layout is linear. Whether modifiers are 435 * used is out-of-band information carried in an API-specific way (e.g. in a 436 * flag for drm_mode_fb_cmd2). 437 */ 438 #define DRM_FORMAT_MOD_NONE 0 439 440 /* Intel framebuffer modifiers */ 441 442 /* 443 * Intel X-tiling layout 444 * 445 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 446 * in row-major layout. Within the tile bytes are laid out row-major, with 447 * a platform-dependent stride. On top of that the memory can apply 448 * platform-depending swizzling of some higher address bits into bit6. 449 * 450 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 451 * On earlier platforms the is highly platforms specific and not useful for 452 * cross-driver sharing. It exists since on a given platform it does uniquely 453 * identify the layout in a simple way for i915-specific userspace, which 454 * facilitated conversion of userspace to modifiers. Additionally the exact 455 * format on some really old platforms is not known. 456 */ 457 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 458 459 /* 460 * Intel Y-tiling layout 461 * 462 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 463 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 464 * chunks column-major, with a platform-dependent height. On top of that the 465 * memory can apply platform-depending swizzling of some higher address bits 466 * into bit6. 467 * 468 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets. 469 * On earlier platforms the is highly platforms specific and not useful for 470 * cross-driver sharing. It exists since on a given platform it does uniquely 471 * identify the layout in a simple way for i915-specific userspace, which 472 * facilitated conversion of userspace to modifiers. Additionally the exact 473 * format on some really old platforms is not known. 474 */ 475 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 476 477 /* 478 * Intel Yf-tiling layout 479 * 480 * This is a tiled layout using 4Kb tiles in row-major layout. 481 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 482 * are arranged in four groups (two wide, two high) with column-major layout. 483 * Each group therefore consits out of four 256 byte units, which are also laid 484 * out as 2x2 column-major. 485 * 256 byte units are made out of four 64 byte blocks of pixels, producing 486 * either a square block or a 2:1 unit. 487 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 488 * in pixel depends on the pixel depth. 489 */ 490 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 491 492 /* 493 * Intel color control surface (CCS) for render compression 494 * 495 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 496 * The main surface will be plane index 0 and must be Y/Yf-tiled, 497 * the CCS will be plane index 1. 498 * 499 * Each CCS tile matches a 1024x512 pixel area of the main surface. 500 * To match certain aspects of the 3D hardware the CCS is 501 * considered to be made up of normal 128Bx32 Y tiles, Thus 502 * the CCS pitch must be specified in multiples of 128 bytes. 503 * 504 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 505 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 506 * But that fact is not relevant unless the memory is accessed 507 * directly. 508 */ 509 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 510 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 511 512 /* 513 * Intel color control surfaces (CCS) for Gen-12 render compression. 514 * 515 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 516 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 517 * main surface. In other words, 4 bits in CCS map to a main surface cache 518 * line pair. The main surface pitch is required to be a multiple of four 519 * Y-tile widths. 520 */ 521 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) 522 523 /* 524 * Intel color control surfaces (CCS) for Gen-12 media compression 525 * 526 * The main surface is Y-tiled and at plane index 0, the CCS is linear and 527 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in 528 * main surface. In other words, 4 bits in CCS map to a main surface cache 529 * line pair. The main surface pitch is required to be a multiple of four 530 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the 531 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, 532 * planes 2 and 3 for the respective CCS. 533 */ 534 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) 535 536 /* 537 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render 538 * compression. 539 * 540 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear 541 * and at index 1. The clear color is stored at index 2, and the pitch should 542 * be ignored. The clear color structure is 256 bits. The first 128 bits 543 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented 544 * by 32 bits. The raw clear color is consumed by the 3d engine and generates 545 * the converted clear color of size 64 bits. The first 32 bits store the Lower 546 * Converted Clear Color value and the next 32 bits store the Higher Converted 547 * Clear Color value when applicable. The Converted Clear Color values are 548 * consumed by the DE. The last 64 bits are used to store Color Discard Enable 549 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line 550 * corresponds to an area of 4x1 tiles in the main surface. The main surface 551 * pitch is required to be a multiple of 4 tile widths. 552 */ 553 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8) 554 555 /* 556 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 557 * 558 * Macroblocks are laid in a Z-shape, and each pixel data is following the 559 * standard NV12 style. 560 * As for NV12, an image is the result of two frame buffers: one for Y, 561 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 562 * Alignment requirements are (for each buffer): 563 * - multiple of 128 pixels for the width 564 * - multiple of 32 pixels for the height 565 * 566 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 567 */ 568 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 569 570 /* 571 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 572 * 573 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 574 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 575 * they correspond to their 16x16 luma block. 576 */ 577 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 578 579 /* 580 * Qualcomm Compressed Format 581 * 582 * Refers to a compressed variant of the base format that is compressed. 583 * Implementation may be platform and base-format specific. 584 * 585 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 586 * Pixel data pitch/stride is aligned with macrotile width. 587 * Pixel data height is aligned with macrotile height. 588 * Entire pixel data buffer is aligned with 4k(bytes). 589 */ 590 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 591 592 /* Vivante framebuffer modifiers */ 593 594 /* 595 * Vivante 4x4 tiling layout 596 * 597 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 598 * layout. 599 */ 600 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 601 602 /* 603 * Vivante 64x64 super-tiling layout 604 * 605 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 606 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 607 * major layout. 608 * 609 * For more information: see 610 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 611 */ 612 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 613 614 /* 615 * Vivante 4x4 tiling layout for dual-pipe 616 * 617 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 618 * different base address. Offsets from the base addresses are therefore halved 619 * compared to the non-split tiled layout. 620 */ 621 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 622 623 /* 624 * Vivante 64x64 super-tiling layout for dual-pipe 625 * 626 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 627 * starts at a different base address. Offsets from the base addresses are 628 * therefore halved compared to the non-split super-tiled layout. 629 */ 630 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 631 632 /* NVIDIA frame buffer modifiers */ 633 634 /* 635 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 636 * 637 * Pixels are arranged in simple tiles of 16 x 16 bytes. 638 */ 639 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 640 641 /* 642 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80, 643 * and Tegra GPUs starting with Tegra K1. 644 * 645 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies 646 * based on the architecture generation. GOBs themselves are then arranged in 647 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power 648 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents 649 * a block depth or height of "4"). 650 * 651 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 652 * in full detail. 653 * 654 * Macro 655 * Bits Param Description 656 * ---- ----- ----------------------------------------------------------------- 657 * 658 * 3:0 h log2(height) of each block, in GOBs. Placed here for 659 * compatibility with the existing 660 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 661 * 662 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for 663 * compatibility with the existing 664 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers. 665 * 666 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block 667 * size). Must be zero. 668 * 669 * Note there is no log2(width) parameter. Some portions of the 670 * hardware support a block width of two gobs, but it is impractical 671 * to use due to lack of support elsewhere, and has no known 672 * benefits. 673 * 674 * 11:9 - Reserved (To support 2D-array textures with variable array stride 675 * in blocks, specified via log2(tile width in blocks)). Must be 676 * zero. 677 * 678 * 19:12 k Page Kind. This value directly maps to a field in the page 679 * tables of all GPUs >= NV50. It affects the exact layout of bits 680 * in memory and can be derived from the tuple 681 * 682 * (format, GPU model, compression type, samples per pixel) 683 * 684 * Where compression type is defined below. If GPU model were 685 * implied by the format modifier, format, or memory buffer, page 686 * kind would not need to be included in the modifier itself, but 687 * since the modifier should define the layout of the associated 688 * memory buffer independent from any device or other context, it 689 * must be included here. 690 * 691 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed 692 * starting with Fermi GPUs. Additionally, the mapping between page 693 * kind and bit layout has changed at various points. 694 * 695 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping 696 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping 697 * 2 = Gob Height 8, Turing+ Page Kind mapping 698 * 3 = Reserved for future use. 699 * 700 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further 701 * bit remapping step that occurs at an even lower level than the 702 * page kind and block linear swizzles. This causes the layout of 703 * surfaces mapped in those SOC's GPUs to be incompatible with the 704 * equivalent mapping on other GPUs in the same system. 705 * 706 * 0 = Tegra K1 - Tegra Parker/TX2 Layout. 707 * 1 = Desktop GPU and Tegra Xavier+ Layout 708 * 709 * 25:23 c Lossless Framebuffer Compression type. 710 * 711 * 0 = none 712 * 1 = ROP/3D, layout 1, exact compression format implied by Page 713 * Kind field 714 * 2 = ROP/3D, layout 2, exact compression format implied by Page 715 * Kind field 716 * 3 = CDE horizontal 717 * 4 = CDE vertical 718 * 5 = Reserved for future use 719 * 6 = Reserved for future use 720 * 7 = Reserved for future use 721 * 722 * 55:25 - Reserved for future use. Must be zero. 723 */ 724 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ 725 fourcc_mod_code(NVIDIA, (0x10 | \ 726 ((h) & 0xf) | \ 727 (((k) & 0xff) << 12) | \ 728 (((g) & 0x3) << 20) | \ 729 (((s) & 0x1) << 22) | \ 730 (((c) & 0x7) << 23))) 731 732 /* To grandfather in prior block linear format modifiers to the above layout, 733 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable 734 * with block-linear layouts, is remapped within drivers to the value 0xfe, 735 * which corresponds to the "generic" kind used for simple single-sample 736 * uncompressed color formats on Fermi - Volta GPUs. 737 */ 738 static inline uint64_t 739 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) 740 { 741 if (!(modifier & 0x10) || (modifier & (0xff << 12))) 742 return modifier; 743 else 744 return modifier | (0xfe << 12); 745 } 746 747 /* 748 * 16Bx2 Block Linear layout, used by Tegra K1 and later 749 * 750 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 751 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 752 * 753 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 754 * 755 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 756 * Valid values are: 757 * 758 * 0 == ONE_GOB 759 * 1 == TWO_GOBS 760 * 2 == FOUR_GOBS 761 * 3 == EIGHT_GOBS 762 * 4 == SIXTEEN_GOBS 763 * 5 == THIRTYTWO_GOBS 764 * 765 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 766 * in full detail. 767 */ 768 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 769 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v)) 770 771 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 772 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0) 773 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 774 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1) 775 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 776 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2) 777 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 778 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3) 779 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 780 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4) 781 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 782 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5) 783 784 /* 785 * Some Broadcom modifiers take parameters, for example the number of 786 * vertical lines in the image. Reserve the lower 32 bits for modifier 787 * type, and the next 24 bits for parameters. Top 8 bits are the 788 * vendor code. 789 */ 790 #define __fourcc_mod_broadcom_param_shift 8 791 #define __fourcc_mod_broadcom_param_bits 48 792 #define fourcc_mod_broadcom_code(val, params) \ 793 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 794 #define fourcc_mod_broadcom_param(m) \ 795 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 796 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 797 #define fourcc_mod_broadcom_mod(m) \ 798 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 799 __fourcc_mod_broadcom_param_shift)) 800 801 /* 802 * Broadcom VC4 "T" format 803 * 804 * This is the primary layout that the V3D GPU can texture from (it 805 * can't do linear). The T format has: 806 * 807 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 808 * pixels at 32 bit depth. 809 * 810 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 811 * 16x16 pixels). 812 * 813 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 814 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 815 * they're (TR, BR, BL, TL), where bottom left is start of memory. 816 * 817 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 818 * tiles) or right-to-left (odd rows of 4k tiles). 819 */ 820 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 821 822 /* 823 * Broadcom SAND format 824 * 825 * This is the native format that the H.264 codec block uses. For VC4 826 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 827 * 828 * The image can be considered to be split into columns, and the 829 * columns are placed consecutively into memory. The width of those 830 * columns can be either 32, 64, 128, or 256 pixels, but in practice 831 * only 128 pixel columns are used. 832 * 833 * The pitch between the start of each column is set to optimally 834 * switch between SDRAM banks. This is passed as the number of lines 835 * of column width in the modifier (we can't use the stride value due 836 * to various core checks that look at it , so you should set the 837 * stride to width*cpp). 838 * 839 * Note that the column height for this format modifier is the same 840 * for all of the planes, assuming that each column contains both Y 841 * and UV. Some SAND-using hardware stores UV in a separate tiled 842 * image from Y to reduce the column height, which is not supported 843 * with these modifiers. 844 */ 845 846 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 847 fourcc_mod_broadcom_code(2, v) 848 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 849 fourcc_mod_broadcom_code(3, v) 850 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 851 fourcc_mod_broadcom_code(4, v) 852 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 853 fourcc_mod_broadcom_code(5, v) 854 855 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 856 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 857 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 858 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 859 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 860 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 861 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 862 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 863 864 /* Broadcom UIF format 865 * 866 * This is the common format for the current Broadcom multimedia 867 * blocks, including V3D 3.x and newer, newer video codecs, and 868 * displays. 869 * 870 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 871 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 872 * stored in columns, with padding between the columns to ensure that 873 * moving from one column to the next doesn't hit the same SDRAM page 874 * bank. 875 * 876 * To calculate the padding, it is assumed that each hardware block 877 * and the software driving it knows the platform's SDRAM page size, 878 * number of banks, and XOR address, and that it's identical between 879 * all blocks using the format. This tiling modifier will use XOR as 880 * necessary to reduce the padding. If a hardware block can't do XOR, 881 * the assumption is that a no-XOR tiling modifier will be created. 882 */ 883 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 884 885 /* 886 * Arm Framebuffer Compression (AFBC) modifiers 887 * 888 * AFBC is a proprietary lossless image compression protocol and format. 889 * It provides fine-grained random access and minimizes the amount of data 890 * transferred between IP blocks. 891 * 892 * AFBC has several features which may be supported and/or used, which are 893 * represented using bits in the modifier. Not all combinations are valid, 894 * and different devices or use-cases may support different combinations. 895 * 896 * Further information on the use of AFBC modifiers can be found in 897 * Documentation/gpu/afbc.rst 898 */ 899 900 /* 901 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific 902 * modifiers) denote the category for modifiers. Currently we have only two 903 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen 904 * different categories. 905 */ 906 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ 907 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) 908 909 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 910 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 911 912 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ 913 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) 914 915 /* 916 * AFBC superblock size 917 * 918 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 919 * size (in pixels) must be aligned to a multiple of the superblock size. 920 * Four lowest significant bits(LSBs) are reserved for block size. 921 * 922 * Where one superblock size is specified, it applies to all planes of the 923 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified, 924 * the first applies to the Luma plane and the second applies to the Chroma 925 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma). 926 * Multiple superblock sizes are only valid for multi-plane YCbCr formats. 927 */ 928 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 929 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 930 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 931 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL) 932 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL) 933 934 /* 935 * AFBC lossless colorspace transform 936 * 937 * Indicates that the buffer makes use of the AFBC lossless colorspace 938 * transform. 939 */ 940 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 941 942 /* 943 * AFBC block-split 944 * 945 * Indicates that the payload of each superblock is split. The second 946 * half of the payload is positioned at a predefined offset from the start 947 * of the superblock payload. 948 */ 949 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 950 951 /* 952 * AFBC sparse layout 953 * 954 * This flag indicates that the payload of each superblock must be stored at a 955 * predefined position relative to the other superblocks in the same AFBC 956 * buffer. This order is the same order used by the header buffer. In this mode 957 * each superblock is given the same amount of space as an uncompressed 958 * superblock of the particular format would require, rounding up to the next 959 * multiple of 128 bytes in size. 960 */ 961 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 962 963 /* 964 * AFBC copy-block restrict 965 * 966 * Buffers with this flag must obey the copy-block restriction. The restriction 967 * is such that there are no copy-blocks referring across the border of 8x8 968 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 969 */ 970 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 971 972 /* 973 * AFBC tiled layout 974 * 975 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 976 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 977 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 978 * larger bpp formats. The order between the tiles is scan line. 979 * When the tiled layout is used, the buffer size (in pixels) must be aligned 980 * to the tile size. 981 */ 982 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 983 984 /* 985 * AFBC solid color blocks 986 * 987 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 988 * can be reduced if a whole superblock is a single color. 989 */ 990 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 991 992 /* 993 * AFBC double-buffer 994 * 995 * Indicates that the buffer is allocated in a layout safe for front-buffer 996 * rendering. 997 */ 998 #define AFBC_FORMAT_MOD_DB (1ULL << 10) 999 1000 /* 1001 * AFBC buffer content hints 1002 * 1003 * Indicates that the buffer includes per-superblock content hints. 1004 */ 1005 #define AFBC_FORMAT_MOD_BCH (1ULL << 11) 1006 1007 /* AFBC uncompressed storage mode 1008 * 1009 * Indicates that the buffer is using AFBC uncompressed storage mode. 1010 * In this mode all superblock payloads in the buffer use the uncompressed 1011 * storage mode, which is usually only used for data which cannot be compressed. 1012 * The buffer layout is the same as for AFBC buffers without USM set, this only 1013 * affects the storage mode of the individual superblocks. Note that even a 1014 * buffer without USM set may use uncompressed storage mode for some or all 1015 * superblocks, USM just guarantees it for all. 1016 */ 1017 #define AFBC_FORMAT_MOD_USM (1ULL << 12) 1018 1019 /* 1020 * Arm 16x16 Block U-Interleaved modifier 1021 * 1022 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image 1023 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels 1024 * in the block are reordered. 1025 */ 1026 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ 1027 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) 1028 1029 /* 1030 * Allwinner tiled modifier 1031 * 1032 * This tiling mode is implemented by the VPU found on all Allwinner platforms, 1033 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3 1034 * planes. 1035 * 1036 * With this tiling, the luminance samples are disposed in tiles representing 1037 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels. 1038 * The pixel order in each tile is linear and the tiles are disposed linearly, 1039 * both in row-major order. 1040 */ 1041 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) 1042 1043 /* 1044 * Amlogic Video Framebuffer Compression modifiers 1045 * 1046 * Amlogic uses a proprietary lossless image compression protocol and format 1047 * for their hardware video codec accelerators, either video decoders or 1048 * video input encoders. 1049 * 1050 * It considerably reduces memory bandwidth while writing and reading 1051 * frames in memory. 1052 * 1053 * The underlying storage is considered to be 3 components, 8bit or 10-bit 1054 * per component YCbCr 420, single plane : 1055 * - DRM_FORMAT_YUV420_8BIT 1056 * - DRM_FORMAT_YUV420_10BIT 1057 * 1058 * The first 8 bits of the mode defines the layout, then the following 8 bits 1059 * defines the options changing the layout. 1060 * 1061 * Not all combinations are valid, and different SoCs may support different 1062 * combinations of layout and options. 1063 */ 1064 #define __fourcc_mod_amlogic_layout_mask 0xff 1065 #define __fourcc_mod_amlogic_options_shift 8 1066 #define __fourcc_mod_amlogic_options_mask 0xff 1067 1068 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ 1069 fourcc_mod_code(AMLOGIC, \ 1070 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ 1071 (((__options) & __fourcc_mod_amlogic_options_mask) \ 1072 << __fourcc_mod_amlogic_options_shift)) 1073 1074 /* Amlogic FBC Layouts */ 1075 1076 /* 1077 * Amlogic FBC Basic Layout 1078 * 1079 * The basic layout is composed of: 1080 * - a body content organized in 64x32 superblocks with 4096 bytes per 1081 * superblock in default mode. 1082 * - a 32 bytes per 128x64 header block 1083 * 1084 * This layout is transferrable between Amlogic SoCs supporting this modifier. 1085 */ 1086 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) 1087 1088 /* 1089 * Amlogic FBC Scatter Memory layout 1090 * 1091 * Indicates the header contains IOMMU references to the compressed 1092 * frames content to optimize memory access and layout. 1093 * 1094 * In this mode, only the header memory address is needed, thus the 1095 * content memory organization is tied to the current producer 1096 * execution and cannot be saved/dumped neither transferrable between 1097 * Amlogic SoCs supporting this modifier. 1098 * 1099 * Due to the nature of the layout, these buffers are not expected to 1100 * be accessible by the user-space clients, but only accessible by the 1101 * hardware producers and consumers. 1102 * 1103 * The user-space clients should expect a failure while trying to mmap 1104 * the DMA-BUF handle returned by the producer. 1105 */ 1106 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) 1107 1108 /* Amlogic FBC Layout Options Bit Mask */ 1109 1110 /* 1111 * Amlogic FBC Memory Saving mode 1112 * 1113 * Indicates the storage is packed when pixel size is multiple of word 1114 * boudaries, i.e. 8bit should be stored in this mode to save allocation 1115 * memory. 1116 * 1117 * This mode reduces body layout to 3072 bytes per 64x32 superblock with 1118 * the basic layout and 3200 bytes per 64x32 superblock combined with 1119 * the scatter layout. 1120 */ 1121 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) 1122 1123 /* 1124 * AMD modifiers 1125 * 1126 * Memory layout: 1127 * 1128 * without DCC: 1129 * - main surface 1130 * 1131 * with DCC & without DCC_RETILE: 1132 * - main surface in plane 0 1133 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) 1134 * 1135 * with DCC & DCC_RETILE: 1136 * - main surface in plane 0 1137 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) 1138 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) 1139 * 1140 * For multi-plane formats the above surfaces get merged into one plane for 1141 * each format plane, based on the required alignment only. 1142 * 1143 * Bits Parameter Notes 1144 * ----- ------------------------ --------------------------------------------- 1145 * 1146 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* 1147 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_* 1148 * 13 DCC 1149 * 14 DCC_RETILE 1150 * 15 DCC_PIPE_ALIGN 1151 * 16 DCC_INDEPENDENT_64B 1152 * 17 DCC_INDEPENDENT_128B 1153 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* 1154 * 20 DCC_CONSTANT_ENCODE 1155 * 23:21 PIPE_XOR_BITS Only for some chips 1156 * 26:24 BANK_XOR_BITS Only for some chips 1157 * 29:27 PACKERS Only for some chips 1158 * 32:30 RB Only for some chips 1159 * 35:33 PIPE Only for some chips 1160 * 55:36 - Reserved for future use, must be zero 1161 */ 1162 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) 1163 1164 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) 1165 1166 /* Reserve 0 for GFX8 and older */ 1167 #define AMD_FMT_MOD_TILE_VER_GFX9 1 1168 #define AMD_FMT_MOD_TILE_VER_GFX10 2 1169 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 1170 1171 /* 1172 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical 1173 * version. 1174 */ 1175 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 1176 1177 /* 1178 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has 1179 * GFX9 as canonical version. 1180 */ 1181 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 1182 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 1183 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 1184 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 1185 1186 #define AMD_FMT_MOD_DCC_BLOCK_64B 0 1187 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 1188 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 1189 1190 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 1191 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF 1192 #define AMD_FMT_MOD_TILE_SHIFT 8 1193 #define AMD_FMT_MOD_TILE_MASK 0x1F 1194 1195 /* Whether DCC compression is enabled. */ 1196 #define AMD_FMT_MOD_DCC_SHIFT 13 1197 #define AMD_FMT_MOD_DCC_MASK 0x1 1198 1199 /* 1200 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and 1201 * one which is not-aligned. 1202 */ 1203 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 1204 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 1205 1206 /* Only set if DCC_RETILE = false */ 1207 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 1208 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 1209 1210 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 1211 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 1212 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 1213 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 1214 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 1215 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 1216 1217 /* 1218 * DCC supports embedding some clear colors directly in the DCC surface. 1219 * However, on older GPUs the rendering HW ignores the embedded clear color 1220 * and prefers the driver provided color. This necessitates doing a fastclear 1221 * eliminate operation before a process transfers control. 1222 * 1223 * If this bit is set that means the fastclear eliminate is not needed for these 1224 * embeddable colors. 1225 */ 1226 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 1227 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 1228 1229 /* 1230 * The below fields are for accounting for per GPU differences. These are only 1231 * relevant for GFX9 and later and if the tile field is *_X/_T. 1232 * 1233 * PIPE_XOR_BITS = always needed 1234 * BANK_XOR_BITS = only for TILE_VER_GFX9 1235 * PACKERS = only for TILE_VER_GFX10_RBPLUS 1236 * RB = only for TILE_VER_GFX9 & DCC 1237 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) 1238 */ 1239 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 1240 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 1241 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 1242 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 1243 #define AMD_FMT_MOD_PACKERS_SHIFT 27 1244 #define AMD_FMT_MOD_PACKERS_MASK 0x7 1245 #define AMD_FMT_MOD_RB_SHIFT 30 1246 #define AMD_FMT_MOD_RB_MASK 0x7 1247 #define AMD_FMT_MOD_PIPE_SHIFT 33 1248 #define AMD_FMT_MOD_PIPE_MASK 0x7 1249 1250 #define AMD_FMT_MOD_SET(field, value) \ 1251 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) 1252 #define AMD_FMT_MOD_GET(field, value) \ 1253 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) 1254 #define AMD_FMT_MOD_CLEAR(field) \ 1255 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) 1256 1257 #if defined(__cplusplus) 1258 } 1259 #endif 1260 1261 #endif /* DRM_FOURCC_H */ 1262