1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef DRM_FOURCC_H 25 #define DRM_FOURCC_H 26 27 28 #if defined(__cplusplus) 29 extern "C" { 30 #endif 31 32 /** 33 * DOC: overview 34 * 35 * In the DRM subsystem, framebuffer pixel formats are described using the 36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the 37 * fourcc code, a Format Modifier may optionally be provided, in order to 38 * further describe the buffer's format - for example tiling or compression. 39 * 40 * Format Modifiers 41 * ---------------- 42 * 43 * Format modifiers are used in conjunction with a fourcc code, forming a 44 * unique fourcc:modifier pair. This format:modifier pair must fully define the 45 * format and data layout of the buffer, and should be the only way to describe 46 * that particular buffer. 47 * 48 * Having multiple fourcc:modifier pairs which describe the same layout should 49 * be avoided, as such aliases run the risk of different drivers exposing 50 * different names for the same data format, forcing userspace to understand 51 * that they are aliases. 52 * 53 * Format modifiers may change any property of the buffer, including the number 54 * of planes and/or the required allocation size. Format modifiers are 55 * vendor-namespaced, and as such the relationship between a fourcc code and a 56 * modifier is specific to the modifer being used. For example, some modifiers 57 * may preserve meaning - such as number of planes - from the fourcc code, 58 * whereas others may not. 59 * 60 * Vendors should document their modifier usage in as much detail as 61 * possible, to ensure maximum compatibility across devices, drivers and 62 * applications. 63 * 64 * The authoritative list of format modifier codes is found in 65 * `include/uapi/drm/drm_fourcc.h` 66 */ 67 68 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ 69 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) 70 71 #define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ 72 73 /* Reserve 0 for the invalid format specifier */ 74 #define DRM_FORMAT_INVALID 0 75 76 /* color index */ 77 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ 78 79 /* 8 bpp Red */ 80 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ 81 82 /* 16 bpp Red */ 83 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ 84 85 /* 16 bpp RG */ 86 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ 87 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ 88 89 /* 32 bpp RG */ 90 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */ 91 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */ 92 93 /* 8 bpp RGB */ 94 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ 95 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ 96 97 /* 16 bpp RGB */ 98 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ 99 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ 100 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ 101 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ 102 103 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ 104 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ 105 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ 106 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ 107 108 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ 109 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ 110 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ 111 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ 112 113 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ 114 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ 115 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ 116 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ 117 118 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ 119 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ 120 121 /* 24 bpp RGB */ 122 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ 123 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ 124 125 /* 32 bpp RGB */ 126 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ 127 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ 128 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ 129 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ 130 131 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ 132 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ 133 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ 134 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ 135 136 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ 137 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ 138 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ 139 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ 140 141 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ 142 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ 143 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ 144 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ 145 146 /* packed YCbCr */ 147 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ 148 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ 149 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ 150 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ 151 152 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ 153 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */ 154 155 /* 156 * packed YCbCr420 2x2 tiled formats 157 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile 158 */ 159 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 160 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0') 161 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */ 162 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0') 163 164 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 165 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2') 166 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */ 167 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2') 168 169 /* 170 * 2 plane RGB + A 171 * index 0 = RGB plane, same format as the corresponding non _A8 format has 172 * index 1 = A plane, [7:0] A 173 */ 174 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8') 175 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8') 176 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8') 177 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8') 178 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8') 179 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8') 180 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8') 181 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8') 182 183 /* 184 * 2 plane YCbCr 185 * index 0 = Y plane, [7:0] Y 186 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian 187 * or 188 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian 189 */ 190 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ 191 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ 192 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ 193 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ 194 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ 195 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ 196 197 /* 198 * 3 plane YCbCr 199 * index 0: Y plane, [7:0] Y 200 * index 1: Cb plane, [7:0] Cb 201 * index 2: Cr plane, [7:0] Cr 202 * or 203 * index 1: Cr plane, [7:0] Cr 204 * index 2: Cb plane, [7:0] Cb 205 */ 206 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ 207 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ 208 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ 209 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ 210 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ 211 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ 212 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ 213 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ 214 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ 215 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ 216 217 218 /* 219 * Format Modifiers: 220 * 221 * Format modifiers describe, typically, a re-ordering or modification 222 * of the data in a plane of an FB. This can be used to express tiled/ 223 * swizzled formats, or compression, or a combination of the two. 224 * 225 * The upper 8 bits of the format modifier are a vendor-id as assigned 226 * below. The lower 56 bits are assigned as vendor sees fit. 227 */ 228 229 /* Vendor Ids: */ 230 #define DRM_FORMAT_MOD_NONE 0 231 #define DRM_FORMAT_MOD_VENDOR_NONE 0 232 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 233 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 234 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 235 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 236 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 237 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 238 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 239 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 240 /* add more to the end as needed */ 241 242 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) 243 244 #define fourcc_mod_code(vendor, val) \ 245 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) 246 247 /* 248 * Format Modifier tokens: 249 * 250 * When adding a new token please document the layout with a code comment, 251 * similar to the fourcc codes above. drm_fourcc.h is considered the 252 * authoritative source for all of these. 253 */ 254 255 /* 256 * Invalid Modifier 257 * 258 * This modifier can be used as a sentinel to terminate the format modifiers 259 * list, or to initialize a variable with an invalid modifier. It might also be 260 * used to report an error back to userspace for certain APIs. 261 */ 262 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) 263 264 /* 265 * Linear Layout 266 * 267 * Just plain linear layout. Note that this is different from no specifying any 268 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), 269 * which tells the driver to also take driver-internal information into account 270 * and so might actually result in a tiled framebuffer. 271 */ 272 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) 273 274 /* Intel framebuffer modifiers */ 275 276 /* 277 * Intel X-tiling layout 278 * 279 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 280 * in row-major layout. Within the tile bytes are laid out row-major, with 281 * a platform-dependent stride. On top of that the memory can apply 282 * platform-depending swizzling of some higher address bits into bit6. 283 * 284 * This format is highly platforms specific and not useful for cross-driver 285 * sharing. It exists since on a given platform it does uniquely identify the 286 * layout in a simple way for i915-specific userspace. 287 */ 288 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) 289 290 /* 291 * Intel Y-tiling layout 292 * 293 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) 294 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) 295 * chunks column-major, with a platform-dependent height. On top of that the 296 * memory can apply platform-depending swizzling of some higher address bits 297 * into bit6. 298 * 299 * This format is highly platforms specific and not useful for cross-driver 300 * sharing. It exists since on a given platform it does uniquely identify the 301 * layout in a simple way for i915-specific userspace. 302 */ 303 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) 304 305 /* 306 * Intel Yf-tiling layout 307 * 308 * This is a tiled layout using 4Kb tiles in row-major layout. 309 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which 310 * are arranged in four groups (two wide, two high) with column-major layout. 311 * Each group therefore consits out of four 256 byte units, which are also laid 312 * out as 2x2 column-major. 313 * 256 byte units are made out of four 64 byte blocks of pixels, producing 314 * either a square block or a 2:1 unit. 315 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width 316 * in pixel depends on the pixel depth. 317 */ 318 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) 319 320 /* 321 * Intel color control surface (CCS) for render compression 322 * 323 * The framebuffer format must be one of the 8:8:8:8 RGB formats. 324 * The main surface will be plane index 0 and must be Y/Yf-tiled, 325 * the CCS will be plane index 1. 326 * 327 * Each CCS tile matches a 1024x512 pixel area of the main surface. 328 * To match certain aspects of the 3D hardware the CCS is 329 * considered to be made up of normal 128Bx32 Y tiles, Thus 330 * the CCS pitch must be specified in multiples of 128 bytes. 331 * 332 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed 333 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks. 334 * But that fact is not relevant unless the memory is accessed 335 * directly. 336 */ 337 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) 338 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) 339 340 /* 341 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 342 * 343 * Macroblocks are laid in a Z-shape, and each pixel data is following the 344 * standard NV12 style. 345 * As for NV12, an image is the result of two frame buffers: one for Y, 346 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). 347 * Alignment requirements are (for each buffer): 348 * - multiple of 128 pixels for the width 349 * - multiple of 32 pixels for the height 350 * 351 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html 352 */ 353 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) 354 355 /* 356 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks 357 * 358 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major 359 * layout. For YCbCr formats Cb/Cr components are taken in such a way that 360 * they correspond to their 16x16 luma block. 361 */ 362 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2) 363 364 /* 365 * Qualcomm Compressed Format 366 * 367 * Refers to a compressed variant of the base format that is compressed. 368 * Implementation may be platform and base-format specific. 369 * 370 * Each macrotile consists of m x n (mostly 4 x 4) tiles. 371 * Pixel data pitch/stride is aligned with macrotile width. 372 * Pixel data height is aligned with macrotile height. 373 * Entire pixel data buffer is aligned with 4k(bytes). 374 */ 375 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) 376 377 /* Vivante framebuffer modifiers */ 378 379 /* 380 * Vivante 4x4 tiling layout 381 * 382 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major 383 * layout. 384 */ 385 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1) 386 387 /* 388 * Vivante 64x64 super-tiling layout 389 * 390 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile 391 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row- 392 * major layout. 393 * 394 * For more information: see 395 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling 396 */ 397 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2) 398 399 /* 400 * Vivante 4x4 tiling layout for dual-pipe 401 * 402 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a 403 * different base address. Offsets from the base addresses are therefore halved 404 * compared to the non-split tiled layout. 405 */ 406 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3) 407 408 /* 409 * Vivante 64x64 super-tiling layout for dual-pipe 410 * 411 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile 412 * starts at a different base address. Offsets from the base addresses are 413 * therefore halved compared to the non-split super-tiled layout. 414 */ 415 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) 416 417 /* NVIDIA frame buffer modifiers */ 418 419 /* 420 * Tegra Tiled Layout, used by Tegra 2, 3 and 4. 421 * 422 * Pixels are arranged in simple tiles of 16 x 16 bytes. 423 */ 424 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) 425 426 /* 427 * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later 428 * 429 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked 430 * vertically by a power of 2 (1 to 32 GOBs) to form a block. 431 * 432 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. 433 * 434 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. 435 * Valid values are: 436 * 437 * 0 == ONE_GOB 438 * 1 == TWO_GOBS 439 * 2 == FOUR_GOBS 440 * 3 == EIGHT_GOBS 441 * 4 == SIXTEEN_GOBS 442 * 5 == THIRTYTWO_GOBS 443 * 444 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format 445 * in full detail. 446 */ 447 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ 448 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) 449 450 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ 451 fourcc_mod_code(NVIDIA, 0x10) 452 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ 453 fourcc_mod_code(NVIDIA, 0x11) 454 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ 455 fourcc_mod_code(NVIDIA, 0x12) 456 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ 457 fourcc_mod_code(NVIDIA, 0x13) 458 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ 459 fourcc_mod_code(NVIDIA, 0x14) 460 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ 461 fourcc_mod_code(NVIDIA, 0x15) 462 463 /* 464 * Some Broadcom modifiers take parameters, for example the number of 465 * vertical lines in the image. Reserve the lower 32 bits for modifier 466 * type, and the next 24 bits for parameters. Top 8 bits are the 467 * vendor code. 468 */ 469 #define __fourcc_mod_broadcom_param_shift 8 470 #define __fourcc_mod_broadcom_param_bits 48 471 #define fourcc_mod_broadcom_code(val, params) \ 472 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val)) 473 #define fourcc_mod_broadcom_param(m) \ 474 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \ 475 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1))) 476 #define fourcc_mod_broadcom_mod(m) \ 477 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \ 478 __fourcc_mod_broadcom_param_shift)) 479 480 /* 481 * Broadcom VC4 "T" format 482 * 483 * This is the primary layout that the V3D GPU can texture from (it 484 * can't do linear). The T format has: 485 * 486 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4 487 * pixels at 32 bit depth. 488 * 489 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually 490 * 16x16 pixels). 491 * 492 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On 493 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows 494 * they're (TR, BR, BL, TL), where bottom left is start of memory. 495 * 496 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k 497 * tiles) or right-to-left (odd rows of 4k tiles). 498 */ 499 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1) 500 501 /* 502 * Broadcom SAND format 503 * 504 * This is the native format that the H.264 codec block uses. For VC4 505 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes. 506 * 507 * The image can be considered to be split into columns, and the 508 * columns are placed consecutively into memory. The width of those 509 * columns can be either 32, 64, 128, or 256 pixels, but in practice 510 * only 128 pixel columns are used. 511 * 512 * The pitch between the start of each column is set to optimally 513 * switch between SDRAM banks. This is passed as the number of lines 514 * of column width in the modifier (we can't use the stride value due 515 * to various core checks that look at it , so you should set the 516 * stride to width*cpp). 517 * 518 * Note that the column height for this format modifier is the same 519 * for all of the planes, assuming that each column contains both Y 520 * and UV. Some SAND-using hardware stores UV in a separate tiled 521 * image from Y to reduce the column height, which is not supported 522 * with these modifiers. 523 */ 524 525 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ 526 fourcc_mod_broadcom_code(2, v) 527 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ 528 fourcc_mod_broadcom_code(3, v) 529 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ 530 fourcc_mod_broadcom_code(4, v) 531 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ 532 fourcc_mod_broadcom_code(5, v) 533 534 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \ 535 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0) 536 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \ 537 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0) 538 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \ 539 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0) 540 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \ 541 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0) 542 543 /* Broadcom UIF format 544 * 545 * This is the common format for the current Broadcom multimedia 546 * blocks, including V3D 3.x and newer, newer video codecs, and 547 * displays. 548 * 549 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles), 550 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are 551 * stored in columns, with padding between the columns to ensure that 552 * moving from one column to the next doesn't hit the same SDRAM page 553 * bank. 554 * 555 * To calculate the padding, it is assumed that each hardware block 556 * and the software driving it knows the platform's SDRAM page size, 557 * number of banks, and XOR address, and that it's identical between 558 * all blocks using the format. This tiling modifier will use XOR as 559 * necessary to reduce the padding. If a hardware block can't do XOR, 560 * the assumption is that a no-XOR tiling modifier will be created. 561 */ 562 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) 563 564 /* 565 * Arm Framebuffer Compression (AFBC) modifiers 566 * 567 * AFBC is a proprietary lossless image compression protocol and format. 568 * It provides fine-grained random access and minimizes the amount of data 569 * transferred between IP blocks. 570 * 571 * AFBC has several features which may be supported and/or used, which are 572 * represented using bits in the modifier. Not all combinations are valid, 573 * and different devices or use-cases may support different combinations. 574 */ 575 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) 576 577 /* 578 * AFBC superblock size 579 * 580 * Indicates the superblock size(s) used for the AFBC buffer. The buffer 581 * size (in pixels) must be aligned to a multiple of the superblock size. 582 * Four lowest significant bits(LSBs) are reserved for block size. 583 */ 584 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf 585 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL) 586 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL) 587 588 /* 589 * AFBC lossless colorspace transform 590 * 591 * Indicates that the buffer makes use of the AFBC lossless colorspace 592 * transform. 593 */ 594 #define AFBC_FORMAT_MOD_YTR (1ULL << 4) 595 596 /* 597 * AFBC block-split 598 * 599 * Indicates that the payload of each superblock is split. The second 600 * half of the payload is positioned at a predefined offset from the start 601 * of the superblock payload. 602 */ 603 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5) 604 605 /* 606 * AFBC sparse layout 607 * 608 * This flag indicates that the payload of each superblock must be stored at a 609 * predefined position relative to the other superblocks in the same AFBC 610 * buffer. This order is the same order used by the header buffer. In this mode 611 * each superblock is given the same amount of space as an uncompressed 612 * superblock of the particular format would require, rounding up to the next 613 * multiple of 128 bytes in size. 614 */ 615 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6) 616 617 /* 618 * AFBC copy-block restrict 619 * 620 * Buffers with this flag must obey the copy-block restriction. The restriction 621 * is such that there are no copy-blocks referring across the border of 8x8 622 * blocks. For the subsampled data the 8x8 limitation is also subsampled. 623 */ 624 #define AFBC_FORMAT_MOD_CBR (1ULL << 7) 625 626 /* 627 * AFBC tiled layout 628 * 629 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all 630 * superblocks inside a tile are stored together in memory. 8x8 tiles are used 631 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for 632 * larger bpp formats. The order between the tiles is scan line. 633 * When the tiled layout is used, the buffer size (in pixels) must be aligned 634 * to the tile size. 635 */ 636 #define AFBC_FORMAT_MOD_TILED (1ULL << 8) 637 638 /* 639 * AFBC solid color blocks 640 * 641 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth 642 * can be reduced if a whole superblock is a single color. 643 */ 644 #define AFBC_FORMAT_MOD_SC (1ULL << 9) 645 646 #if defined(__cplusplus) 647 } 648 #endif 649 650 #endif /* DRM_FOURCC_H */ 651