1 /* 2 * QEMU Xen PVH machine - common code. 3 * 4 * Copyright (c) 2024 Advanced Micro Devices, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef XEN_PVH_COMMON_H__ 10 #define XEN_PVH_COMMON_H__ 11 12 #include <assert.h> 13 #include "hw/sysbus.h" 14 #include "hw/hw.h" 15 #include "hw/xen/xen-hvm-common.h" 16 #include "hw/pci-host/gpex.h" 17 18 #define TYPE_XEN_PVH_MACHINE MACHINE_TYPE_NAME("xen-pvh-base") 19 OBJECT_DECLARE_TYPE(XenPVHMachineState, XenPVHMachineClass, 20 XEN_PVH_MACHINE) 21 22 struct XenPVHMachineClass { 23 MachineClass parent; 24 25 /* PVH implementation specific init. */ 26 void (*init)(MachineState *state); 27 28 /* 29 * set_pci_intx_irq - Deliver INTX irqs to the guest. 30 * 31 * @opaque: pointer to XenPVHMachineState. 32 * @irq: IRQ after swizzling, between 0-3. 33 * @level: IRQ level. 34 */ 35 void (*set_pci_intx_irq)(void *opaque, int irq, int level); 36 37 /* 38 * set_pci_link_route: - optional implementation call to setup 39 * routing between INTX IRQ (0 - 3) and GSI's. 40 * 41 * @line: line the INTx line (0 => A .. 3 => B) 42 * @irq: GSI 43 */ 44 int (*set_pci_link_route)(uint8_t line, uint8_t irq); 45 46 /* 47 * Each implementation can optionally enable features that it 48 * supports and are known to work. 49 */ 50 bool has_pci; 51 bool has_tpm; 52 bool has_virtio_mmio; 53 }; 54 55 struct XenPVHMachineState { 56 /*< private >*/ 57 MachineState parent; 58 59 XenIOState ioreq; 60 61 struct { 62 MemoryRegion low; 63 MemoryRegion high; 64 } ram; 65 66 struct { 67 GPEXHost gpex; 68 MemoryRegion mmio_alias; 69 MemoryRegion mmio_high_alias; 70 } pci; 71 72 struct { 73 MemMapEntry ram_low, ram_high; 74 MemMapEntry tpm; 75 76 /* Virtio-mmio */ 77 MemMapEntry virtio_mmio; 78 uint32_t virtio_mmio_num; 79 uint32_t virtio_mmio_irq_base; 80 81 /* PCI */ 82 MemMapEntry pci_ecam, pci_mmio, pci_mmio_high; 83 uint32_t pci_intx_irq_base; 84 } cfg; 85 }; 86 87 void xen_pvh_class_setup_common_props(XenPVHMachineClass *xpc); 88 #endif 89