1 /* SPDX-License-Identifier: MIT */
2 /******************************************************************************
3  * arch-x86/cpuid.h
4  *
5  * CPUID interface to Xen.
6  *
7  * Copyright (c) 2007 Citrix Systems, Inc.
8  *
9  * Authors:
10  *    Keir Fraser <keir@xen.org>
11  */
12 
13 #ifndef __XEN_PUBLIC_ARCH_X86_CPUID_H__
14 #define __XEN_PUBLIC_ARCH_X86_CPUID_H__
15 
16 /*
17  * For compatibility with other hypervisor interfaces, the Xen cpuid leaves
18  * can be found at the first otherwise unused 0x100 aligned boundary starting
19  * from 0x40000000.
20  *
21  * e.g If viridian extensions are enabled for an HVM domain, the Xen cpuid
22  * leaves will start at 0x40000100
23  */
24 
25 #define XEN_CPUID_FIRST_LEAF 0x40000000
26 #define XEN_CPUID_LEAF(i)    (XEN_CPUID_FIRST_LEAF + (i))
27 
28 /*
29  * Leaf 1 (0x40000x00)
30  * EAX: Largest Xen-information leaf. All leaves up to an including @EAX
31  *      are supported by the Xen host.
32  * EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification
33  *      of a Xen host.
34  */
35 #define XEN_CPUID_SIGNATURE_EBX 0x566e6558 /* "XenV" */
36 #define XEN_CPUID_SIGNATURE_ECX 0x65584d4d /* "MMXe" */
37 #define XEN_CPUID_SIGNATURE_EDX 0x4d4d566e /* "nVMM" */
38 
39 /*
40  * Leaf 2 (0x40000x01)
41  * EAX[31:16]: Xen major version.
42  * EAX[15: 0]: Xen minor version.
43  * EBX-EDX: Reserved (currently all zeroes).
44  */
45 
46 /*
47  * Leaf 3 (0x40000x02)
48  * EAX: Number of hypercall transfer pages. This register is always guaranteed
49  *      to specify one hypercall page.
50  * EBX: Base address of Xen-specific MSRs.
51  * ECX: Features 1. Unused bits are set to zero.
52  * EDX: Features 2. Unused bits are set to zero.
53  */
54 
55 /* Does the host support MMU_PT_UPDATE_PRESERVE_AD for this guest? */
56 #define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
57 #define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD  (1u<<0)
58 
59 /*
60  * Leaf 4 (0x40000x03)
61  * Sub-leaf 0: EAX: bit 0: emulated tsc
62  *                  bit 1: host tsc is known to be reliable
63  *                  bit 2: RDTSCP instruction available
64  *             EBX: tsc_mode: 0=default (emulate if necessary), 1=emulate,
65  *                            2=no emulation, 3=no emulation + TSC_AUX support
66  *             ECX: guest tsc frequency in kHz
67  *             EDX: guest tsc incarnation (migration count)
68  * Sub-leaf 1: EAX: tsc offset low part
69  *             EBX: tsc offset high part
70  *             ECX: multiplicator for tsc->ns conversion
71  *             EDX: shift amount for tsc->ns conversion
72  * Sub-leaf 2: EAX: host tsc frequency in kHz
73  */
74 
75 /*
76  * Leaf 5 (0x40000x04)
77  * HVM-specific features
78  * Sub-leaf 0: EAX: Features
79  * Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag)
80  * Sub-leaf 0: ECX: domain id (iff EAX has XEN_HVM_CPUID_DOMID_PRESENT flag)
81  */
82 #define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */
83 #define XEN_HVM_CPUID_X2APIC_VIRT      (1u << 1) /* Virtualized x2APIC accesses */
84 /* Memory mapped from other domains has valid IOMMU entries */
85 #define XEN_HVM_CPUID_IOMMU_MAPPINGS   (1u << 2)
86 #define XEN_HVM_CPUID_VCPU_ID_PRESENT  (1u << 3) /* vcpu id is present in EBX */
87 #define XEN_HVM_CPUID_DOMID_PRESENT    (1u << 4) /* domid is present in ECX */
88 /*
89  * With interrupt format set to 0 (non-remappable) bits 55:49 from the
90  * IO-APIC RTE and bits 11:5 from the MSI address can be used to store
91  * high bits for the Destination ID. This expands the Destination ID
92  * field from 8 to 15 bits, allowing to target APIC IDs up 32768.
93  */
94 #define XEN_HVM_CPUID_EXT_DEST_ID      (1u << 5)
95 /*
96  * Per-vCPU event channel upcalls work correctly with physical IRQs
97  * bound to event channels.
98  */
99 #define XEN_HVM_CPUID_UPCALL_VECTOR    (1u << 6)
100 
101 /*
102  * Leaf 6 (0x40000x05)
103  * PV-specific parameters
104  * Sub-leaf 0: EAX: max available sub-leaf
105  * Sub-leaf 0: EBX: bits 0-7: max machine address width
106  */
107 
108 /* Max. address width in bits taking memory hotplug into account. */
109 #define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0)
110 
111 #define XEN_CPUID_MAX_NUM_LEAVES 5
112 
113 #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
114