137f95959SGuenter Roeck /* 237f95959SGuenter Roeck * Copyright (c) 2017, Impinj, Inc. 337f95959SGuenter Roeck * 437f95959SGuenter Roeck * i.MX2 Watchdog IP block 537f95959SGuenter Roeck * 637f95959SGuenter Roeck * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 737f95959SGuenter Roeck * 837f95959SGuenter Roeck * This work is licensed under the terms of the GNU GPL, version 2 or later. 937f95959SGuenter Roeck * See the COPYING file in the top-level directory. 1037f95959SGuenter Roeck */ 1137f95959SGuenter Roeck 1237f95959SGuenter Roeck #ifndef IMX2_WDT_H 1337f95959SGuenter Roeck #define IMX2_WDT_H 1437f95959SGuenter Roeck 15daca13d4SGuenter Roeck #include "qemu/bitops.h" 1637f95959SGuenter Roeck #include "hw/sysbus.h" 17daca13d4SGuenter Roeck #include "hw/irq.h" 18daca13d4SGuenter Roeck #include "hw/ptimer.h" 19*db1015e9SEduardo Habkost #include "qom/object.h" 2037f95959SGuenter Roeck 2137f95959SGuenter Roeck #define TYPE_IMX2_WDT "imx2.wdt" 22*db1015e9SEduardo Habkost typedef struct IMX2WdtState IMX2WdtState; 2337f95959SGuenter Roeck #define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT) 2437f95959SGuenter Roeck 2537f95959SGuenter Roeck enum IMX2WdtRegisters { 26daca13d4SGuenter Roeck IMX2_WDT_WCR = 0x0000, /* Control Register */ 27daca13d4SGuenter Roeck IMX2_WDT_WSR = 0x0002, /* Service Register */ 28daca13d4SGuenter Roeck IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */ 29daca13d4SGuenter Roeck IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */ 30daca13d4SGuenter Roeck IMX2_WDT_WMCR = 0x0008, /* Misc Register */ 3137f95959SGuenter Roeck }; 3237f95959SGuenter Roeck 33daca13d4SGuenter Roeck #define IMX2_WDT_MMIO_SIZE 0x000a 34daca13d4SGuenter Roeck 35daca13d4SGuenter Roeck /* Control Register definitions */ 36daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */ 37daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */ 38daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */ 39daca13d4SGuenter Roeck #define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */ 40daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */ 41daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */ 42daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */ 43daca13d4SGuenter Roeck #define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */ 44daca13d4SGuenter Roeck 45daca13d4SGuenter Roeck #define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \ 46daca13d4SGuenter Roeck | IMX2_WDT_WCR_WDW) 47daca13d4SGuenter Roeck 48daca13d4SGuenter Roeck /* Service Register definitions */ 49daca13d4SGuenter Roeck #define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */ 50daca13d4SGuenter Roeck #define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */ 51daca13d4SGuenter Roeck 52daca13d4SGuenter Roeck /* Reset Status Register definitions */ 53daca13d4SGuenter Roeck #define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */ 54daca13d4SGuenter Roeck #define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */ 55daca13d4SGuenter Roeck 56daca13d4SGuenter Roeck /* Interrupt Control Register definitions */ 57daca13d4SGuenter Roeck #define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */ 58daca13d4SGuenter Roeck #define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */ 59daca13d4SGuenter Roeck #define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */ 60daca13d4SGuenter Roeck #define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */ 61daca13d4SGuenter Roeck 62daca13d4SGuenter Roeck #define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT) 63daca13d4SGuenter Roeck 64daca13d4SGuenter Roeck /* Misc Control Register definitions */ 65daca13d4SGuenter Roeck #define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */ 6637f95959SGuenter Roeck 67*db1015e9SEduardo Habkost struct IMX2WdtState { 6837f95959SGuenter Roeck /* <private> */ 6937f95959SGuenter Roeck SysBusDevice parent_obj; 7037f95959SGuenter Roeck 71daca13d4SGuenter Roeck /*< public >*/ 7237f95959SGuenter Roeck MemoryRegion mmio; 73daca13d4SGuenter Roeck qemu_irq irq; 74daca13d4SGuenter Roeck 75daca13d4SGuenter Roeck struct ptimer_state *timer; 76daca13d4SGuenter Roeck struct ptimer_state *itimer; 77daca13d4SGuenter Roeck 78daca13d4SGuenter Roeck bool pretimeout_support; 79daca13d4SGuenter Roeck bool wicr_locked; 80daca13d4SGuenter Roeck 81daca13d4SGuenter Roeck uint16_t wcr; 82daca13d4SGuenter Roeck uint16_t wsr; 83daca13d4SGuenter Roeck uint16_t wrsr; 84daca13d4SGuenter Roeck uint16_t wicr; 85daca13d4SGuenter Roeck uint16_t wmcr; 86daca13d4SGuenter Roeck 87daca13d4SGuenter Roeck bool wcr_locked; /* affects WDZST, WDBG, and WDW */ 88daca13d4SGuenter Roeck bool wcr_wde_locked; /* affects WDE */ 89daca13d4SGuenter Roeck bool wcr_wdt_locked; /* affects WDT (never cleared) */ 90*db1015e9SEduardo Habkost }; 9137f95959SGuenter Roeck 9237f95959SGuenter Roeck #endif /* IMX2_WDT_H */ 93