xref: /openbmc/qemu/include/hw/watchdog/wdt_aspeed.h (revision ddda3748)
1 /*
2  * ASPEED Watchdog Controller
3  *
4  * Copyright (C) 2016-2017 IBM Corp.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #ifndef WDT_ASPEED_H
11 #define WDT_ASPEED_H
12 
13 #include "hw/misc/aspeed_scu.h"
14 #include "hw/sysbus.h"
15 
16 #define TYPE_ASPEED_WDT "aspeed.wdt"
17 #define ASPEED_WDT(obj) \
18     OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
19 #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
20 #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
21 #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
22 
23 #define ASPEED_WDT_REGS_MAX        (0x20 / 4)
24 
25 typedef struct AspeedWDTState {
26     /*< private >*/
27     SysBusDevice parent_obj;
28     QEMUTimer *timer;
29 
30     /*< public >*/
31     MemoryRegion iomem;
32     uint32_t regs[ASPEED_WDT_REGS_MAX];
33 
34     AspeedSCUState *scu;
35     uint32_t pclk_freq;
36 } AspeedWDTState;
37 
38 #define ASPEED_WDT_CLASS(klass) \
39      OBJECT_CLASS_CHECK(AspeedWDTClass, (klass), TYPE_ASPEED_WDT)
40 #define ASPEED_WDT_GET_CLASS(obj) \
41      OBJECT_GET_CLASS(AspeedWDTClass, (obj), TYPE_ASPEED_WDT)
42 
43 typedef struct AspeedWDTClass {
44     SysBusDeviceClass parent_class;
45 
46     uint32_t offset;
47     uint32_t ext_pulse_width_mask;
48     uint32_t reset_ctrl_reg;
49     void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
50     void (*wdt_reload)(AspeedWDTState *s);
51 }  AspeedWDTClass;
52 
53 #endif /* WDT_ASPEED_H */
54