1 /* 2 * ASPEED Watchdog Controller 3 * 4 * Copyright (C) 2016-2017 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef WDT_ASPEED_H 11 #define WDT_ASPEED_H 12 13 #include "hw/misc/aspeed_scu.h" 14 #include "hw/sysbus.h" 15 #include "qom/object.h" 16 17 #define TYPE_ASPEED_WDT "aspeed.wdt" 18 OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT) 19 #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" 20 #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" 21 #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" 22 #define TYPE_ASPEED_2700_WDT TYPE_ASPEED_WDT "-ast2700" 23 #define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030" 24 25 #define ASPEED_WDT_REGS_MAX (0x80 / 4) 26 27 struct AspeedWDTState { 28 /*< private >*/ 29 SysBusDevice parent_obj; 30 QEMUTimer *timer; 31 32 /*< public >*/ 33 MemoryRegion iomem_container; 34 MemoryRegion iomem; 35 uint32_t regs[ASPEED_WDT_REGS_MAX]; 36 37 AspeedSCUState *scu; 38 uint32_t pclk_freq; 39 }; 40 41 42 struct AspeedWDTClass { 43 SysBusDeviceClass parent_class; 44 45 uint32_t iosize; 46 uint32_t ext_pulse_width_mask; 47 uint32_t reset_ctrl_reg; 48 void (*reset_pulse)(AspeedWDTState *s, uint32_t property); 49 void (*wdt_reload)(AspeedWDTState *s); 50 uint64_t (*sanitize_ctrl)(uint64_t data); 51 uint32_t default_status; 52 uint32_t default_reload_value; 53 }; 54 55 #endif /* WDT_ASPEED_H */ 56