xref: /openbmc/qemu/include/hw/watchdog/wdt_aspeed.h (revision 2df1eb27)
1 /*
2  * ASPEED Watchdog Controller
3  *
4  * Copyright (C) 2016-2017 IBM Corp.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #ifndef WDT_ASPEED_H
11 #define WDT_ASPEED_H
12 
13 #include "hw/misc/aspeed_scu.h"
14 #include "hw/sysbus.h"
15 #include "qom/object.h"
16 
17 #define TYPE_ASPEED_WDT "aspeed.wdt"
18 OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
19 #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
20 #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
21 #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
22 #define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
23 
24 #define ASPEED_WDT_REGS_MAX        (0x30 / 4)
25 
26 struct AspeedWDTState {
27     /*< private >*/
28     SysBusDevice parent_obj;
29     QEMUTimer *timer;
30 
31     /*< public >*/
32     MemoryRegion iomem;
33     uint32_t regs[ASPEED_WDT_REGS_MAX];
34 
35     AspeedSCUState *scu;
36     uint32_t pclk_freq;
37 };
38 
39 
40 struct AspeedWDTClass {
41     SysBusDeviceClass parent_class;
42 
43     uint32_t iosize;
44     uint32_t ext_pulse_width_mask;
45     uint32_t reset_ctrl_reg;
46     void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
47     void (*wdt_reload)(AspeedWDTState *s);
48     uint64_t (*sanitize_ctrl)(uint64_t data);
49     uint32_t default_status;
50     uint32_t default_reload_value;
51 };
52 
53 #endif /* WDT_ASPEED_H */
54