1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #ifndef HW_VIRTIO_GPU_H 15 #define HW_VIRTIO_GPU_H 16 17 #include "qemu/queue.h" 18 #include "ui/qemu-pixman.h" 19 #include "ui/console.h" 20 #include "hw/virtio/virtio.h" 21 #include "qemu/log.h" 22 #include "sysemu/vhost-user-backend.h" 23 24 #include "standard-headers/linux/virtio_gpu.h" 25 #include "qom/object.h" 26 27 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base" 28 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass, 29 VIRTIO_GPU_BASE) 30 31 #define TYPE_VIRTIO_GPU "virtio-gpu-device" 32 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU) 33 34 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device" 35 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL) 36 37 #define TYPE_VHOST_USER_GPU "vhost-user-gpu" 38 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU) 39 40 #define VIRTIO_ID_GPU 16 41 42 struct virtio_gpu_simple_resource { 43 uint32_t resource_id; 44 uint32_t width; 45 uint32_t height; 46 uint32_t format; 47 uint64_t *addrs; 48 struct iovec *iov; 49 unsigned int iov_cnt; 50 uint32_t scanout_bitmask; 51 pixman_image_t *image; 52 uint64_t hostmem; 53 QTAILQ_ENTRY(virtio_gpu_simple_resource) next; 54 }; 55 56 struct virtio_gpu_scanout { 57 QemuConsole *con; 58 DisplaySurface *ds; 59 uint32_t width, height; 60 int x, y; 61 int invalidate; 62 uint32_t resource_id; 63 struct virtio_gpu_update_cursor cursor; 64 QEMUCursor *current_cursor; 65 }; 66 67 struct virtio_gpu_requested_state { 68 uint16_t width_mm, height_mm; 69 uint32_t width, height; 70 int x, y; 71 }; 72 73 enum virtio_gpu_base_conf_flags { 74 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1, 75 VIRTIO_GPU_FLAG_STATS_ENABLED, 76 VIRTIO_GPU_FLAG_EDID_ENABLED, 77 VIRTIO_GPU_FLAG_DMABUF_ENABLED, 78 }; 79 80 #define virtio_gpu_virgl_enabled(_cfg) \ 81 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED)) 82 #define virtio_gpu_stats_enabled(_cfg) \ 83 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED)) 84 #define virtio_gpu_edid_enabled(_cfg) \ 85 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED)) 86 #define virtio_gpu_dmabuf_enabled(_cfg) \ 87 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED)) 88 89 struct virtio_gpu_base_conf { 90 uint32_t max_outputs; 91 uint32_t flags; 92 uint32_t xres; 93 uint32_t yres; 94 }; 95 96 struct virtio_gpu_ctrl_command { 97 VirtQueueElement elem; 98 VirtQueue *vq; 99 struct virtio_gpu_ctrl_hdr cmd_hdr; 100 uint32_t error; 101 bool finished; 102 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next; 103 }; 104 105 struct VirtIOGPUBase { 106 VirtIODevice parent_obj; 107 108 Error *migration_blocker; 109 110 struct virtio_gpu_base_conf conf; 111 struct virtio_gpu_config virtio_config; 112 const GraphicHwOps *hw_ops; 113 114 int renderer_blocked; 115 int enable; 116 117 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS]; 118 119 int enabled_output_bitmask; 120 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS]; 121 }; 122 123 struct VirtIOGPUBaseClass { 124 VirtioDeviceClass parent; 125 126 void (*gl_flushed)(VirtIOGPUBase *g); 127 }; 128 129 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \ 130 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \ 131 DEFINE_PROP_BIT("edid", _state, _conf.flags, \ 132 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \ 133 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1024), \ 134 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 768) 135 136 struct VirtIOGPU { 137 VirtIOGPUBase parent_obj; 138 139 uint64_t conf_max_hostmem; 140 141 VirtQueue *ctrl_vq; 142 VirtQueue *cursor_vq; 143 144 QEMUBH *ctrl_bh; 145 QEMUBH *cursor_bh; 146 147 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist; 148 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq; 149 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq; 150 151 uint64_t hostmem; 152 153 bool processing_cmdq; 154 QEMUTimer *fence_poll; 155 QEMUTimer *print_stats; 156 157 uint32_t inflight; 158 struct { 159 uint32_t max_inflight; 160 uint32_t requests; 161 uint32_t req_3d; 162 uint32_t bytes_3d; 163 } stats; 164 }; 165 166 struct VirtIOGPUClass { 167 VirtIOGPUBaseClass parent; 168 169 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq); 170 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 171 void (*update_cursor_data)(VirtIOGPU *g, 172 struct virtio_gpu_scanout *s, 173 uint32_t resource_id); 174 }; 175 176 struct VirtIOGPUGL { 177 struct VirtIOGPU parent_obj; 178 179 bool renderer_inited; 180 bool renderer_reset; 181 }; 182 183 struct VhostUserGPU { 184 VirtIOGPUBase parent_obj; 185 186 VhostUserBackend *vhost; 187 int vhost_gpu_fd; /* closed by the chardev */ 188 CharBackend vhost_chr; 189 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS]; 190 bool backend_blocked; 191 }; 192 193 #define VIRTIO_GPU_FILL_CMD(out) do { \ 194 size_t s; \ 195 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \ 196 &out, sizeof(out)); \ 197 if (s != sizeof(out)) { \ 198 qemu_log_mask(LOG_GUEST_ERROR, \ 199 "%s: command size incorrect %zu vs %zu\n", \ 200 __func__, s, sizeof(out)); \ 201 return; \ 202 } \ 203 } while (0) 204 205 /* virtio-gpu-base.c */ 206 bool virtio_gpu_base_device_realize(DeviceState *qdev, 207 VirtIOHandleOutput ctrl_cb, 208 VirtIOHandleOutput cursor_cb, 209 Error **errp); 210 void virtio_gpu_base_reset(VirtIOGPUBase *g); 211 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, 212 struct virtio_gpu_resp_display_info *dpy_info); 213 214 /* virtio-gpu.c */ 215 void virtio_gpu_ctrl_response(VirtIOGPU *g, 216 struct virtio_gpu_ctrl_command *cmd, 217 struct virtio_gpu_ctrl_hdr *resp, 218 size_t resp_len); 219 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g, 220 struct virtio_gpu_ctrl_command *cmd, 221 enum virtio_gpu_ctrl_type type); 222 void virtio_gpu_get_display_info(VirtIOGPU *g, 223 struct virtio_gpu_ctrl_command *cmd); 224 void virtio_gpu_get_edid(VirtIOGPU *g, 225 struct virtio_gpu_ctrl_command *cmd); 226 int virtio_gpu_create_mapping_iov(VirtIOGPU *g, 227 struct virtio_gpu_resource_attach_backing *ab, 228 struct virtio_gpu_ctrl_command *cmd, 229 uint64_t **addr, struct iovec **iov, 230 uint32_t *niov); 231 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, 232 struct iovec *iov, uint32_t count); 233 void virtio_gpu_process_cmdq(VirtIOGPU *g); 234 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); 235 void virtio_gpu_reset(VirtIODevice *vdev); 236 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd); 237 void virtio_gpu_update_cursor_data(VirtIOGPU *g, 238 struct virtio_gpu_scanout *s, 239 uint32_t resource_id); 240 241 /* virtio-gpu-3d.c */ 242 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, 243 struct virtio_gpu_ctrl_command *cmd); 244 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g); 245 void virtio_gpu_virgl_reset(VirtIOGPU *g); 246 int virtio_gpu_virgl_init(VirtIOGPU *g); 247 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g); 248 249 #endif 250